WO1982002276A1 - Circuit de detection de cellules de memoire mortes multi-bits - Google Patents

Circuit de detection de cellules de memoire mortes multi-bits Download PDF

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Publication number
WO1982002276A1
WO1982002276A1 PCT/US1980/001723 US8001723W WO8202276A1 WO 1982002276 A1 WO1982002276 A1 WO 1982002276A1 US 8001723 W US8001723 W US 8001723W WO 8202276 A1 WO8202276 A1 WO 8202276A1
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WO
WIPO (PCT)
Prior art keywords
transistor means
memory
voltage
storage
output
Prior art date
Application number
PCT/US1980/001723
Other languages
English (en)
Inventor
Corp Mostek
Original Assignee
Jiang Ching Lin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiang Ching Lin filed Critical Jiang Ching Lin
Priority to PCT/US1980/001723 priority Critical patent/WO1982002276A1/fr
Publication of WO1982002276A1 publication Critical patent/WO1982002276A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells

Definitions

  • This invention relates to read only memories, and more particularly to a multi-bit read only memory cell sensing circuit.
  • Such a sensing circuit must be simple in construction and operation to complement the advantages of multi-bit read only memory cells.
  • a sensing circuit for use with a multi-bit read only memory cell.
  • a multi-bit read only memory having a plurality of storage transistors, each having drain, source and gate terminals, arranged to form rows and columns is provided.
  • Each of the plurality of storage transistors has a predefined permanent threshold voltage.
  • the gate terminals of a row of the plurality of storage transistors are each connected to a common word line input.
  • the source terminals of a column of the plurality of storage transistors are each connected to a common bit line.
  • the drain terminals of the plurality of storage transistors are connected to a common reference voltage source.
  • a plurality of reference transistors is provided, each having drain, source and gate terminals arranged into rows and columns. Each of the plurality of reference transistors has a predefined permanent threshold voltage.
  • the gate terminals of a row of the plurality of reference transistors are each connected to one of the common word lines associated with a row of the plurality of storage transistors.
  • the source terminals of a column of the plurality of reference transistors are connected to a source voltage supply, and the drain terminals of the plurality of reference transistors are connected to a common reference voltage source.
  • Circuitry is further provided for selectively comparing the output voltage of ones of the plurality of reference transistors to the output voltage of the plurality of storage transistors to thereby determine the voltage level stored in each of the plurality of storage transistors.
  • the read only memory (ROM) cell sensing circuit of the present invention is illustrated and is generally identified by the numeral 10 " .
  • Sensing circuit 10 is illustrated in FIGURE 1 as only a portion of an array of numerous such ROM memory cells arranged in rows and columns in a conventional manner to form a read only memory.
  • the ROM thereby formed using the present sensing circuit 10 may be fabricated on a single semiconductor chip and is primarily intended for such fabrication utilizing metal-oxide-semiconductor technology.
  • the memory cells When arranged in an array of memory cells, the memory cells are disposed in columns and connected to bit lines 20 and 22 and column lines 24 and 26. Since memory cells are typically disposed in separate rows of a read only memory, the rows are addressed or enabled by separate word lines, such as word line 28. Word line 28 enables all memory cells in one row of the read only memory.
  • memory storage transistors 30, 32, 34 and 36 Interconnected to word line 28 are memory storage transistors 30, 32, 34 and 36 each having gate, drain and source terminals forming storage cells.
  • Memory storage transistors 30, 32, 34 and 36 are representative of numerous other such storage transistors interconnected to word line 28.
  • the gate terminals of storage transistors 30, 32, 34 and 36 are each connected to word line 28.
  • the respective source terminals are connected to either of bit lines 20 or 22.
  • the respective drain terminals are connected to either of column lines 24 or 26.
  • Each of storage transistors 30, 32, 34 and 36 are capable of having different ion implantations to establish threshold levels of, for example, .5, 2.5, 5 and 8 volts.
  • Each memory cell of the ROM therefore, has the capability of storing multi-level or multi-bit data within a single memory cell.
  • the sensing circuit for determining the voltage level stored within the cells formed by storage transistors 30, 32, 34 and 36 includes reference transistors 40, 42 and 44 each having gate, source and drain terminals.
  • the reference transistors 40, 42 and 44 are provided for each word line of the ROM and, as illustrated in FIGURE 1, are provided for word line 28. Similarly, a set of reference cells is provided for each word line of the ROM utilizing the present sensing circuit 10.
  • the source terminal of reference transistor 40 is interconnected to a reference data line 48.
  • the drain terminal of reference transistor 40 is interconnected to a reference column line 50 at ground potential.
  • the drain terminal of reference transistor 42 is interconnected to a reference column line 52.
  • the source terminal of reference transistor 42 and the source terminal of reference transistor 44 are interconnected to a reference data line 54.
  • the drain terminal of reference transistor 44 is interconnected to a reference column line 56.
  • the threshold levels of reference transistors 40, 42 and 44 may be established at, for example, .5, 2.5 and 5 volts, respectively.
  • Source voltage supply, cc . is applied to precharge transistors 60, 62, 64, 66, 68, 70, 72 and 74.
  • the gates of precharge transistors 60, 62, 64, 66, 68, 70, 72 and 74 receive the PC, precharge signal, to be subsequently described with reference to FIGURE 2.
  • Precharge transistor 60 precharges reference data line 48.
  • Precharge transistor 68 precharges reference column line 52.
  • Precharge transistor 64 precharges reference data line 54.
  • Precharge transistor 66 precharges reference column line 56.
  • Precharge transistor 68 precharges bit line 20.
  • Precharge transistor 70 precharges column line 24.
  • Precharge transistor 72 precharges bit line 22.
  • Precharge transistor 74 precharges column line 26. All bit lines, column lines, reference column lines and reference data lines are precharged to a value of V less one threshold.
  • Reference column lines 52 and 56 are activated to provide a ground voltage potential to the drains of reference transistors 42 and 44 by actuation of transistors 80 and 82.
  • the gate of transistor 80 is activated by an address change to the ROM by detecting a one bit change in the address. This one bit change, designated as the most significant bit
  • MSB is applied in one of two states, MSB and MSB to transistors 80 and 82, respectively.
  • the MSB address bit also controls the voltage level on word line 28.
  • MSB is a logic high, the voltage on word line 28 is bootstrapped to a value greater than V , for example, 8 volts.
  • MSB is a logic low, the voltage on word line 28 is at V , for example, 5 volts.
  • An important aspect of the present sensing circuit 10 is the use of this multi-level word line addressing scheme for determining the value of data stored within storage transistors 30, 32, 34 and 36.
  • the present sensing circuit 10 functions to compare each of the threshold voltage levels stored in the reference cells formed by reference transistors 40, 42 and 44 to each of the cells formed by storage transistors 30, 32, 34 and 36.
  • Four voltage level thresholds can be determined using a minimum number of three reference cells, 40, 42 and 44.
  • This comparison is made by a pair of differential amplifiers associated with each storage transistor 30, 32, 34 and 36. Illustrated in FIGURE 1, for simplicity of illustration, are two such pairs of differential amplifiers associated with storage transistors 30 and 32.
  • Associated with storage transistor 30 are differential amplifiers 100 and 102.
  • differential amplifiers 104 and 106 Associated with storage transistor 32 are differential amplifiers 104 and 106. It is understood that associated with storage transistor 34 are similarly configured differential amplifiers 100 and 102 and associated with storage transistor 36 are similarly configured differential amplifiers 104 and 106. Each differential amplifier 100, 102, 104 and 106 includes three transistors identified by the suffix "a", "b" and "c". Differential amplifiers 100 and 102 are connected in parallel across storage transistor 30 as are differential amplifiers 104 and 106, being connected in parallel across storage transistor 32. It therefore can be seen that only two differential amplifiers for each storage transistor are necessary in the present sensing circuit 10.
  • the source terminal of storage transistor 30 is interconnected to the gate terminals of transistors 100a and 102a.
  • the drain terminal of storage transistor 30 and drain terminal of storage transis ' tor 32 are connected by column line 24 to the drain terminals of transistors 100c, 102c, 104c and 106c.
  • the differential input to differential amplifier 100 is applied to the gate terminal of transistor 100b via reference data line 54.
  • the differential input to differential amplifier 102 is applied to the gate terminal of transistor 102b via reference data line 48.
  • the differential input to differential amplifier 104 is applied to the gate terminal of transistor 104b from reference data line 54.
  • the differential input to differential amplifier 106 is applied to the gate terminal of transistor 106b via reference data line 48.
  • the outputs of differential amplifier 100 are applied from the source terminal of -transistor 100a via an output ⁇ line Dl, 110, and from the source terminal of transistor 100b via an output line ⁇ 5X, 112.
  • the outputs of differential amplifier 102 are applied from the source terminal of transistor 102a via output line Dl' , 114, and from the source terminal of transistor 102b via output line Dl 1 , 116.
  • the outputs of differential amplifier 104 are applied from the source terminal of transistor 104a to an output line D2, 118, and from the source terminal of transistor 104b via an output line 1)2., 120.
  • the outputs of differential amplifier 106 are applied from the source terminal of transistor 106a via an output line D2' , 122, and via the source terminal of transistor 106b via an output line D2', 124.
  • the output of flip-flop circuit 130, D ⁇ is applied via signal line 134 to a NOR circuit 136 which generates the DATA signal.
  • the DATA signal represents the decoded output of differential amplifiers 100 and 102 to provide the data value stored within a particular storage transistor 30.
  • the output of flip-flop circuit 132, Dl' is applied to an AND circuit 138 which also receives the MSB, most significant bit, from the address to the random access memory.
  • the output of AND circuit 138 is applied to NOR circuit 136.
  • Applied to column line 24 through a transistor 150 is the CD, column decode, signal which, as will subsequently be described with respect to FIGURE 2, provides a ground voltage potential to column line 24.
  • capacitors 152 and 154 Interconnected to reference data lines 48 and 54 are capacitors 152 and 154 which provide a delay for the application of the signals on reference data lines 48 and 54 to differential amplifiers 102, 106 and 100, 104, respectively.
  • the value of the' threshold voltage of reference transistors 40 • nd 42 or reference transistors 40 and 44 are each compared to the voltage level stored in each of the storage transistors 30, 32, 34 and 36 to determine the value actually stored within these storage cells.
  • the output of reference transistor 40 is always applied to differential airiplifiers 102 and 106.
  • the determination of whether the output of reference cells 42 or 44 will be applied to differential amplifiers 100 and 104 via reference data line 54 is determined by the state of address to the read only memory by changing the MSB.
  • the presence of MSB applied to the gate terminal of transistor 80 applies the output of reference transistor 42 via reference data line 54 to differential amplifiers 100 and 104.
  • the presence of the MSB signal from the address to the read only memory, applied to the gate terminal of transistor 82 permits the output of reference transistor 44 to be delayed by capacitor 154 and applied via reference data line 54 to differential amplifiers
  • the differential input to differential amplifiers 100 and 102 is applied from storage transistor 30 by supplying a ground reference potential to the drain terminal of storage transistor 30 via column line 24. This ground reference potential is also supplied to the "* r__vde formed between transistors 100c and 104c of differential amplifiers 100 and 104 and the node formed
  • Storage transistor 30 will then, in turn, supply data on bit line 20 for application to differential amplifiers 100 and 102. Because column line 24 is shared between storage transistors 30 and 32, . ' • storage transistor 32 provides its data on bit line 22 for application to differential amplifiers 104 and 106. •. " Therefore, it can be seen that storage transistors 30 and:: 32 are read simultaneously to thereby read two memory ' ' . cells at once.
  • the rate at which the differential inputs are " applied to each of the differential amplifiers 100, 102, 104 and 106 will determine the state of the output signal of each of the differential amplifiers 100, 102, 104 and 106, which indicates the V_. of a storage transistor..-
  • These output signals are applied via flip-flop circuits ' 130 and 132 to NOR circuit 136 and AND circuit 138 which decode the differential outputs to provide the data value of the voltage stored within storage cells 30, 32, 34 and 36.
  • the present sensing circuit 10 operates in a two page mode, such that two levels or pages of data can be stored within each memory transistor 30, 32, 34 and 36. In page one mode, the MSB signal is a logic low to place word line 28 at the level of V cc .
  • word line 28 is bootstrapped such that the voltage level on word line 28 is bootstrapped above V cc when the MSB signal is high.
  • the logic outputs of differential amplifiers 100 and 102, Dl and Dl', and the DATA signal for the page two mode of operation are indicated in Table 2 below.
  • ⁇ 30 for page one is a logic 1 and at page two is a logic 0.
  • FIGURE 2a illustrates the voltage level of the precharge • * signal, PC
  • FIGURE 2b illustrates the voltage waveform . ' . present on column lines 24 and 26
  • FIGURE 2c illustrates • the voltage level of the CD signal
  • FIGURE 2d illustrates the voltage level of word line 28
  • FIGURE 2e illustrates the voltage level of word line 28
  • bit lines 20 and 22 are precharged using the PC signal (FIGURE 2a) to a high voltage level of V less one threshold (FIGURE 2e) .
  • the column lines 24 and 26 are precharged using the PC signal (FIGURE 2a) to a high voltage level of V less one threshold (FIGURE 2e) .

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

Circuit de detection de memoire morte multi-bits (10). Une pluralite de transistors de stockage (30, 32, 34, 36) sont disposes en rangees (28) et en colonnes (20, 22) et ont chacun une tension de seuil permanente predeterminee. Une pluralite de transistors de reference (40, 42, 44) sont prevus. Un reseau de circuits (100, 102, 104, 106) est prevu pour comparer selectivement la tension de sortie de transistors de la pluralite de transistors de reference (40, 42, 44) par rapport a la tension de sortie de la pluralite de transistors de stockage (30, 32, 34, 36) pour determiner le niveau de tension stockee dans chaque transistor de la pluralite de transistors de stockage (30, 32, 34, 36).
PCT/US1980/001723 1980-12-24 1980-12-24 Circuit de detection de cellules de memoire mortes multi-bits WO1982002276A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US1980/001723 WO1982002276A1 (fr) 1980-12-24 1980-12-24 Circuit de detection de cellules de memoire mortes multi-bits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/US1980/001723 WO1982002276A1 (fr) 1980-12-24 1980-12-24 Circuit de detection de cellules de memoire mortes multi-bits
WOUS80/01723801224 1980-12-24

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WO1982002276A1 true WO1982002276A1 (fr) 1982-07-08

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984000840A1 (fr) * 1982-08-16 1984-03-01 Ncr Co Comparateur d'impedance permettant la detection d'une memoire morte
EP0136119A2 (fr) * 1983-09-16 1985-04-03 Fujitsu Limited Circuit de mémoire morte à cellules multi-bits
WO1990016069A1 (fr) 1989-06-12 1990-12-27 Kabushiki Kaisha Toshiba Dispositif memoire a semi-conducteur
US5764571A (en) * 1991-02-08 1998-06-09 Btg Usa Inc. Electrically alterable non-volatile memory with N-bits per cell

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU514347A1 (ru) * 1974-07-02 1976-05-15 Специальное Конструкторское Бюро Систем Промышленной Автоматики Аналоговое запоминающее устройство
US4090257A (en) * 1976-06-28 1978-05-16 Westinghouse Electric Corp. Dual mode MNOS memory with paired columns and differential sense circuit
US4179626A (en) * 1978-06-29 1979-12-18 Westinghouse Electric Corp. Sense circuit for use in variable threshold transistor memory arrays
US4181865A (en) * 1977-04-28 1980-01-01 Tokyo Shibaura Electric Co., Ltd. Sensing circuit for a multi-level signal charge
US4192014A (en) * 1978-11-20 1980-03-04 Ncr Corporation ROM memory cell with 2n FET channel widths
US4202044A (en) * 1978-06-13 1980-05-06 International Business Machines Corporation Quaternary FET read only memory

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU514347A1 (ru) * 1974-07-02 1976-05-15 Специальное Конструкторское Бюро Систем Промышленной Автоматики Аналоговое запоминающее устройство
US4090257A (en) * 1976-06-28 1978-05-16 Westinghouse Electric Corp. Dual mode MNOS memory with paired columns and differential sense circuit
US4181865A (en) * 1977-04-28 1980-01-01 Tokyo Shibaura Electric Co., Ltd. Sensing circuit for a multi-level signal charge
US4202044A (en) * 1978-06-13 1980-05-06 International Business Machines Corporation Quaternary FET read only memory
US4179626A (en) * 1978-06-29 1979-12-18 Westinghouse Electric Corp. Sense circuit for use in variable threshold transistor memory arrays
US4192014A (en) * 1978-11-20 1980-03-04 Ncr Corporation ROM memory cell with 2n FET channel widths

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984000840A1 (fr) * 1982-08-16 1984-03-01 Ncr Co Comparateur d'impedance permettant la detection d'une memoire morte
EP0136119A2 (fr) * 1983-09-16 1985-04-03 Fujitsu Limited Circuit de mémoire morte à cellules multi-bits
EP0136119A3 (en) * 1983-09-16 1985-10-02 Fujitsu Limited Plural-bit-per-cell read-only memory
WO1990016069A1 (fr) 1989-06-12 1990-12-27 Kabushiki Kaisha Toshiba Dispositif memoire a semi-conducteur
EP0477369A1 (fr) * 1989-06-12 1992-04-01 Kabushiki Kaisha Toshiba Dispositif memoire a semi-conducteur
EP0477369A4 (fr) * 1989-06-12 1995-03-22 Tokyo Shibaura Electric Co
US5450361A (en) * 1989-06-12 1995-09-12 Kabushiki Kaisha Toshiba Semiconductor memory device having redundant memory cells
US5764571A (en) * 1991-02-08 1998-06-09 Btg Usa Inc. Electrically alterable non-volatile memory with N-bits per cell
US6104640A (en) * 1991-02-08 2000-08-15 Btg International Inc. Electrically alterable non-violatile memory with N-bits per cell
US6243321B1 (en) 1991-02-08 2001-06-05 Btg Int Inc Electrically alterable non-volatile memory with n-bits per cell
US6339545B2 (en) 1991-02-08 2002-01-15 Btg International Inc. Electrically alterable non-volatile memory with n-bits per cell
US6343034B2 (en) 1991-02-08 2002-01-29 Btg International Inc. Electrically alterable non-volatile memory with n-bits per cell
US6344998B2 (en) 1991-02-08 2002-02-05 Btg International Inc. Electrically alterable non-volatile memory with N-Bits per cell
US6356486B1 (en) 1991-02-08 2002-03-12 Btg International Inc. Electrically alterable non-volatile memory with n-bits per cell
US6404675B2 (en) 1991-02-08 2002-06-11 Btg International Inc. Electrically alterable non-volatile memory with n-bits per cell

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