Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/213—Channel regions of field-effect devices
  • H10D62/221—Channel regions of field-effect devices of FETs
  • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
  • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
  • H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths

Definitions

• the present invention relates to- semiconductor memory devices.
• the invention is concerned in particular with semiconductor "memory devices- of the kind having a conductive substrate of one conductivity type having a channel region therein, and a charge storage gate struc ⁇ ture overlying the channel region, the gate structure including a gate electrode and having at least a memory section; hereinafter, such a device will be referred to as a semiconductor memory device of the kind specified.
• MNOS metal-nitride-oxide-semiconductor
• an MNOS NVRAM of known construction typically requires a 5 volt power supply and a ground connection.
• the nonvolatile memory portion requires a gate voltage of approximately 30 volts magni ⁇ tude for writing, and a control voltage (applied to the channel via the source or drain) of about the same magnitude.
• Reduced complexity, power dissipation and cost could be achieved by decreasing the control voltage and the gate voltage requirements so that the RAM 5 volt power supply can be used to supply the control voltage and the gate voltage.
• N-channel MNOS devices are also susceptible to channel dopant-sensitive spurious writing during channel-shielded operation.
• MNOS n-channel devices typically are adjusted to enhancement operation by implanting the substrate with p-type ions such as boron.
• a device* initially in a low threshold voltage, "0" state, will be channel-shielded and thereby prevented from writing to a "1" state when the gate is pulsed with a large positive voltage, +V, and the source is also pulsed with a positive voltage, with the substrate at ground.
• a channel is formed from the source to the drain, but the positive source voltage is applied to the channel, thereby diminishing the potential difference between the gate and the substrate and preventing writing. Consequent ly, the threshold remains at the low magnitude voltage.
• the gate is again pulsed to +V with the substrate at 0 volts, but this time the source is at, e.g., 0 volts.
• the channel potential is 0 volts and a high voltage field is present from the gate to the channel.
• negative charge tunnels from the substrate to the silicon dioxide-silicon nitride gate dielectric and is trapped therein, raising the threshold to, e.g., about +10 volts.
• the channel-shielded MNOS device is sensitive to the enhancement impurity concentration, excessive impurity concentration can cause breakdown between the channel and the substrate during the channel- shielded operation. The channel-shielded operation may then cause unwanted avalanche writing of the device to the "1" state.
• ⁇ . S. Patent No. 4,019,198 issued April 19, 1977 to Endo et al. relates to a -nonvolatile* p-channel- MNOS semiconductor memory device having " a high concentration impurity layer of the same conductivity type as the substrate surrounding the source and/or the drain.
• the aim of -the patent is to - - -- use avalanche writing caused by the impurity layer to provide relatively low write voltages and a large threshold window.
• the device includes a substrate of a first conductivity type (p ) , and a source and drain of the second conductivity type (n) which are connected by a permanent channel (n) to form a depletion mode structure.
• a highly doped layer of the first conductivity type (p+) underlies the permanent channel. This channel is separated from the gate electrode by a dual dielectric, including a relatively thick 75 Angstrom memory oxide.
• the Christie device is written to a "1" state by applying a +18 volt signal through the gate with the source and drain at +10 volts and the substrate at ground. These voltages cause avalanche breakdown of the pn junction between the n-channel and the doped p- layer and thereby inject hot electrons into the dielectric to write the device to a reported threshold of approximately 10 volts. Applying +18 volts to the gate with the source, drain and substrate at ground erases the device.
• the present invention provides a semiconductor memory device having a conductive substrate of one con- ductivity type having a channel region therein, and a charge storage gate structure overlying the channel re ⁇ gion, the gate structure including a gate electrode and having at least a memory section, characterized by means for providing avalanche writing of the device upon ap- plication of suitable voltages to the channel region and the gate electrode, which means comprise a first sub ⁇ strate region having a first, relatively high concentra ⁇ tion of said one conductivity type providing impurities disposed beneath the memory section of the gate struc- ture, and a second substrate region beneath the first region and having a second, relatively low concentration of said one conductivity type providing impurities.
• said first sub- strate region has an impurity concentration of at least 10 17/cm3 and a thickness of less than one micron.
• a semiconductor memory device in accordance with a preferred embodiment of the invention comprises a p type substrate having a spaced apart n type source and drain which define a channel region.
• the device has a charge storage gate structure, typically a nitride- oxide charge storage insulator, overlying the channel; and a p+p- junction in the substrate.
• the p+p- struc ⁇ ture includes a first, p+ conductivity type, region be- tween the source and drain in the channel region de ⁇ fined by the thin-oxide memory structure and a second, p- region which constitutes the substrate resistivity beneath the first region.
• the binary state of the device is selected by applying a low voltage (e.g.
• the invention is applicable to p channel enhancement structures also.
• the first and second junction-forming layers are n+n- and the gate and source/drain write voltages are negative.
• Figs. 1 and 4 are cross-sectional views of alternative embodiments of a low voltage write, avalanche breakdown nonvolatile MNOS memory device in accordance with the present invention
• Fig. 2 is an enlarged cross-sectional view of the memory area of the device of Fig. 1; and *
• Figs. 3 and 5 show plots of the threshold voltage of the devices of Fig. 1 and Fig. 4, respectively, as a function of the channel shielding voltage, V ⁇ , at a gate voltage of +12 volts.
• Fig. 1 is a cross-sectional view taken parallel to the channel of a low voltage write, avalanche breakdown MNOS field effect transistor 10 embodying the principles of the present invention.
• the transistor 10 is exemplary of a class of devices which embody the principles of the present invention.
• the transistor 10 comprises a substrate 11 ⁇ Of-'One--co ductivi y- -type (illustratively p- type) within which are spaced-apart surface-adjacent, channel-defining source and drain regions 12 and 13 of the second, opposite-conductivity type ( ⁇ -type) .
• a thick insulating layer 16, typically of silicon dioxide, is forme on the substrate 11 to prevent field inversion and electric ally isolate the device 10.
• a gate structure comprising a layered dual insulator and a gate electrode 21 overlies the channel region between the source 12 and the drain 13.
• the gate electrode is any suitable conductive material such as aluminum, aluminum-silicon, or polysilicon.
• the insulator i structure in the memory region comprises a relatively thin silicon dioxide layer 18 of about 10-60 Angstroms thickness (.1-6 nanometers, n ) for permitting charge transfer between the substrate and the gate, and' silicon nitride layer 19 of about 350 to 450 Angstroms thickness (35-45 nm) .
• the silicon dioxide layer includes at least one of thick portions 31 and 32 which are formed at the sides of the memory oxide 18 adjacent the source and/or the drain.
• the portions 31 and 32 are relatively thick (e.g., about 400 Angstroms, 40 nm) to hinder charge transfer between 31 or 32 and the substrate and thereby to prevent memory operation of the underlying channel portion.
• These non-memory oxide portions 31 and 32 can be placed at either the source or the drain side of the memory oxide 18 or both to control the "0" state threshold voltage and to increase gate modulated junction breakdown between the source and substrate and/or the drain and substrate, respectively.
• the resulting "split gate” and “trigate” structures are described more fully in U.S.
• Patent 3,719,866 issued to Naber and Lockwood and assigned to NCR Corporation.
• electrical contacts 22, 23, 24 and 26 are shown connected to the gate 21, source 12, drain 13, and substrate 11, respectivel for applying bias voltages which control the conduction path and current across the channel region.
• this particular electrical contact arrangement is shown merely to facilitate description: for example, contact to the source and drain junctions is usually made at a single point along each of a pair of diffusion stripes which comprise the source and the drain for a-plurality of devices.
• Fig. 1 illustrates a primary feature of the present invention: the provision of a low voltage write, enhancement type memory device which is of relatively simple construction and can be fabricated in a simple fashion. This can be accomplished by suitably doping the .channel region under the non-memory portions of the tri-gate structure.
• transistor 10 regions 31 and 32 with p type impurities to yield a fixed enhancement, non-memory threshold voltage (VNM) of, for example, approximately +1V, and by adjusting the p type impurity concentration in the memory channel region 33 such that a "0" state threshold voltage VT0 _ ⁇ approximately +1V and a "1" state threshold voltage VTl >> +1V can be obtained through proper voltage biasing of the memory device.
• VNM non-memory threshold voltage
• OMPI region to approximately 500-700 A°.
• a p+ dopant concentration of at least about 10 18/cm3 this occurs with about 3V across the depletion region, at which time the substrate silicon in the depleted p+ region. undergoes avalanche breakdown. Hot electron carriers are generated by the avalanche breakdown and injected into the gate insulator 18-19 by the potential difference between the gate electrode and the channel.
• the negative charge is trapped and stored at the interface between the memory oxide 18 and the nitride 19 as well as in the nitride bulk, upon removal of the write voltages it is found that the threshold voltage of the memory device has shifted to a more positive value by virtue of the trapped negative charge.
• the device can be maintained in the erased state or written to a relatively high positive threshold voltage state.
• the present invention uses the channel shielding technique described in the Background Art (i.e., voltages of the same po ⁇ larity are applied to the gate and to the source or drain) , but uses the technique to avalanche write the
• channel- shielded write refers to the application of channel shielding techniques to write, rather than to prevent writing.
• Transistor 10 was fabricated using conventional processing techniques. The aim, based upon the above- described theory, was to achieve a low write voltage of
• the substrate 11 was silicon, doped with boron to a p type background concentration of 10
• a gate oxide of about 400 Angstroms thickness (40 nm) was formed over the channel within thick field oxide 16 (which was about 1.0 micron in thickness) prior to formation of the substrate region 27.
• the channel was then implanted through the 400 A° oxide using boron at 60 keV and a dose of 5x10 11/cm2. (Note: this implantation step does not complicate the process, since this low dose (5x10 11/cm2) implant is also used to set- the threshold voltage of peripheral non-memory gates) .
• the memory gate was doped by implanting boron atoms at a dose of 3x10 13 atoms per square centimeter and an energy of about 30 keV through the 400 Angstrom (40 nm) gate silicon dioxide into the substrate silicon beneath the memory region 33.
• the non-memory regions 31 and 32 and the substrate regions beneath regions 31 and 32 were protec ⁇ ted from the memory doping by a previously applied photo ⁇ resist coating layer which was photolithographically patterned in such a way that the photoresist was removed only in the memory channel region 33.
• the implantation resulted in a p+ layer 27 about 1500 A° in thickness with an average boron doping concentration of about 2xl0 18 /cm 3 .
• the silicon dioxide in the memory region was etched away using buffered hydrofluoric acid, the photoresist was stripped and the memory silicon dioxide layer 18 was thermally grown to a thickness of about 20 A° in an oxygen atmosphere and at a- temperature of about 600°C.
• Approximately 400 A° of silicon nitride 19 was then deposited over the entire structure by chemical vapor deposition using silane and ammonia reactants. Source, drain and substrate contact holes were defined using hot phosphoric acid (to etch the nitride) and buffered hydrofluoric acid (to etch the oxide).
• An aluminum film (1.0 micron) was then deposited over the surface of the wafer in a metal evaporation system.
• the gate (21), source (23) and drain (24) electrodes were subsequently- formed using standard photolithographic techniques .
• the resultant structure comprises a tri-gate memory device 10.
• the resulting cross-section of the memory portion of transistor 10 is shown schematically in Fig. 2.
• the gate structure comprises a thin silicon dioxide dielectric layer 18 which is 20 A 0 thick; a silicon nitride dielectric layer 19 which is 400 A° thick; and a 1.0 micron thick aluminum gate electrode 21.
• the doping profile resulting from the ion implantation into the p-type 10 15/cm3- substrate background doping is an approximately 1500 A° thick p+ layer 27 of approxi- ately 2x10 18/cm3 boron concentration.
• the gate voltage is not limited to +12 volts, for voltages either smaller than or larger than +12V can be used. Those skilled in the art will appreciate that below +12 volts, the decreased potential difference between the gate and the channel decreases writing efficiency. However, it is possible to decrease the gate voltage and achieve adequate trans- fer of the charge carriers into the gate dielectric for writing.
• the state of the memory transistor 10 can be sensed by grounding the source electrode 12 and the substrate 11, applying a positive voltage to the drain 13, and applying a positive voltage to the gate 21.
• a gate voltage intermediate the values of the erased and written thresholds, i.e., between VT0 and VT1
• the drain current will be an indicator of the binary state of the memory transistor.
• split gate embodiment of the low voltage write FET 10 which comprises a memory section 33 and only one of the non-memory sections 31 or 32, is readily formed.
• the split gate transistor is formed using the aforementioned process for the FET 10 and adjusting the masks used in the memory gate deposition and memory oxide formation steps to form the memory section 33 at one..end. o£.the..channel,.adjacent the source- or drain and to form an adjacent, non-memory section at the opposite end of the channel adjacent the drain or source.
• the aforementioned process is modified, in pertinent part, by using a memory gate implantation mask which exposes the desired memory region adjacent the source and protects .the non-memory region adjacent the.drain.
• the memory gate implant thus forms p+ region 27 adjacent the source under memory region 33.
• the previously- formed thick (about 400 Angstroms) non-memory silicon dioxide gate layer is etched away in the translated memory region 33 (using the gate implantation mask) and the thin memory oxide is grown in the memory region 3
• FIG. 4 shows an embodiment of the invention in the form of a pure memory device, that is, a FET 40- in which the memory oxide spans the channel length, i.e. neither of the non-memory oxide sections 31 and 32 is present.
• the thick 400 A° (non- memory) gate oxide is formed over the channel region; a memory gate implant mask is used which exposes the entire channel length to the implant so that the resulting p+ region 27 spans the channel length; the non-memory oxide is then removed along the length of the channel; and the memory oxide is grown spanning the length of the channel.
• Fig. 5 presents the low voltage write character ⁇ istics of a pure memory device 40 which was formed using the same parameters" as the exemplary FET 10, with the above-listed adjustments in the memory gate masks. As shown, writing was initiated for a V_ value of about +2 to +3 volts, which again is within the predicted range of silicon avalanche breakdown voltage values of . +1 to +4 volts for a p+ doping concentration of the order of 10 18/cm3.
• the data indicated that not only are the control voltage and the write gate voltage requirements low, but that these voltages can be conveniently provided by the industry standard 5 volt and 12 volt power supplies used in RAM operation.
• split gate, trigate, and pure memory MNOS alterable threshold memory transistors which can be written with low voltage.
• Each exemplary device is n-channel and depends for its operation upon the presence of a p+ type surface layer in -the- -memory channel region.
• the doping is conveniently done by ion implantation of boron or other suitable p type impurity. Writing with 0 volts on the source results in little change of threshold voltage from that of the erased state. However, if it is desired to write the device, the source (or drain) is set above approximately +1 to +4 volts. Conveniently, the source can be set to the 5 volt level used in RAM power supplies. This induces avalanche breakdown of the silicon substrate in the depleted portion of the p+ layer in the memory channel. Hot electron carriers are generated which are injected into the memory gate insulator.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Non-Volatile Memory (AREA)
• Arrangements For Transmission Of Measured Signals (AREA)
• Time-Division Multiplex Systems (AREA)
• Selective Calling Equipment (AREA)

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Citations (6)

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• 1979
  • 1979-11-26 WO PCT/US1979/001025 patent/WO1980001122A1/en not_active Application Discontinuation
  • 1979-11-26 JP JP50018479A patent/JPS55500965A/ja active Pending
• 1980
  • 1980-06-03 EP EP19800900104 patent/EP0020708A4/en not_active Withdrawn

Patent Citations (6)

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