UST892019I4 - Semiconductor integrated circuit with isolated elements and power transistor utilizing substrate "for low collector resistance - Google Patents

Semiconductor integrated circuit with isolated elements and power transistor utilizing substrate "for low collector resistance Download PDF

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Publication number
UST892019I4
UST892019I4 US892019DH UST892019I4 US T892019 I4 UST892019 I4 US T892019I4 US 892019D H US892019D H US 892019DH US T892019 I4 UST892019 I4 US T892019I4
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United States
Prior art keywords
power transistor
integrated circuit
substrate
collector resistance
semiconductor integrated
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Publication of UST892019I4 publication Critical patent/UST892019I4/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H01L27/0825—Combination of vertical direct transistors of the same conductivity type having different characteristics,(e.g. Darlington transistors)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion

Definitions

  • a substrate preferably of low resistivity, can serve as a collector contact region of a power transistor as Well as a support for other functional elements of an integrated circuit.

Abstract

A SUBSTRATE, PREFERABLY OF LOW RESISTIVITY, CAN SERVE AS A COLLECTOR CONTACT REGION OF A POWER TRANSISTOR AS WELL AS A SUPPORT FOR OTHER FUNCTIONAL ELEMENTS OF AN INTEGRATED CIRCUITS. AN EPITAXIAL LAYERS ON THE SURFACE OF THE SUBSTRATE, OF THE SAME CONDUCTIVITY TYPE BUT HIGHER RESISTIVITY, CONTAINS OTHER REGIONS OF FUNCTIONAL ELEMENTS. ISOLATION MEANS SUCH AS PN JUNCTION FORMING REGIONS OR DIELECTRIC MATERIAL, UNDERLIES AND ENCLOSES THOSE PORTIONS OF THE EPITAXIAL LAYER TO BE ISOLATED. MINIMAL COLLECTOR RESISTANCE AND INCREASED POWER HANDLING CAPABILITY CAN BE OBTAINED WITH THE POWER TRANSISTOR STRUCTURE WITHOUT SACRIFICING ISOLATION OR COMPLICATING FABRICATION.

Description

DEFENSIVE PUBLICATION UNITED STATES PATENT OFFICE Published at the request of the applicant or owner in accordance with the Notice of Dec. 16, 1969, 869 O.G. 687. The abstracts of Defensive Publication applications are identified by distinctly numbered series and are arranged chronologically. The heading of each abstract indicates the number of pages of specification, including claims and sheets of drawings contained in the application as originally filed. The files of these applications are available to the public for inspection and reproduction may be purchased for 30 cents asheet.
Defensive Publication applications have not been examined as to the merits of alleged invention. The Patent Oillcc makes no assertion as to the novelty of the disclosed subject matter.
PUBLISHED NOVEMBER 30, 1971 892 O.G. 160a T892,019 SEMICONDUCTOR INTEGRATED CIRCUIT WITH ISOLATED ELEMENTS AND POWER TRANSIS- TOR UTILIZING SUBSTRATE FOR LOW COLLEC- TOR RESISTANCE Edgar A. Sack, 48 St. Andrews St, Severna Park, Md. 21146 Filed Jan. 27, 1969, Ser. No. 794,046 Int. Cl. H011 19/00 US. Cl. 317-235 1 Sheet Drawing. 8 Pages Specification "allrnww zewnuwnanmywws via-u IIIIIIIII/III/I/I/IIIlI/III/III.
A substrate, preferably of low resistivity, can serve as a collector contact region of a power transistor as Well as a support for other functional elements of an integrated circuit. An epitaxial layer on the surface of the substrate, of the same conductivity type but higher resistivity, contains other regions of functional elements. Isolation means such as PN junction forming reg-ions or dielectric material, underlies and encloses those portions of the epitaxial layer to be isolated. Minimal collector resistance and increased power handling capability can be obtained with the power transistor structure without sacrificing isolation or complicating fabrication.
US892019D 1969-01-27 1969-01-27 Semiconductor integrated circuit with isolated elements and power transistor utilizing substrate "for low collector resistance Pending UST892019I4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US79404669A 1969-01-27 1969-01-27

Publications (1)

Publication Number Publication Date
UST892019I4 true UST892019I4 (en) 1971-11-30

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Family Applications (1)

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US892019D Pending UST892019I4 (en) 1969-01-27 1969-01-27 Semiconductor integrated circuit with isolated elements and power transistor utilizing substrate "for low collector resistance

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US (1) UST892019I4 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461253A (en) * 1988-09-30 1995-10-24 Nippon Steel Inc. Semiconductor substrate structure for producing two isolated circuits on a same substrate
USRE35642E (en) * 1987-12-22 1997-10-28 Sgs-Thomson Microelectronics, S.R.L. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
US5688702A (en) * 1988-02-08 1997-11-18 Kabushiki Kaisha Toshiba Process of making a semiconductor device using a silicon-on-insulator substrate
USRE36311E (en) * 1987-12-22 1999-09-21 Sgs-Thomson Microelectronics, S.R.L. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE35642E (en) * 1987-12-22 1997-10-28 Sgs-Thomson Microelectronics, S.R.L. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
USRE36311E (en) * 1987-12-22 1999-09-21 Sgs-Thomson Microelectronics, S.R.L. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
US5688702A (en) * 1988-02-08 1997-11-18 Kabushiki Kaisha Toshiba Process of making a semiconductor device using a silicon-on-insulator substrate
US5461253A (en) * 1988-09-30 1995-10-24 Nippon Steel Inc. Semiconductor substrate structure for producing two isolated circuits on a same substrate

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