UST100501I4 - Integrated circuit layout utilizing separated active circuit and wiring regions - Google Patents

Integrated circuit layout utilizing separated active circuit and wiring regions Download PDF

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Publication number
UST100501I4
UST100501I4 US06/058,360 US5836079A UST100501I4 US T100501 I4 UST100501 I4 US T100501I4 US 5836079 A US5836079 A US 5836079A US T100501 I4 UST100501 I4 US T100501I4
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US
United States
Prior art keywords
insulating layer
apertures
sets
exposed
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US06/058,360
Inventor
John Balyoz
Algirdas J. Gruodis
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Individual
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Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Individual filed Critical Individual
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Publication of UST100501I4 publication Critical patent/UST100501I4/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/901—Masterslice integrated circuits comprising bipolar technology
    • H10W20/40—
    • H10W20/43—

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In the method for fabricating a semiconductor substrate integrated circuit layout including: forming a plurality of spaced-apart circuit cells in columnar arrays within said substrate; forming a first insulating layer above said substrate, said layer having apertures therein to expose selected active regions of said selected cells; the improvement comprising: depositing first and second sets of elongated conductors in substantially parallel relationship atop said first insulating layer in said columnar direction; said first set being disposed directly atop said exposed cells to make selected contact with selected ones of said exposed active regions through said apertures in said first insulating layer; said second set being disposed in areas between said exposed cells; forming a second insulating layer above said first and second sets of conductors, said second insulating layer having apertures therein to expose selected ones of said first and second sets; and depositing a third set of substantially parallel, elongated conductors atop said second insulating layer, orthogonally with respect to said columnar direction, to make selected contact with said exposed ones of said first and second sets through said apertures in said second insulating layer.
US06/058,360 1977-09-06 1979-07-17 Integrated circuit layout utilizing separated active circuit and wiring regions Pending UST100501I4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US83071577A 1977-09-06 1977-09-06

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US83071577A Continuation 1977-09-06 1977-09-06

Publications (1)

Publication Number Publication Date
UST100501I4 true UST100501I4 (en) 1981-04-07

Family

ID=25257547

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/058,360 Pending UST100501I4 (en) 1977-09-06 1979-07-17 Integrated circuit layout utilizing separated active circuit and wiring regions

Country Status (5)

Country Link
US (1) UST100501I4 (en)
EP (1) EP0001209A1 (en)
JP (1) JPS5441088A (en)
CA (1) CA1102009A (en)
IT (1) IT1110167B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4623911A (en) 1983-12-16 1986-11-18 Rca Corporation High circuit density ICs
US4748494A (en) 1985-04-19 1988-05-31 Hitachi, Ltd. Lead arrangement for reducing voltage variation
US10878158B2 (en) * 2018-07-16 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4249193A (en) * 1978-05-25 1981-02-03 International Business Machines Corporation LSI Semiconductor device and fabrication thereof
JPS55138865A (en) * 1979-04-17 1980-10-30 Nec Corp Semiconductor device
JPS55163859A (en) * 1979-06-07 1980-12-20 Fujitsu Ltd Manufacture of semiconductor device
FR2524206B1 (en) * 1982-03-26 1985-12-13 Thomson Csf Mat Tel PREDIFFUSED INTEGRATED CIRCUIT, AND METHOD FOR INTERCONNECTING CELLS OF THIS CIRCUIT
US4737836A (en) * 1983-12-30 1988-04-12 International Business Machines Corporation VLSI integrated circuit having parallel bonding areas
JPH0758761B2 (en) * 1983-12-30 1995-06-21 インターナショナル・ビジネス・マシーンズ・コーポレーション Semiconductor integrated circuit chip
EP0154346B1 (en) * 1984-03-08 1991-09-18 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
JPS6288337A (en) * 1985-10-15 1987-04-22 Nec Corp Semiconductor integrated circuit device
JP2685756B2 (en) * 1987-07-20 1997-12-03 株式会社東芝 Design method of semiconductor integrated circuit device
JPH04340252A (en) * 1990-07-27 1992-11-26 Mitsubishi Electric Corp Semiconductor integrated circuit device, arrangement and wiring method of cell

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3808475A (en) * 1972-07-10 1974-04-30 Amdahl Corp Lsi chip construction and method
CA1024661A (en) * 1974-06-26 1978-01-17 International Business Machines Corporation Wireable planar integrated circuit chip structure
US4006492A (en) * 1975-06-23 1977-02-01 International Business Machines Corporation High density semiconductor chip organization
CA1091360A (en) * 1975-12-29 1980-12-09 Takao Uehara Normalized interconnection patterns

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4623911A (en) 1983-12-16 1986-11-18 Rca Corporation High circuit density ICs
US4748494A (en) 1985-04-19 1988-05-31 Hitachi, Ltd. Lead arrangement for reducing voltage variation
US10878158B2 (en) * 2018-07-16 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same
US11409937B2 (en) 2018-07-16 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same
US11797746B2 (en) 2018-07-16 2023-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor device having more similar cell densities in alternating rows
US12086524B2 (en) 2018-07-16 2024-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having more similar cell densities in alternating rows

Also Published As

Publication number Publication date
IT7827013A0 (en) 1978-08-25
IT1110167B (en) 1985-12-23
EP0001209A1 (en) 1979-04-04
JPS5441088A (en) 1979-03-31
CA1102009A (en) 1981-05-26

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