USRE42955E1 - GaN-based permeable base transistor and method of fabrication - Google Patents

GaN-based permeable base transistor and method of fabrication Download PDF

Info

Publication number
USRE42955E1
USRE42955E1 US12/268,515 US26851504A USRE42955E US RE42955 E1 USRE42955 E1 US RE42955E1 US 26851504 A US26851504 A US 26851504A US RE42955 E USRE42955 E US RE42955E
Authority
US
United States
Prior art keywords
collector
window
metallization
base
gan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US12/268,515
Other languages
English (en)
Inventor
Liberty L. Gunter
Kanin Chu
Charles R. Eddy, Jr.
Theodore D. Moustakas
Enrico Bellotti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Information and Electronic Systems Integration Inc
Original Assignee
BAE Systems Information and Electronic Systems Integration Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BAE Systems Information and Electronic Systems Integration Inc filed Critical BAE Systems Information and Electronic Systems Integration Inc
Priority to US12/268,515 priority Critical patent/USRE42955E1/en
Application granted granted Critical
Publication of USRE42955E1 publication Critical patent/USRE42955E1/en
Adjusted expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L27/0605—
    • H01L29/0692—
    • H01L29/66454—
    • H01L29/7722—
    • H01L29/2003—
    • H01L29/32—

Definitions

  • the invention relates to transistors, and more particularly, to permeable base transistors.
  • GaN gallium nitride
  • the PBT is device very similar to the MESFET but with vertical transport instead of lateral, and has received much attention in the last quarter of a century due to its potential as a high power, high frequency, and high temperature-operating device.
  • PBTs were suggested as early as 1964, and are typically fabricated using silicon, cobalt disilicide, gallium arsenide, silicon carbide, nickel phthalocyanine, and copper phthalocyanine.
  • One embodiment of the present invention provides an etched grooved GaN-based permeable-base transistor device.
  • the device includes a GaN emitter region (e.g., having a thickness of about 6 to 10 ⁇ m) that is grown (e.g., on (0001) sapphire) using hydride vapor-phase epitaxy (HVPE). This emitter region may further include He implantation under base and collector contact pads to provide pad isolation (e.g., implant angle of about 7°).
  • the device further includes a GaN base region (e.g., having a thickness of about 1 to 2 ⁇ m) that is grown on the GaN emitter region using molecular beam epitaxy (MBE).
  • MBE molecular beam epitaxy
  • the device further includes a GaN collector region (e.g., having a thickness of about 0.1 to 0.3 ⁇ m) that has a plurality of collector fingers
  • the collector region is grown on the GaN base region using MBE.
  • the collector fingers have finger sidewall angles of about 80° to 85° for 1:1 and 1:3 finger spacing.
  • the collector region has a collector pad region and a plurality of collector fingers, wherein the collector fingers have a first height in the collector pad region and a second height out of the collector pad region, with the first and second heights configured so as to prevent disconnect between the collector fingers and the collector pad region.
  • the difference in the first and second heights could be the thickness of one layer of collector pad metal.
  • Another embodiment of the present invention provides a method for fabricating an etched grooved GaN-based permeable-base transistor device.
  • One such embodiment of the method includes seven mask levels, including: Level 1—He implant mask; Level 2—nitride isolation pad; Level 3—collector ohmic pad mask; Level 4—e-beam lithography of collector fingers for liftoff; Level 5—base recess and metallization; Level 6—emitter and device isolation etch, emitter ohmic; and Level 7—microwave test pad metal deposition. Note that not all seven masks need to be used in practicing other embodiments of the present invention.
  • FIG. 1a is a side and top perspective view of a GaN PBT device configured in accordance with an embodiment of the present invention.
  • FIG. 1b is a vertical cross sectional view of the GaN PBT device shown in FIG. 1a .
  • FIG. 2a demonstrates the material structure of a GaN PBT device configured in accordance with an embodiment of the present invention.
  • FIG. 2b illustrates various views of a GaN PBT device used to illustrate fabrication processes configured in accordance with an embodiment of the present invention.
  • FIGS. 3a through 7 illustrate a seven mask process flow for fabricating an GaN PBT and variations thereof in accordance with an embodiment of the present invention.
  • FIG. 8 is a top plan view SEM picture of a completed GaN PBT device fabricated in accordance with an embodiment of the present invention.
  • FIG. 9 (a and b) are SEM pictures showing a GaN PBT device fabricated in accordance with an embodiment of the present invention, with FIG. 9a showing a 1:1 finger pitch, and FIG. 9b a 1:3 finger pitch.
  • FIG. 10 is a graph showing a I–V characteristic curve of a GaN PBT device fabricated in accordance with an embodiment of the present invention.
  • Embodiments of the present invention provide a design and method of fabrication of an etched grooved GaN-based permeable-base transistor structure. Process flow details regarding passivation, active region dry etching, and a mask set designed for PBT fabrication are disclosed.
  • the mask set is configured to provide discrete PBT devices with a range of geometries for different frequency and power level operation, and high quality metal contacts to the various GaN layers.
  • One particular embodiment is fabricated using n-type GaN grown by hydride vapor phase epitaxy (HVPE) and molecular beam epitaxy on thick HVPE GaN quasi-substrates.
  • the fabrication process employs isolation pads via helium (He) implantation and silicon nitride (SiN) deposition, as well as sub-micron chlorine-based high density inductively coupled plasma (ICP) etching of collector fingers patterned via e-beam lithography.
  • Base Schottky contacts are deposited on the etched GaN layer prior to ohmic metal deposition so Schottky contacts on dry etched surfaces as well as low temperature annealed (0–500° C.) Schottky and ohmic contacts are characterized for their performance.
  • the resulting high power GaN PBT device has a cutoff frequency f T of about 134 GHz and a maximum frequency f max of about 500 GHz.
  • the device has a breakdown voltage of about 50V and a g m of 70 mS/mm.
  • Analysis of the device topology shows smooth etched finger structures and base layer surface with finger sidewall angles of about 80° to 85° for 1:1 and 1:3 finger spacing.
  • Specific contact resistivities of about 3 ⁇ 10 ⁇ 6 ⁇ cm 2 for the ohmic contacts were achieved with Ti/Al/Ni/Au metallization scheme.
  • GaN PBT that combines the high breakdown field of GaN and the good frequency response of a PBT.
  • Applications for use include, for example, millimeter-wave power applications.
  • etched groove there are two types of PBTs: etched groove and embedded or overgrown.
  • etched groove many submicrometer bases lay in etched grooves between ridge-like emitter contacts.
  • embedded or overgrown the base is completely buried inside the semiconductor lattice by epitaxial regrowth of the semiconductor.
  • Embodiments of the present invention are directed to the etched groove type PBT.
  • the operation of the PBT is very similar to that of the MESFET except that the PBT is a vertical device and the MESFET is a lateral carrier device.
  • the current flows perpendicular to the material surface.
  • the thickness of the grown material layers can be altered to vary the device characteristics.
  • the PBT is unipolar with a relatively short base length compared to the base length of a MESFET.
  • FIGS. 1a and 1b illustrate an etched groove PBT with metal contact configured in accordance with one embodiment of the present invention.
  • the spacing between metal fingers should be such that the two depleted zones meet (e.g., spacing between metal fingers smaller than 1 ⁇ m); and the leakage current of both base-collector and base-emitter Schottky diodes should be minimized.
  • This submicrometer-periodicity Schottky-barrier grating is used to modulate the vertical flow of electrons.
  • the top ohmic layer serves as the collector contact (on top of the device fingers).
  • the bottom and middle ohmic layers serve as the emitter and base contacts, respectively, which are deposited in two separate etched regions. Since the gate length (l g ) is defined by the thickness of the Schottky metal in the base region, l g can be realistically fabricated as smaller than 0.1 ⁇ m (the limit of most conventional transistors). Because of this, the effective channel length is mainly controlled by the depletion width towards collector and emitter.
  • the device was fabricated starting from a GaN quasi-substrates (e.g., 6 to 10 ⁇ m) grown on (0001) sapphire using a hydride vapor-phase epitaxy (HVPE) reactor. Note that this GaN quasi-substrate layer also serves as the emitter region for the PBT. In one embodiment, this layer is auto-doped n-type with a silicon (Si) carrier concentration of about 5 ⁇ 10 18 cm ⁇ 3 .
  • Atomic force microscopy (AFM) studies on the GaN quasi-substrates show a step-flow growth mode with atomically smooth terraces or “fingers” of 0.2 ⁇ m width and step-height of 2 monolayers. RMS roughness of 0.45 nm was obtained over a 10 ⁇ 10 ⁇ m area.
  • the base and collector epilayers of this embodiment are 1.3 ⁇ m and 0.2 ⁇ m thick, respectively.
  • the layers can be grown by plasma-enhanced molecular beam epitaxy (MBE) carried out, for example, in a Varian Genii GenII system. Other such systems can be used here as well.
  • MBE plasma-enhanced molecular beam epitaxy
  • Seamless epitaxy of GaN via MBE on GaN quasi-substrates can be achieved by growing the epilayers in group III-rich conditions.
  • These base and emitter layers replicate the underlying GaN quasi-substrate layer without renucleation.
  • the base and collector layers are doped with silicon (Si) to carrier concentrations of 5 ⁇ 10 16 and 5 ⁇ 10 18 , respectively.
  • the Schottky barrier When the PBT is in ON condition, the majority carriers flow from emitter (held at ground potential) to collector (biased at positive potential). Under normal operation, the Schottky barrier is reverse-biased by a negative base-to-emitter voltage. A voltage dependent depletion region forms beneath the Schottky barrier. This constricts the effective area of the n-channel (reducing the depletion region on either side of the emitter finger), causing the channel to open and the collector current to vary with applied base bias.
  • the base bias induces a potential barrier under the collector. Near pinch-off, electrons that are injected from the emitter are accelerated by the collector bias, and pass across the potential barrier. At higher collector biases, the thermionic emission current rises exponentially with applied collector bias eventually becoming space charge limited, resulting in a triode mode device operation, where the collector current does not saturate at high collector voltages.
  • V 1 ⁇ qNa 2 2 ⁇ ⁇ r ⁇ ⁇ 0
  • q is the charge of an electron
  • a is the channel thickness (or, in the case of a PBT, half the width of 1 finger)
  • ⁇ (r) is the relative permittivity of the material
  • ⁇ (0) is the permittivity of vacuum.
  • FIGS. 3a through 7 demonstrate a process flow for the fabrication of a GaN PBT in accordance with one embodiment of the present invention. This process flow includes all steps required to fabricate the device, as well as the design of a photolithography mask set drawn using AutoCAD. Various process alternatives are also provided.
  • the GaN PBT because it is based on vertical transport, has three distinctly doped layers versus the two of lateral transistor devices for the metal contacts and the device itself to perform optimally.
  • the bottom n + layer is deposited thick (e.g., n + 5 ⁇ 10 18 cm ⁇ 3 , HVPE) to keep the vertical threading dislocations minimal
  • the layer structure is chosen because the heavily doped regions will be used for ohmic contacts and the lightly doped region will be used for a Schottky contact to adequately pinch off for a given range of high frequency operation.
  • the desired blocking voltage of the transistor determines the thick n-region.
  • the final structure will look similar to that shown in FIG. 1b , where the material layers are the same as in FIG. 2a .
  • a full PBT will have a plurality of the collector fingers, and is this particular case. Only three are shown in FIG. 1b for the purpose of illustration. In one particular embodiment, the full PBT device has 20 collector fingers, each surrounded by two base regions to control the width of the channel, as shown in FIG. 1b . It will be appreciated that, in developing a process for a PBT device, it is necessary to have tolerances to variability in the semiconductor material characteristics and fabrication process. Some tolerances that are used herein are passivation layers, implantation, and pre-metal deposition treatments.
  • view 1 is the overall top view
  • view 2 is the cross section through the collector RF probe pad
  • view 3 is the cross section through the collector ohmic pad
  • view 4 is the cross section through the base collector fingers
  • view 5 is the cross section through the base RF probe pad.
  • This particular embodiment begins with the HVPE growth of 10 ⁇ m of heavily doped (e.g., 2 ⁇ 10 18 cm ⁇ 3 to 5 ⁇ 10 18 cm ⁇ 3 ) n-GaN followed by 2 ⁇ m of MBE grown, lightly doped (e.g., 2 ⁇ 10 16 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 ) n-GaN and 0.3 ⁇ m of MBE grown, highly doped (e.g., 2 ⁇ 10 18 cm ⁇ 3 to 5 ⁇ 10 18 cm ⁇ 3 ) n-GaN.
  • the silicon nitride deposition (to be discussed in turn) is to passivate the sidewalls of the collector fingers to prevent shorting of the base to the collector if metal accidentally deposits on the sidewalls.
  • Step 1 Perform RCA wafer clean.
  • the purpose of the RCA wafer clean is to remove organic contaminants (e.g., dust particles, grease or silica gel) from the wafer surface, as well as any oxide layer that may have built up, and any ionic or heavy metal contaminants.
  • organic contaminants e.g., dust particles, grease or silica gel
  • Step 2 Open windows for helium (He) implantation using optical lithography. Due to the fact that the PBT is a “normally-on” device, the semiconductor material is conducting by default. Thus, an insulating layer is used to isolate the pads from the device. In this particular embodiment, the insulating layer is provided with He implantation.
  • FIG. 3a shows the optical lithography for He implantation of this step. As can be seen, the photo resist (PR) is shown is each of the views in locations where no He implantation is desired. In one particular embodiment, the wafer is patterned with about 9 ⁇ m photo resist for the He implantation.
  • Step 3 Perform He 2+ implantation at about 250 keV, 1.35 ⁇ m isolation depth (determined from a TRIM calculation).
  • FIG. 3b shows the locations of He implantation with the diagonal striping.
  • a dose of about 1 ⁇ 10 15 cm ⁇ 3 was targeted with an acceleration voltage of 180 keV at an implant angle of 7°.
  • TRIM simulations estimated an implant depth of about 2 ⁇ m.
  • Step 4 Strip the photo resist mask. The resulting structure after stripping is shown in FIG. 3c .
  • Step 5 Open windows for thin, high quality silicon nitride pad (SiN x ), about 1000–2000 ⁇ thick, using optical lithography.
  • FIG. 3d shows the optical lithography for the SiN x pad of this step.
  • Step 5a Perform deposition of high quality SiN x pad, 1000–2000 ⁇ thick.
  • This SiN x layer serves as the second electrical isolation for the collector and base contact pads.
  • FIG. 3e shows the resulting structure after the SiN x deposition of this step.
  • 1000 ⁇ of high quality SiN x pads were deposited on top of the He-implant region via plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • Step 5b Perform lift-off of high quality silicon nitride pad, 1000–2000 ⁇ thick.
  • FIG. 3f shows the resulting structure after the SiN x lift-off of this step, where all SiN x deposited on top of photo resist is removed.
  • Step 6 Open windows for Ti metal pad using optical lithography.
  • FIG. 3g shows the optical lithography for the Ti pad of this step.
  • Step 6a Perform Ti metallization.
  • FIG. 3h shows the resulting structure after the Ti metallization of this step.
  • Ti/Au (500 ⁇ /1000 ⁇ ) collector metal pads are deposited using e-beam evaporation.
  • Step 6b Perform lift-off of Ti metallization.
  • FIG. 3i shows the resulting structure after the Ti metallization lift-off of this step, where all Ti deposited on top of photo resist is removed.
  • Step 7 Perform E-beam lithography of collector fingers and for self-aligned base recess and metallization.
  • FIG. 3j shows the E-beam lithography of the collector fingers of this step.
  • the wafer is patterned with e-beam lithography using PMMA photo resist (about 0.14 ⁇ m) for the metallization of the collector fingers.
  • Step 7a Perform ohmic metallization of collector.
  • a 1 minute HCl:DI H 2 0 (1:1) dip is used for removing contaminants on the semiconductor surface.
  • FIG. 3k shows the resulting structure after the Ti/Ni metallization of this step.
  • the metal scheme used for the collector fingers is Ti/Ni with thicknesses of 100 ⁇ and 400 ⁇ , respectively. With this arrangement, Ti acts as the metal contact, while Ni serves as the base shallow etch mask.
  • Step 7b Perform lift-off of ohmic metallization of collector.
  • FIG. 3m shows the resulting structure after the Ti/Ni metallization lift-off of this step, where all Ti/Ni deposited on top of photo resist is removed.
  • each collector finger is about 0.2 ⁇ m wide and 230 ⁇ m in length. Since only 200 ⁇ m of this length covers each finger active region of the device, the total finger area is 40 ⁇ m 2 .
  • Each device has 20 fingers either with a 1:1 pitch (evenly spaced) or 1:3 pitch.
  • Step 8 Open windows for a Ti cap in collector pad region using optical lithography.
  • FIG. 3n shows the optical lithography for the Ti cap of this step.
  • Step 8a Deposit thin Ti cap in collector pad region again to prevent collector metal fingers from peeling upward and losing contact to the pad.
  • FIG. 3p shows the resulting structure after the Ti metallization of this step.
  • Ti/Au (500 ⁇ /1000 ⁇ ) collector metal caps are deposited using e-beam evaporation.
  • Step 8b Perform lift-off of the thin Ti cap in collector region.
  • FIG. 3q shows the resulting structure after the Ti metallization lift-off of this step, where all Ti deposited on top of photo resist is removed.
  • Step 9 Open windows for the base recess/metallization (collector lines are part of mask) using optical lithography.
  • FIG. 3r shows the optical lithography for the base recess/metallization of this step.
  • Step 9a Perform a high density plasma etch to recess the base layer to n ⁇ layer (e.g., about 0.5 ⁇ m).
  • FIG. 3s shows the resulting structure after the high density plasma etch in the base region of this step.
  • the wafer is etched using a custom-built inductively coupled plasma (ICP) etching system utilizing pure Cl 2 chemistry.
  • Etching can be performed at a chamber pressure of about 3.8 ⁇ 10 ⁇ 3 torr, 350 W ICP power and about ⁇ 400 V chuck bias with a ramp down to about ⁇ 200V bias for the last minute of the etch.
  • the ramp down etches a layer of material damaged by plasma leaving behind undamaged GaN for subsequent metal contact deposition. This etch-damage removal enables excellent ohmic electrical characteristics. Approximately 0.5 nm etch depth is achievable.
  • Step 9b Perform conformal SiN x deposition for spacer and sidewall passivation. This layer prevents shorting between the base and collector if metal accidentally deposits on the finger sidewalls.
  • FIG. 3t shows the resulting structure after the SiN x deposition for spacer and sidewall passivation of this step.
  • the conformal SiN layer is less than 500 ⁇ .
  • Step 9c Perform directional etch to remove SiN x on parallel surfaces.
  • FIG. 3u shows the resulting structure after the directional etch for SiN x removal of this step.
  • a directional reactive-ion etching (RIE) of the SiN planes parallel to the surface was used to expose the base layer between the fingers.
  • Step 9d Perform base metallization (Pt/Ni).
  • FIG. 3v shows the resulting structure after the base metallization of this step.
  • the base contact was deposited using Ni/Pt/Au (Schottky contacts) having layers of thickness 100 ⁇ /400 ⁇ /100 ⁇ , respectively.
  • Step 9e Perform lift-off of base metallization (Pt/Ni).
  • FIG. 3w shows the resulting structure after the base metallization lift-off of this step.
  • a post Schottky deposition anneal is used to alloy the ohmic contacts. This is because the Schottky metal is deposited before the emitter ohmic metal. A low temperature anneal does not substantially alter the forward bias behavior of the Schottky contacts, but decreases the reverse leakage current. Further note that the Schottky contacts are the contacts in the base region). In one particular embodiment, an anneal for about 60 seconds at 500° C. is used to maintain low reverse current leakage while providing low contact resistance.
  • Step 10 Open emitter etch/contact window using optical lithography.
  • FIG. 3x shows the resulting structure after the optical lithography for emitter etch of this step.
  • the wafer is patterned with a thick photoresist (e.g., about 4 ⁇ m) for a deep etch of 2 ⁇ m to 3 ⁇ m down to the emitter layer via ICP etching.
  • Step 10a Etch emitter recess to bottom, HVPE n + GaN quasi-substrate layer (e.g., about 2.5 ⁇ m).
  • FIG. 3y shows the resulting structure after the etching of the emitter recess of this step.
  • Step 10b Perform emitter ohmic metallization.
  • FIG. 3z shows the resulting structure after the emitter ohmic metallization of this step.
  • the emitter ohmic contacts were deposited using a Ti/Al/Ni/Au metal scheme having thicknesses of 300 ⁇ /1500 ⁇ /400 ⁇ /1500 ⁇ , respectively.
  • Step 10c Perform lift-off of emitter ohmic metallization.
  • FIG. 3 aa shows the resulting structure after the emitter ohmic metallization of this step.
  • Step 11 Open windows for RF test pad metallization using optical lithography.
  • FIG. 3 bb shows the resulting structure after the optical lithography of this step.
  • Step 11a Deposit RF test pad metal.
  • FIG. 3 cc shows the resulting structure after the deposition of test pad metal of this step.
  • this metal includes an adhesion layer (e.g., titanium or nickel) and a thick gold (Au) capping layer, since Au is a good microwave conductor and prevents oxidation.
  • Au gold
  • Step 11b Perform lift-off RF test pad metal.
  • FIG. 3 dd shows the resulting and final structure after the RF test pads liftoff of this step.
  • a first variation on the PBT fabrication methodology deals with the deposition of the SiN x in step 5.
  • a conformal deposition of SiN x over the entire wafer followed by photo resist patterning and wet chemistry etch to remove the SiN x from the unwanted areas may be more desirable, since SiN x is sometimes difficult to remove via liftoff.
  • the SiN x is about 1000 ⁇ thick, and the wet chemical etch will provide a shallow slope on the sidewalls which will ensure metal continuity from the collector fingers to the contact pad.
  • the metal pad on top of the collector region can be altered to Ni/Pt because of the new Schottky metal on the collector fingers.
  • the electron beam lithography can also be changed, to provide a second variation.
  • a large window can be opened.
  • FIG. 4 shows the e-beam lithography for opening a large base window in accordance with one such embodiment of the present invention. This window would be used for base recess and metallization as well as collector finger metallization. This will ensure that the metal on the collector fingers is not very thick, thus minimizing the chance of connection between the various fingers.
  • step 9d where the Schottky metal deposited would be the metal for both the base region and collector fingers.
  • the Schottky metal would be feasible as the collector metal because of ballistic electrons that could pass the potential barrier.
  • the Ti capping layer on the collector contact in steps 8 through 8b can be omitted, in this particular variation.
  • a “0” level Ti/Pt layer can be used.
  • the first layer (step 3) is a He implantation, which requires alignment for further steps in the process.
  • implanted He areas are not distinguishable under optical alignment
  • a “0” level mask for subsequent optical and electron beam alignment was added.
  • the metal to be used for enabling optical alignment is titanium (Ti) followed by platinum (Pt).
  • this “0” level mask is a Ti/Pt layer of about 200–500/1500 ⁇ , respectively. These metals are chosen because of Ti's good adhesion to GaN and Pt is a good alignment metal for e-beam writers (because it is high Z). Crosses for optical alignment and squares for e-beam alignment are thus provided.
  • the thick Pt was found to work best for this e-beam writing system. Also, it was found that the He 2+ implantation given in step 3 would penetrate the photo resist about 3.50 ⁇ m based on a TRIM calculation of Rp+ ⁇ Rp (the ion range and range straggling). This shows that a thick resist, such as AZ4620, is needed.
  • the SiN x etch can be done via a wet chemistry of NH 4 F, which will leave a shallow slope on the nitride walls due to the slow etching and isotropy characteristic of wet chemistry etches.
  • the e-beam photo resist, PMMA is not intended to be a dry etch mask and for this reason, cannot be used as previously given in step 7. For this reason, only the collector fingers shall be opened.
  • 20 fingers could be used. These fingers shall be 40–200 ⁇ m long and varying width (0.15–0.3 ⁇ m).
  • the metal on top of these fingers can be, for example, Schottky, Ni/Pt/Ni (200/500/500 ⁇ ), where the final Ni layer is used as an etch mask since it was found to withstand a chlorine etch well.
  • the settings of this etch shall be ICP, ⁇ 0.43 ⁇ m in depth using pure Cl 2 chemistry, 400 W ICP power, and 200 eV ion energies.
  • the low bias voltage is used to provide a slow and accurate etch depth.
  • the structure resulting from the base etch following collector metal deposition (with photo resist) is shown in FIG. 5a .
  • the decreased etch depth (0.43 ⁇ m) is due to an additional etch step that is needed and will be described next.
  • a base metal deposition as given in step 9b isolates the base metal from the GaN material on the sides of the collector fingers so an additional etching after the SiN x deposition is needed to expose the sidewalls of the collector fingers, and to allow better base metal contact and, therefore, better base voltage control of the collector current resulting in higher transconductance in the device.
  • This deposited SiN x is, for instance, less than 500 ⁇ via PECVD. This thickness is decreased since the minimum base region width is 1500 ⁇ and 1000 ⁇ of SiN x on both sides would completely close the base region.
  • This additional etch is a two-stage etch.
  • a CH 4 —O 2 mix is used via RIE to directionally remove the SiN x since Cl 2 has a much faster etch rate on GaN than on SiN x .
  • an ICP base etch for collector finger contact will be used to etch the GaN 0.07 ⁇ m as shown in FIG. 5b .
  • the 0.07 ⁇ m depth is exactly the thickness of the subsequent metal deposition to prevent shorting of any metal that accidentally deposits on the sidewalls or in case the metal deposition is slightly thicker than expected.
  • the base is metallized with Ni/Pt (300/400 ⁇ ). Following this, all steps can be as previously discussed.
  • a fourth variation of the fabrication process includes the initial deposition of Ti/Al/Pt alignment markers.
  • the addition of Al is to create an ohmic contact at the first layer for ohmic circular transmission line measurement (CTLM) and Schottky diode test structures that will be employed since the e-beam writer cannot write large areas during definition of the collector regions (otherwise, the first ohmic deposition).
  • CTLM circular transmission line measurement
  • the addition of Al will not affect the e-beam alignment with the thick Pt (e.g., 1500 ⁇ ) deposited. He implantation under both base and collector contact pads is used due to the high conductivity of the material. This is shown in FIG. 6a .
  • the placement of the e-beam alignment markers is also given. Each alignment box is 4 ⁇ m ⁇ 4 ⁇ m. Note that they are 75 ⁇ m from the region to be written, due to the stringent requirements of the ebeam writing tool.
  • the first SiN x deposition is similar to previous versions with the exception that it is now included under the base contact pad (as well as the collector pad) as shown in FIG. 6b . This is a double safeguard for pad isolation. Now referring to FIG. 6c , note that the metal deposition shown on the collector pad is altered. Ni and Pt are both high stress films, so Ti/Au was chosen as a replacement since Ti is low stress and Au prevents oxidation to underlying metals. In one particular embodiment, these are deposited at 500/1000 ⁇ , respectively.
  • Collector fingers were also changed from Schottky to ohmic since collector and base metals were no longer to be deposited simultaneously.
  • the new metal scheme is Ti/Ni (100/400 ⁇ ). Process tests support the use of a thicker Ni layer and removal of the Al layer and are the reason for this increase in thickness. This thin metal is the maximum thickness allowed with the thin (e.g., 1500 ⁇ ) e-beam resist needed for fine features (e.g., 0.15 ⁇ m). Following this metal liftoff, SiN x is deposited (as previously described with the two stage etch).
  • the emitter is etched. This requires a thick resist of, for instance, AZ4620 of about 4 ⁇ m. Dimensions of the emitter etch are given in FIG. 6d , and the final device structure is shown in FIG. 6e .
  • a fifth variation of the fabrication process includes a modification to the silicon nitride pad deposited in steps 5, 5a, and 5b.
  • the SiN x pad is square such that, the He implanted region will extend out to the collector fingers, and no SiN will be under the fingers. This will reduce the difference in height between the fingers in the collector pad region (e.g., view 3 of FIG. 2b ) relative to the height of the fingers out of the collector pad region (e.g., view 4 of FIG. 2b ), which helps to prevent the metal fingers from disconnecting from the collector pad due to a significant difference in height.
  • FIG. 7 where there is only a layer of titanium under the fingers at the collector pad region (and no SiN layer).
  • the height difference of the collector fingers in the collector region and the collector fingers out of the collector region is about one layer of titanium.
  • FIG. 8 shows a top view SEM picture of a completed PBT device configured in accordance with the present invention.
  • high accuracy in the alignment of the different mask layers was achieved since the devices were processed with an optical lithography alignment tolerance in the order of 1.5 ⁇ m. This tolerance is much smaller than the usual limit for this technique.
  • FIG. 9 shows detailed SEM images of the collector finger of two different devices, with device (a) having 1:1 finger pitch and device (b) having 1:3 finger pitch.
  • One half the finger width (0.2 ⁇ m/2) is the effective device channel and the base contact thickness (600 ⁇ ) is the equivalent gate length. Note that these values are very small when compared to the conventional FET device features. Further note that a ramp down from ⁇ 400V bias to ⁇ 200V bias during the etch step produced a fairly smooth etched base surface. A finger sidewall angle of approximately 85° was achieved, which is highly anisotropic. A nickel metal layer thickness of 400 ⁇ acted as an excellent etch mask as can be appreciated by the uniform morphology of the finger structures.
  • Probing of the various CTLM test structures shows ohmic metal contacts which have specific contact resistivity, ⁇ c , of about 3 ⁇ 10 ⁇ 6 ⁇ cm 2 , which is an indication of the excellent contact quality.
  • the DC characteristic curve of a device with 1:1 finger pitch is shown in FIG. 10 .
  • the output characteristics have been measured for an applied base-emitter bias V BE ranging from +0.5 V to ⁇ 1.0 V.
  • the collector-emitter voltage V CE is in the 0 V to 5.5 V range. From the plot, it is evident that the base voltage controls the output current I C , showing transistor action.
  • a current density J C of up to 520 mA/mm 2 is achieved.
  • DC testing of the devices shows good base control (modulation Of I CE ), and current densities of up to 450 mA/mm 2 were achieved for a V CE of 5.0V.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
US12/268,515 2003-12-04 2004-10-01 GaN-based permeable base transistor and method of fabrication Expired - Fee Related USRE42955E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/268,515 USRE42955E1 (en) 2003-12-04 2004-10-01 GaN-based permeable base transistor and method of fabrication

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US52723803P 2003-12-04 2003-12-04
US12/268,515 USRE42955E1 (en) 2003-12-04 2004-10-01 GaN-based permeable base transistor and method of fabrication
PCT/US2004/032276 WO2005062365A1 (fr) 2003-12-04 2004-10-01 Transistor a base permeable a base de gan et procede de fabrication

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/532,456 Reissue US7413958B2 (en) 2003-12-04 2004-10-01 GaN-based permeable base transistor and method of fabrication

Publications (1)

Publication Number Publication Date
USRE42955E1 true USRE42955E1 (en) 2011-11-22

Family

ID=34710058

Family Applications (3)

Application Number Title Priority Date Filing Date
US12/268,515 Expired - Fee Related USRE42955E1 (en) 2003-12-04 2004-10-01 GaN-based permeable base transistor and method of fabrication
US10/532,456 Ceased US7413958B2 (en) 2003-12-04 2004-10-01 GaN-based permeable base transistor and method of fabrication
US12/132,802 Expired - Fee Related US8247843B2 (en) 2003-12-04 2008-06-04 GaN-based permeable base transistor and method of fabrication

Family Applications After (2)

Application Number Title Priority Date Filing Date
US10/532,456 Ceased US7413958B2 (en) 2003-12-04 2004-10-01 GaN-based permeable base transistor and method of fabrication
US12/132,802 Expired - Fee Related US8247843B2 (en) 2003-12-04 2008-06-04 GaN-based permeable base transistor and method of fabrication

Country Status (3)

Country Link
US (3) USRE42955E1 (fr)
EP (1) EP1690290A4 (fr)
WO (1) WO2005062365A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120034785A1 (en) * 2010-08-05 2012-02-09 Hisataka Hayashi Semiconductor device manufacturing method
US9112103B1 (en) 2013-03-11 2015-08-18 Rayvio Corporation Backside transparent substrate roughening for UV light emitting diode

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007142243A (ja) * 2005-11-21 2007-06-07 Matsushita Electric Ind Co Ltd 窒化物半導体電界効果トランジスタ及びその製造方法
DE102006007293B4 (de) * 2006-01-31 2023-04-06 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zum Herstellen eines Quasi-Substratwafers und ein unter Verwendung eines solchen Quasi-Substratwafers hergestellter Halbleiterkörper
DE102009034532A1 (de) * 2009-07-23 2011-02-03 Msg Lithoglas Ag Verfahren zum Herstellen einer strukturierten Beschichtung auf einem Substrat, beschichtetes Substrat sowie Halbzeug mit einem beschichteten Substrat
US8709897B2 (en) 2010-11-30 2014-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. High performance strained source-drain structure and method of fabricating the same
US9093395B2 (en) * 2011-09-02 2015-07-28 Avogy, Inc. Method and system for local control of defect density in gallium nitride based electronics
US8927999B2 (en) * 2011-11-21 2015-01-06 Avogy, Inc. Edge termination by ion implantation in GaN
US8754421B2 (en) 2012-02-24 2014-06-17 Raytheon Company Method for processing semiconductors using a combination of electron beam and optical lithography
CN110783450A (zh) * 2019-10-22 2020-02-11 深圳第三代半导体研究院 一种基于氮化镓/铝镓氮异质结的磁场传感器

Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3966501A (en) 1973-03-23 1976-06-29 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices
US4224361A (en) * 1978-09-05 1980-09-23 International Business Machines Corporation High temperature lift-off technique
US4510016A (en) * 1982-12-09 1985-04-09 Gte Laboratories Method of fabricating submicron silicon structures such as permeable base transistors
US4701996A (en) * 1984-12-19 1987-10-27 Calviello Joseph A Method for fabricating edge channel FET
US5006488A (en) * 1989-10-06 1991-04-09 International Business Machines Corporation High temperature lift-off process
US5175597A (en) * 1990-06-15 1992-12-29 Thomson-Csf Semiconductor component with schottky junction for microwave amplification and fast logic circuits
US5215619A (en) * 1986-12-19 1993-06-01 Applied Materials, Inc. Magnetic field-enhanced plasma etch reactor
US5270554A (en) * 1991-06-14 1993-12-14 Cree Research, Inc. High power high frequency metal-semiconductor field-effect transistor formed in silicon carbide
US5571732A (en) * 1993-08-19 1996-11-05 Texas Instruments Incorporated Method for fabricating a bipolar transistor
US5895260A (en) * 1996-03-29 1999-04-20 Motorola, Inc. Method of fabricating semiconductor devices and the devices
US5929467A (en) * 1996-12-04 1999-07-27 Sony Corporation Field effect transistor with nitride compound
US6051503A (en) * 1996-08-01 2000-04-18 Surface Technology Systems Limited Method of surface treatment of semiconductor substrates
US6156581A (en) * 1994-01-27 2000-12-05 Advanced Technology Materials, Inc. GaN-based devices using (Ga, AL, In)N base layers
US6410396B1 (en) 2000-04-26 2002-06-25 Mississippi State University Silicon carbide: germanium (SiC:Ge) heterojunction bipolar transistor; a new semiconductor transistor for high-speed, high-power applications
US20020117685A1 (en) 2001-02-23 2002-08-29 Hitachi, Ltd. Semiconductor device and the method of producing the same
US20020190273A1 (en) * 1999-12-23 2002-12-19 Sylvain Delage Bipolar transistor with upper heterojunction collector and method for making same
US20030015708A1 (en) * 2001-07-23 2003-01-23 Primit Parikh Gallium nitride based diodes with low forward voltage and low reverse current operation
US6533874B1 (en) 1996-12-03 2003-03-18 Advanced Technology Materials, Inc. GaN-based devices using thick (Ga, Al, In)N base layers
US6545340B1 (en) 1998-09-22 2003-04-08 Qinetiq Limited Semiconductor device
US20030151046A1 (en) * 2002-02-14 2003-08-14 Innovative Technology Licensing, Llc Bipolar transistor characterization apparatus and method employing air bridge connectors to test probe pads
US20040023508A1 (en) * 2002-08-02 2004-02-05 Applied Materials, Inc. Method of plasma etching a deeply recessed feature in a substrate using a plasma source gas modulated etchant system
US6690042B2 (en) * 2000-09-27 2004-02-10 Sensor Electronic Technology, Inc. Metal oxide semiconductor heterostructure field effect transistor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198072A (en) * 1990-07-06 1993-03-30 Vlsi Technology, Inc. Method and apparatus for detecting imminent end-point when etching dielectric layers in a plasma etch system
US6432788B1 (en) * 1999-07-22 2002-08-13 Implant Sciences Corporation Method for fabricating an emitter-base junction for a gallium nitride bipolar transistor
US6639255B2 (en) * 1999-12-08 2003-10-28 Matsushita Electric Industrial Co., Ltd. GaN-based HFET having a surface-leakage reducing cap layer

Patent Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3966501A (en) 1973-03-23 1976-06-29 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices
US4224361A (en) * 1978-09-05 1980-09-23 International Business Machines Corporation High temperature lift-off technique
US4510016A (en) * 1982-12-09 1985-04-09 Gte Laboratories Method of fabricating submicron silicon structures such as permeable base transistors
US4701996A (en) * 1984-12-19 1987-10-27 Calviello Joseph A Method for fabricating edge channel FET
US5215619A (en) * 1986-12-19 1993-06-01 Applied Materials, Inc. Magnetic field-enhanced plasma etch reactor
US5006488A (en) * 1989-10-06 1991-04-09 International Business Machines Corporation High temperature lift-off process
US5175597A (en) * 1990-06-15 1992-12-29 Thomson-Csf Semiconductor component with schottky junction for microwave amplification and fast logic circuits
US5270554A (en) * 1991-06-14 1993-12-14 Cree Research, Inc. High power high frequency metal-semiconductor field-effect transistor formed in silicon carbide
US5571732A (en) * 1993-08-19 1996-11-05 Texas Instruments Incorporated Method for fabricating a bipolar transistor
US6156581A (en) * 1994-01-27 2000-12-05 Advanced Technology Materials, Inc. GaN-based devices using (Ga, AL, In)N base layers
US5895260A (en) * 1996-03-29 1999-04-20 Motorola, Inc. Method of fabricating semiconductor devices and the devices
US6051503A (en) * 1996-08-01 2000-04-18 Surface Technology Systems Limited Method of surface treatment of semiconductor substrates
US6533874B1 (en) 1996-12-03 2003-03-18 Advanced Technology Materials, Inc. GaN-based devices using thick (Ga, Al, In)N base layers
US5929467A (en) * 1996-12-04 1999-07-27 Sony Corporation Field effect transistor with nitride compound
US6545340B1 (en) 1998-09-22 2003-04-08 Qinetiq Limited Semiconductor device
US20020190273A1 (en) * 1999-12-23 2002-12-19 Sylvain Delage Bipolar transistor with upper heterojunction collector and method for making same
US6410396B1 (en) 2000-04-26 2002-06-25 Mississippi State University Silicon carbide: germanium (SiC:Ge) heterojunction bipolar transistor; a new semiconductor transistor for high-speed, high-power applications
US6690042B2 (en) * 2000-09-27 2004-02-10 Sensor Electronic Technology, Inc. Metal oxide semiconductor heterostructure field effect transistor
US20020117685A1 (en) 2001-02-23 2002-08-29 Hitachi, Ltd. Semiconductor device and the method of producing the same
US20030015708A1 (en) * 2001-07-23 2003-01-23 Primit Parikh Gallium nitride based diodes with low forward voltage and low reverse current operation
US20030151046A1 (en) * 2002-02-14 2003-08-14 Innovative Technology Licensing, Llc Bipolar transistor characterization apparatus and method employing air bridge connectors to test probe pads
US20040023508A1 (en) * 2002-08-02 2004-02-05 Applied Materials, Inc. Method of plasma etching a deeply recessed feature in a substrate using a plasma source gas modulated etchant system

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
Bozler, Carl O. et al. "Fabrication and Numerical Simulation of the Permeable Base Transistor", IEEE, 1980, pp. 1-14.
Bunea, Gabriela E. et al., "Modeling of a GaN Based Static Induction Transistor", Dept. of Physics, Electrical and Computer Engineering, Boston University, pp. 1-6, Boston, MA, (No date).
Camarchia, Vittorio et al. "Physics-Based Modeling of Submicron GaN Permeable Base Transistors", IEEE Electron Device Letters, Jun. 2002, pp. 303-305, vol. 23, No. 6.
Gunter, Liberty Lewis, "Process Design and Development of a Gallium Nitride Permeable Base Transistor", Boston University College of Engineering, 2002, 134 pages.
Henning, J.P. et al., "A Novel Self-Aligned Fabrication Process for Microwave Static Induction Transistors in Silicon Carbide", IEEE Electron Device Letters, Dec. 2000, pp. 578-580, vol. 21, No. 12.
Misra M. et al. "Investigation of vertical transport in n-GaN films grown by molecular beam epitaxy using Schottky barrier diodes", Applied Physics Letters, Feb. 21, 2000, pp. 1045-1047, vol. 76, No. 8. American Institute of Physics.
Nishizawa, Jun-Ichi et al., "The 2.45 GHz 36 W CW Si Recessed Gate Type SIT with High Gain and High Voltage Operation", IEEE Transactions On Electronic Devices, Feb. 2000, pp. 482-487, vol. 47, No. 2.
PCT International Search Report dated Apr. 7, 2005 of International Application No. PCT/US04/32276 filed Oct. 1, 2004.

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120034785A1 (en) * 2010-08-05 2012-02-09 Hisataka Hayashi Semiconductor device manufacturing method
US8536061B2 (en) * 2010-08-05 2013-09-17 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US9112103B1 (en) 2013-03-11 2015-08-18 Rayvio Corporation Backside transparent substrate roughening for UV light emitting diode
US9461198B2 (en) 2013-03-11 2016-10-04 Rayvio Corporation Backside transparent substrate roughening for UV light emitting diode

Also Published As

Publication number Publication date
EP1690290A1 (fr) 2006-08-16
WO2005062365A1 (fr) 2005-07-07
US7413958B2 (en) 2008-08-19
US20080265259A1 (en) 2008-10-30
US8247843B2 (en) 2012-08-21
US20060148156A1 (en) 2006-07-06
EP1690290A4 (fr) 2008-10-22

Similar Documents

Publication Publication Date Title
US8247843B2 (en) GaN-based permeable base transistor and method of fabrication
US7745851B2 (en) Polytype hetero-interface high electron mobility device and method of making
US9142659B2 (en) Electrode configurations for semiconductor devices
US7244973B2 (en) Field-effect semiconductor device and method for making the same
CN111403487B (zh) 一种集成mosfet及二极管的半导体装置及其制造方法
US5514605A (en) Fabrication process for compound semiconductor device
US7491627B2 (en) III-nitride device and method with variable epitaxial growth direction
WO1989007333A1 (fr) Dispositif a transistors verticaux fabrique avec post-croissance de semi-conducteurs
JPH0613411A (ja) 電界効果トランジスタ及びその製造方法
CN117438457B (zh) 凹槽栅型GaN基HEMT器件及其制备方法
KR100321889B1 (ko) 반도체 장치 및 그 제조 방법
JP2008072083A (ja) 窒化物半導体デバイス及びその作製方法
US20060284282A1 (en) Heterjunction bipolar transistor with tunnelling mis emitter junction
US7402844B2 (en) Metal semiconductor field effect transistors (MESFETS) having channels of varying thicknesses and related methods
WO2022031937A1 (fr) Hfet à base de gan à enrichissement
US10177247B2 (en) Continuous crystalline gallium nitride (GaN) PN structure with no internal regrowth interfaces
CN111863958B (zh) 一种常开型高电子迁移率晶体管结构及其制造方法
JPH05129345A (ja) マイクロ波集積回路の製造方法
WO2022271083A1 (fr) Appareil à semi-conducteur et son procédé de fabrication
Vojak et al. A self-aligned dual-grating GaAs permeable base transistor
CN117855266A (zh) 一种具有低欧姆接触电阻率的GaN基HEMT器件及其制备方法
Cabalu et al. Design and Fabrication of GaN-based Permeable-Base Transistors
KR20220083618A (ko) 고전자이동도 트랜지스터 및 그 제조방법
CN115799296A (zh) Iii族氮化物二极管器件及其制作方法和应用
Adachi et al. A new gate structure vertical-GaAs FET

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 4

SULP Surcharge for late payment
FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY