WO2022271083A1 - Appareil à semi-conducteur et son procédé de fabrication - Google Patents

Appareil à semi-conducteur et son procédé de fabrication Download PDF

Info

Publication number
WO2022271083A1
WO2022271083A1 PCT/SG2021/050763 SG2021050763W WO2022271083A1 WO 2022271083 A1 WO2022271083 A1 WO 2022271083A1 SG 2021050763 W SG2021050763 W SG 2021050763W WO 2022271083 A1 WO2022271083 A1 WO 2022271083A1
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric film
semiconductor apparatus
layer
highly doped
gan
Prior art date
Application number
PCT/SG2021/050763
Other languages
English (en)
Inventor
Yuan Gao
Chengyu HU
Original Assignee
Igss-Gan Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Igss-Gan Pte Ltd filed Critical Igss-Gan Pte Ltd
Publication of WO2022271083A1 publication Critical patent/WO2022271083A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the disclosures made herein relate generally to a semiconductor apparatus, and more particularly to a semiconductor apparatus (e.g. gate formation of gate Gallium nitride high-electron-mobility transistor (GaN HEMT) device or the like) and method for fabricating the same.
  • a semiconductor apparatus e.g. gate formation of gate Gallium nitride high-electron-mobility transistor (GaN HEMT) device or the like
  • GaN HEMT gallium nitride high-electron-mobility transistor
  • a switching device that operates in a normally-off mode is the most preferred switching device in power switching applications, wherein, when a gate bias is 0V, the switching device is off with no current flow and power consumption.
  • An AlGaN/GaN HEMT device is known to be one of the best power switching devices, due to its high breakdown voltage, high current density and low parasitic capacitance, etc.
  • There are many methods to manufacture a normally-off HEMT device and the most common way is to grow a layer of pGaN on top of an AlGaN barrier. The pGaN layer will supply a hole carrier to deplete a two-dimensional electron gas (2DEG) conduction channel, hence switching off the transistor.
  • 2DEG two-dimensional electron gas
  • the pGaN layer is grown in a metal organic chemical vapor deposition (MOCVD) process using Magnesium (Mg) as dopant.
  • MOCVD metal organic chemical vapor deposition
  • Mg doping efficiency is quite poor, which means that higher Mg doping (i.e., E19 level) is needed in order to provide sufficient Hole carrier.
  • E19 level Magnesium
  • the pGaN film tends to be more rough and defective, which will result in V th stability issue.
  • Mg may diffuse into AlGaN barrier layer, and in the fabrication process, the pGaN layer needs to be selectively etched away, hence the AlGaN barrier surface will be exposed or damaged during pGaN etch process, all these will be resulting in poor dynamic drain-source on resistance (Rds_on) performance.
  • the present invention relates to a semiconductor apparatus.
  • the semiconductor apparatus includes a Gallium nitride (GaN) channel layer and an Aluminium gallium nitride (AlGaN) layer.
  • a two-dimensional electron gas (2DEG) is formed between the GaN channel layer and the AlGaN layer.
  • a GaN cap is formed on at least one portion of the AlGaN layer.
  • a first dielectric film is formed on at least one portion of the GaN cap.
  • the first dielectric film is patterned with a phot resist, after an isolation region is formed.
  • a highly doped p type layer is deposited on a portion of the first dielectric film and a portion of a channel depletion zone, after a gate region of the dielectric film is etched away in the semiconductor apparatus.
  • the highly doped p type layer is patterned with the photo resist, wherein the highly doped p type layer and the first dielectric film are covered with a second dielectric film.
  • the highly doped p type layer provides an optimized hole carrier supply to deplete a 2DEG conduction channel so as to enable integration of both normally -off mode and normally -on mode on a same EPI wafer of the semiconductor apparatus.
  • the channel depletion zone is formed under the gate region of the dielectric film as the gate region of the dielectric film is opened in the semiconductor apparatus.
  • the first dielectric film is patterned with the photo resist, after the isolation region is formed, so as to open a gate region of the semiconductor apparatus.
  • the first dielectric film ensures good surface state of the AlGaN layer.
  • the first dielectric film is formed on at least one portion of the isolation region.
  • the semiconductor apparatus comprises a GaN HEMT device.
  • the present invention relates to a method for fabricating a semiconductor apparatus.
  • the method includes providing a GaN channel layer and an AlGaN layer. Further, the method includes forming a 2DEG between the GaN channel layer and the AlGaN layer. Further, the method includes forming a GaN cap on at least one portion of the AlGaN layer. Further, the method includes forming a first dielectric film on at least one portion of the GaN cap. The first dielectric film is patterned with a photo resist, after an isolation region is formed. Further, the method includes depositing a highly doped p type layer on a portion of the first dielectric film and a portion of a channel depletion zone, after a gate region of the dielectric film is etched away in the semiconductor apparatus. The highly doped p type layer is patterned with the photo resist, wherein the highly doped p type layer and the first dielectric film are covered with a second dielectric film.
  • Figure la and Figure lb illustrate an example fabrication process of a conventional GaN HEMT device, in accordance with prior art.
  • FIG. 2a to Figure 2d illustrate an example fabrication process of a GaN HEMT device, in accordance with one embodiment of the present invention.
  • Figure 3 is an example flow chart illustrating a method for fabricating GaN HEMT device, according to one embodiment of the present invention.
  • the embodiment herein is to provide a semiconductor apparatus semiconductor apparatus includes a Gallium nitride (GaN) channel layer and an Aluminium gallium nitride (AlGaN) layer.
  • a two-dimensional electron gas (2DEG) is formed between the GaN channel layer and the AlGaN layer.
  • a GaN cap is formed on at least one portion of the AlGaN layer.
  • a first dielectric film is formed on at least one portion of the GaN cap.
  • the first dielectric film is patterned with a photo resist, after an isolation region is formed.
  • a highly doped p type layer is deposited on a portion of the first dielectric film and a portion of a channel depletion zone, after a gate region of the dielectric film is etched away in the semiconductor apparatus.
  • the highly doped p type layer is patterned with the photo resist, wherein the highly doped p type layer and the first dielectric film are covered with a second dielectric film.
  • E mode normally-off
  • the most common method to make an E mode device is to grow a pGaN layer on top of an AlGaN barrier layer, and the pGaN layer will supply the hole carrier to deplete the 2DEG channel. But, the pGaN layer growth is a challenge, which will degrade device performance and reliability.
  • the proposed method will use a highly doped p type layer to provide more efficient hole carrier supply, so as to improve semiconductor apparatus the performance.
  • the proposed method also can simplify the EPI and fabrication process and enable integration of both E mode and D mode device on the same EPI wafer. This results in enabling a power integrated circuit (IC) design easily.
  • the method provides a stable V t h performance and a better dynamic Rds_on performance since AlGaN barrier layer can be protected at the beginning of the fabrication process.
  • more efficient p dope layer material can be introduced to a gate region only during fabrication process, this layer can supply enough hole carrier, deplete the 2DEG channel, then a normal- off HEMT device can be made with more stable V th performance, also a better dynamic Rds_on performance can be achieved since AlGaN barrier layer surface can be protected at the beginning of the process.
  • Figure la and Figure lb illustrate an example fabrication process of a conventional GaN HEMT device (1000), in accordance with prior art. Referring to Figure la to Figure lb, the fabrication of a pGaN E mode
  • HEMT device (1000) starts with a pGaN layer (110) grown on a top of the AlGaN barrier layer (104) and a depletion zone (112) is formed due to a hole carrier injection of the pGaN layer (110). Further, after isolation region (108) is formed, a gate photo resist (118) is patterned, followed by RIE etch away majority of the pGaN except the gate region. This etch will damage and expose AlGaN barrier layer (104).
  • FIG. 2a to Figure 2d illustrate an example fabrication process of a semiconductor apparatus (2000), in accordance with one embodiment of the present invention.
  • the semiconductor apparatus (2000) can be a Gallium nitride high-electron-mobility transistor (GaN HEMT) device.
  • GaN HEMT Gallium nitride high-electron-mobility transistor
  • the semiconductor apparatus (2000) includes a 2DEG (106) formed between a GaN channel layer (102) and an AlGaN layer (104).
  • An GaN cap (120) is formed on at least one portion of the AlGaN layer (104) and a first dielectric film (114) is formed on at least one portion of the GaN cap (120).
  • the first dielectric film (106) is patterned with a photo resist (118), after an isolation region (108) is formed.
  • a highly doped p type layer (122) is deposited on a portion of the first dielectric film (114) and a portion of a channel depletion zone (112), after a gate region of the dielectric film (114) is etched away in the semiconductor apparatus (2000).
  • the channel depletion zone (112) is formed under the gate region of the dielectric film (106) as the gate region of the dielectric film (106) is opened in the semiconductor apparatus (2000).
  • the highly doped p type layer (122) is patterned with the photo resist (118).
  • the highly doped p type layer (122) and the first dielectric film (114) are covered with a second dielectric film (116).
  • the highly doped p type layer (122) provides an optimized hole carrier supply to deplete a 2DEG conduction channel so as to enable integration of both normally -off mode and normally -on mode on a same EPI wafer of the semiconductor apparatus (2000).
  • the first dielectric film (114) is patterned with the photo resist (118), after the isolation region (108) is formed, so as to open a gate region of the semiconductor apparatus (2000).
  • the first dielectric film (114) ensures good surface state of the AlGaN layer (104).
  • the first dielectric film (114) is formed on at least one portion of the isolation region (108).
  • Figure 3 is an example flow chart (S3000) illustrating a method for fabricating the GaN HEMT device, according to one embodiment of the present invention.
  • the method includes providing the GaN channel layer (102) and the AlGaN layer (104).
  • the method includes forming the 2DEG (106) between the GaN channel layer (102) and the AlGaN layer (104).
  • the method includes forming the GaN cap on the at least one portion of the AlGaN layer (104).
  • the method includes forming the first dielectric film (114) on at least one portion of the GaN cap (120). The first dielectric film (106) is patterned with the photo resist (118), after the isolation region (108) is formed.
  • the method includes depositing the highly doped p type layer (122) on the portion of the first dielectric film (114) and a portion of a channel depletion zone (112), after the gate region of the dielectric film (114) is etched away in the semiconductor apparatus (2000).
  • the highly doped p type layer (122) is patterned with the photo resist (118), wherein the highly doped p type layer (122) and the first dielectric film (114) are covered with the second dielectric film (116).
  • the proposed method will use a highly doped p type layer to provide more efficient hole carrier supply, so as to improve semiconductor apparatus the performance.
  • the proposed method also can simplify the EPI and fabrication process and enable integration of both E mode and D mode device on the same EPI wafer. This results in enabling a power integrated circuit (IC) design easily.
  • the method provides a stable V t h performance and a better dynamic Rds_on performance since AlGaN barrier layer can be protected at the beginning of the fabrication process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

La présente invention concerne un appareil à semi-conducteur (2000) et un procédé de fabrication de l'appareil à semi-conducteur (2000). Le procédé consiste à former un premier film diélectrique (114) sur au moins une partie d'un capuchon de GaN (120). Le premier film diélectrique (106) est modelé avec une résine photosensible (118), après formation d'une région d'isolation (108). Le procédé consiste à déposer la couche de type p fortement dopée sur la partie du premier film diélectrique (114) et une partie d'une zone d'appauvrissement de canal (112), après que la région de grille du film diélectrique (114) est éliminée par gravure dans l'appareil à semi-conducteur (2000). La couche de type p fortement dopée (122) est structurée avec la résine photosensible (118), la couche de type p hautement dopée (122) et le premier film diélectrique (114) étant recouverts par le second film diélectrique (116).
PCT/SG2021/050763 2021-06-21 2021-12-06 Appareil à semi-conducteur et son procédé de fabrication WO2022271083A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG10202106656Y 2021-06-21
SG10202106656Y 2021-06-21

Publications (1)

Publication Number Publication Date
WO2022271083A1 true WO2022271083A1 (fr) 2022-12-29

Family

ID=84546013

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SG2021/050763 WO2022271083A1 (fr) 2021-06-21 2021-12-06 Appareil à semi-conducteur et son procédé de fabrication

Country Status (1)

Country Link
WO (1) WO2022271083A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130256684A1 (en) * 2012-03-28 2013-10-03 Fujitsu Limited Compound semiconductor device and method of manufacturing the same
US20140091316A1 (en) * 2012-09-28 2014-04-03 Fujitsu Limited Semiconductor device and manufacturing method of semiconductor device
US20140239306A1 (en) * 2013-02-22 2014-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. High electron mobility transistor and method of forming the same
CN105845723A (zh) * 2016-05-18 2016-08-10 中国科学院微电子研究所 增强型GaN基高电子迁移率晶体管及其制备方法
KR20170069479A (ko) * 2015-12-11 2017-06-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130256684A1 (en) * 2012-03-28 2013-10-03 Fujitsu Limited Compound semiconductor device and method of manufacturing the same
US20140091316A1 (en) * 2012-09-28 2014-04-03 Fujitsu Limited Semiconductor device and manufacturing method of semiconductor device
US20140239306A1 (en) * 2013-02-22 2014-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. High electron mobility transistor and method of forming the same
KR20170069479A (ko) * 2015-12-11 2017-06-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법
CN105845723A (zh) * 2016-05-18 2016-08-10 中国科学院微电子研究所 增强型GaN基高电子迁移率晶体管及其制备方法

Similar Documents

Publication Publication Date Title
US11437485B2 (en) Doped gate dielectrics materials
US9111786B1 (en) Complementary field effect transistors using gallium polar and nitrogen polar III-nitride material
US8399911B2 (en) Enhancement mode field effect device and the method of production thereof
EP2166575B1 (fr) Dispositif semi-conducteur en matériau composé
JP6066933B2 (ja) 半導体デバイスの電極構造
KR101660870B1 (ko) 보상형 게이트 미스페트
US8946780B2 (en) Ohmic contact schemes for group III-V devices having a two-dimensional electron gas layer
US20220376084A1 (en) Semiconductor device and method for manufacturing the same
US20060281238A1 (en) Method of manufacturing an adaptive AlGaN buffer layer
US20130099285A1 (en) High electron mobility transistor having reduced threshold voltage variation and method of manufacturing the same
JP2007165431A (ja) 電界効果型トランジスタおよびその製造方法
WO2017123999A1 (fr) Dispositifs en nitrure iii à mode de perfectionnement ayant un isolant de grille en al(1-x)sixo
KR20140042871A (ko) 전류 애퍼쳐 수직 전자 트랜지스터들
KR102080745B1 (ko) 질화물 반도체 소자 및 그 제조 방법
US10559677B2 (en) Method of fabricating an enhancement mode group III-nitride HEMT device and a group III-nitride structure fabricated therefrom
WO2012066892A1 (fr) Dispositif à semi-conducteur et son procédé de fabrication
US9679762B2 (en) Access conductivity enhanced high electron mobility transistor
US11843047B2 (en) Integration of p-channel and n-channel E-FET III-V devices without parasitic channels
US20130240900A1 (en) Semiconductor device and method for producing the same
US20100314695A1 (en) Self-aligned vertical group III-V transistor and method for fabricated same
US8558242B2 (en) Vertical GaN-based metal insulator semiconductor FET
CN111370472A (zh) 混合栅p-GaN增强型氮化镓基晶体管结构及制作方法
US20220416071A1 (en) High electron mobility transistor and method of manufacturing the same
US20230290834A1 (en) ENHANCEMENT-MODE GaN HFET
TW202329461A (zh) 高電子遷移率電晶體及其製作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21946262

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21946262

Country of ref document: EP

Kind code of ref document: A1