US9978651B2 - Silicon carbide single crystal substrate, silicon carbide semiconductor device, and method for manufacturing silicon carbide semiconductor device - Google Patents

Silicon carbide single crystal substrate, silicon carbide semiconductor device, and method for manufacturing silicon carbide semiconductor device Download PDF

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US9978651B2
US9978651B2 US15/552,863 US201615552863A US9978651B2 US 9978651 B2 US9978651 B2 US 9978651B2 US 201615552863 A US201615552863 A US 201615552863A US 9978651 B2 US9978651 B2 US 9978651B2
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silicon carbide
main surface
single crystal
crystal substrate
carbide single
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US20180033703A1 (en
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Tsubasa Honke
Kyoko Okita
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present disclosure relates to a silicon carbide single crystal substrate, a silicon carbide semiconductor device, and a method for manufacturing the silicon carbide semiconductor device.
  • Patent Document 1 discloses a method for polishing a compound semiconductor wafer using an abrasive material and slurry containing abrasive grains.
  • PTD 1 Japanese Patent Laying-Open No. 2012-45690
  • An object of the present disclosure is to provide a silicon carbide single crystal substrate, a silicon carbide semiconductor device, and a method for manufacturing the silicon carbide semiconductor device so as to achieve suppression of position deviation of a mask pattern in a photolithography process.
  • a silicon carbide single crystal substrate includes a first main surface and a second main surface opposite to the first main surface.
  • the first main surface includes: a central square region surrounded by a square having a center corresponding to an intersection between the first main surface and a straight line that passes through a center of gravity of the silicon carbide single crystal substrate and that is parallel to a thickness direction of the silicon carbide single crystal substrate; and an outer square region surrounded by a square that has a side parallel to a straight line perpendicular to a straight line connecting the intersection to a certain position on an outer edge of the first main surface and that has a center corresponding to a position separated away by 10.5 mm from the certain position toward the intersection.
  • each of the central square region and the outer square region has a side having a length of 15 mm.
  • the first main surface has a maximum diameter of not less than 100 mm.
  • the silicon carbide single crystal substrate has a TTV of not more than 5 ⁇ m.
  • a value obtained by dividing a LTIR in the central square region by a LTV in the central square region is not less than 0.8 and not more than 1.2.
  • a value obtained by dividing a LTV in the outer square region by the LTV in the central square region is not less than 1 and not more than 3.
  • a silicon carbide single crystal substrate a silicon carbide semiconductor device, and a method for manufacturing the silicon carbide semiconductor device so as to achieve suppression of position deviation of a mask pattern in a photolithography process.
  • FIG. 1 is a schematic plan view showing a structure of a silicon carbide single crystal substrate according to a first embodiment.
  • FIG. 2 is a schematic longitudinal cross sectional view taken along a II-II line of FIG. 1 .
  • FIG. 3 is a schematic longitudinal cross sectional view of the silicon carbide single crystal substrate to illustrate a method for measuring a TTV.
  • FIG. 4 is a schematic longitudinal cross sectional view of the silicon carbide single crystal substrate to illustrate a method for measuring a LTIR.
  • FIG. 5 is a schematic longitudinal cross sectional view of the silicon carbide single crystal substrate to illustrate a method for measuring a LTV.
  • FIG. 6 is a schematic plan view showing the structure of the silicon carbide single crystal substrate according to the first embodiment.
  • FIG. 7 is a partially enlarged schematic longitudinal cross sectional view showing the structure of the silicon carbide single crystal substrate according to the first embodiment.
  • FIG. 8 is a schematic lateral cross sectional view showing a structure of a polishing apparatus for the silicon carbide single crystal substrate according to the first embodiment.
  • FIG. 9 is a schematic longitudinal cross sectional view showing a first step of a method for manufacturing the silicon carbide single crystal substrate according to the first embodiment.
  • FIG. 10 is a schematic longitudinal cross sectional view showing a second step of the method for manufacturing the silicon carbide single crystal substrate according to the first embodiment.
  • FIG. 11 shows a relation between grain sizes and frequency of diamond abrasive grains.
  • FIG. 12 is a schematic longitudinal cross section view showing a structure of a silicon carbide semiconductor device according to a second embodiment.
  • FIG. 13 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 14 is a schematic longitudinal cross sectional view showing a first step of the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 15 is a schematic longitudinal cross sectional view showing a second step of the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 16 is a schematic longitudinal cross sectional view showing a third step of the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 17 is a schematic longitudinal cross sectional view showing a fourth step of the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • a mask pattern is formed on the other main surface. If the thickness of the silicon carbide single crystal substrate in, for example, the radial direction is varied, flatness of the other main surface of the silicon carbide single crystal substrate is deteriorated when the one main surface of the silicon carbide single crystal substrate is fixed on the surface of the chuck. Accordingly, a position of the mask pattern to be formed on the other main surface may be deviated from a desired position.
  • a main surface of a silicon carbide single crystal substrate is normally polished using a rotating surface plate.
  • a circumferential speed at the outer circumferential side of the surface plate is faster than the circumferential speed at the central side thereof. Accordingly, a polishing rate at the outer circumferential side of the silicon carbide single crystal substrate is higher than a polishing rate at the central side thereof.
  • the thickness of the silicon carbide single crystal substrate is likely to be thinner from the central side toward the outer circumferential side.
  • the other main surface becomes less flat particularly at the outer circumferential side thereof. Accordingly, position deviation of a mask pattern is more likely to be notable particularly at the outer circumferential side of the other main surface.
  • a silicon carbide single crystal substrate 10 includes a first main surface 10 a and a second main surface 10 b opposite to first main surface 10 a .
  • First main surface 10 a includes: a central square region 1 surrounded by a square having a center corresponding to an intersection O 1 between first main surface 10 a and a straight line L 1 that passes through a center of gravity G of silicon carbide single crystal substrate 10 and that is parallel to a thickness direction TD of silicon carbide single crystal substrate 10 ; and an outer square region 2 surrounded by a square that has a side parallel to a straight line perpendicular to a straight line L 2 connecting intersection O 1 to a certain position on an outer edge 10 c of first main surface 10 a and that has a center O 2 corresponding to a position separated away by 10.5 mm from the certain position toward the intersection.
  • each of central square region 1 and outer square region 2 has a side having a length of 15 mm.
  • First main surface 10 a has a maximum diameter W of not less than 100 mm.
  • Silicon carbide single crystal substrate 10 has a TTV of not more than 5 ⁇ m.
  • a value obtained by dividing a LTIR in central square region 1 by a LTV in central square region 1 is not less than 0.8 and not more than 1.2.
  • a value obtained by dividing a LTV in outer square region 2 by the LTV in central square region 1 is not less than 1 and not more than 3.
  • the value obtained by dividing the LTIR in the central square region by the LTV in the central square region is not less than 0.8 and not more than 1.2.
  • the LTIR is different from the LTV in terms of its reference plane. Therefore, there may be a case where the LTIR is small and the LTV is large, or a case where the LTIR is large and the LTV is small. Hence, by using only one of these parameters, it is difficult to determine the flatness with precision. Therefore, by calculating a ratio of the LTIR and the LTV and controlling the ratio to fall within the above-described range, the flatness in the central square region can be controlled with precision.
  • the value obtained by dividing the LTV in the outer square region by the LTV in the central square region is not less than 1 and not more than 3.
  • maximum diameter W may be not less than 150 mm.
  • maximum diameter W may be not less than 200 mm.
  • a flaw having a depth of not less than 0.5 nm in thickness direction TD may be formed in first main surface 10 a .
  • the flaw may have an area density of not more than 0.085/cm 2 .
  • a value obtained by dividing a LTIR in outer square region 2 by the LTV in outer square region 2 is not less than 0.8 and not more than 1.2.
  • the LTIR is different from the LTV in terms of its reference plane. Therefore, there may be a case where the LTIR is small and the LTV is large, or a case where the LTIR is large and the LTV is small. Hence, by only using one of these parameters, it is difficult to determine the flatness with precision. Therefore, by calculating a ratio of the LTIR and the LTV and controlling the ratio to fall within the above-described range, the flatness in the outer square region can be controlled with precision.
  • a silicon carbide semiconductor device 100 includes silicon carbide single crystal substrate 10 recited in any one of (1) to (5).
  • a silicon carbide semiconductor device 100 includes the following steps. Silicon carbide single crystal substrate 10 recited in any one of (1) to (5) is prepared. Silicon carbide single crystal substrate 10 is processed.
  • a silicon carbide single crystal substrate 10 includes: a first main surface 10 a ; and a second main surface 10 b opposite to first main surface 10 a .
  • Silicon carbide single crystal substrate 10 is composed of hexagonal silicon carbide of polytype 4H, for example.
  • First main surface 10 a corresponds to a ⁇ 0001 ⁇ plane or a plane angled off by about 4° or less relative to the ⁇ 0001 ⁇ plane, for example.
  • First main surface 10 a may correspond to a (0001) plane or a plane angled off by about 4° or less relative to the (0001) plane
  • second main surface 10 b may correspond to a (000-1) plane or a plane angled off by 4° or less relative to the (000-1) plane
  • first main surface 10 a may correspond to the (000-1) plane or the plane angled off by about 4° or less relative to the (000-1) plane
  • second main surface 10 b may correspond to the (0001) plane or the plane angled off by 4° or less relative to the (0001) plane.
  • first main surface 10 a has a substantially circular shape, for example.
  • First main surface 10 a includes a central square region 1 and an outer square region 2 .
  • Central square region 1 is a region surrounded by a square having a center corresponding to an intersection O 1 between first main surface 10 a and a straight line L 1 that passes through a center of gravity G of silicon carbide single crystal substrate 10 (see FIG. 2 ) and that is parallel to a thickness direction TD of silicon carbide single crystal substrate 10 .
  • Central square region 1 is a region surrounded by a square having intersection O 1 as a rotational symmetry center when first main surface 10 a is viewed in thickness direction TD.
  • Outer square region 2 is a region surrounded by a square that has a side parallel to a straight line perpendicular to a straight line L 2 connecting intersection O 1 to a certain position C 2 on an outer edge 10 c of first main surface 10 a and that has a center O 2 corresponding to a position separated away by 10.5 mm from certain position C 2 toward the intersection.
  • Outer square region 2 is a region surrounded by a square having center O 2 as a rotational symmetry center when first main surface 10 a is viewed in thickness direction TD.
  • Thickness direction TD is a direction from second main surface 10 b toward first main surface 10 a .
  • thickness direction TD is a direction perpendicular to first main surface 10 a .
  • thickness direction TD may be a direction perpendicular to a least squares plane of first main surface 10 a , for example.
  • each of central square region 1 and outer square region 2 has a side having a length of 15 mm.
  • central square region 1 has sides parallel to straight line L 2 , and sides perpendicular to both straight line L 2 and straight line L 1 .
  • outer square region 2 has sides parallel to straight line L 2 , and sides perpendicular to both straight line L 2 and straight line L 1 .
  • first main surface 10 a When viewed in thickness direction TD, first main surface 10 a has a maximum diameter W of not less than 100 mm. Maximum diameter W may be not less than 150 mm, or may be not less than 200 mm. Maximum diameter W is the longest linear distance between two different points on the circumferential edge of first main surface 10 a.
  • TTV Total Thickness Variation
  • a TTV is measured in the following procedure, for example. First, second main surface 10 b of silicon carbide single crystal substrate 10 is entirely adsorbed onto a flat adsorption surface. Next, an image of the whole of first main surface 10 a is obtained optically. As shown in FIG. 3 and Formula 1, the TTV is a value obtained by subtracting a height T 2 from a height T 1 with second main surface 10 b being entirely adsorbed on the flat adsorption surface. Height T 1 is a height from second main surface 10 b to a maximum point A 1 of first main surface 10 a , and height T 2 is a height from second main surface 10 b to a minimum point A 2 of first main surface 10 a .
  • the TTV is a value obtained by subtracting the shortest distance between second main surface 10 b and first main surface 10 a from the longest distance between second main surface 10 b and first main surface 10 a in the direction perpendicular to second main surface 10 b .
  • the TTV is a distance between a plane L 3 passing through maximum point A 1 and parallel to second main surface 10 b and a plane L 4 passing through minimum point A 2 and parallel to second main surface 10 b .
  • Silicon carbide single crystal substrate 10 in the present embodiment has a TTV of not more than 5 ⁇ m.
  • the TTV is preferably not more than 3 ⁇ m, more preferably, not more than 1.5 ⁇ m.
  • a LTIR is measured in the following procedure, for example. First, second main surface 10 b of silicon carbide single crystal substrate 10 is entirely adsorbed onto a flat adsorption surface. Next, an image of first main surface 10 a at a certain local region (such as central square region 1 and outer square region 2 ) is obtained optically. Next, a least squares plane L 5 of first main surface 10 a is determined by calculation. As shown in FIG. 4 and Formula 2, the LTIR is a value obtained by adding a height T 4 to a height T 3 with second main surface 10 b being entirely adsorbed on the flat adsorption surface.
  • Height T 4 is a height from least squares plane L 5 to a maximum point A 4 of first main surface 10 a
  • height T 3 is a height from least squares plane L 5 to a minimum point A 3 of first main surface 10 a .
  • Minimum point A 3 refers to a position, at which a distance is maximum between first main surface 10 a and least squares plane L 5 along the direction perpendicular to least squares plane L 5 , in a region of first main surface 10 a located at the second main surface 10 b side relative to least squares plane L 5 .
  • Maximum point A 4 refers to a position, at which a distance is maximum between least squares plane L 5 and first main surface 10 a along the direction perpendicular to least squares plane L 5 , in a region of first main surface 10 a located opposite to the second main surface 10 b side relative to least squares plane L 5 .
  • the LTIR is a distance between a plane L 6 passing through maximum point A 4 and parallel to least squares plane L 5 and a plane L 7 passing through minimum point A 3 and parallel to least squares plane L 5 .
  • the LTIR in central square region 1 is, for example, not more than 1 ⁇ m, and is preferably not more than 0.5.
  • the LTIR in outer square region 2 is, for example, not more than 1 ⁇ m, and is preferably not more than 0.7.
  • a LTV is measured in the following procedure, for example. First, second main surface 10 b of silicon carbide single crystal substrate 10 is entirely adsorbed onto a flat adsorption surface. Next, an image of first main surface 10 a at a certain local region (such as central square region 1 and outer square region 2 ) is obtained optically. As shown in FIG. 5 and Formula 3, the LTV is a value obtained by subtracting a height T 5 from a height T 6 with second main surface 10 b being entirely adsorbed on the flat adsorption surface.
  • Height T 6 is a height from second main surface 10 b to a maximum point A 6 of first main surface 10 a
  • height T 5 is a height from second main surface 10 b to a minimum point A 5 of first main surface 10 a
  • the LTV is a value obtained by subtracting the shortest distance between second main surface 10 b and first main surface 10 a from the longest distance between second main surface 10 b and first main surface 10 a in the direction perpendicular to second main surface 10 b .
  • the LTV is a distance between a plane L 9 passing through maximum point A 6 and parallel to second main surface 10 b and a plane L 10 passing through minimum point A 5 and parallel to second main surface 10 b .
  • the LTV in central square region 1 is, for example, not more than 1 ⁇ m, and is preferably not more than 0.5 ⁇ m.
  • the LTV in outer square region 2 is, for example, not more than 1 ⁇ m, and is preferably not more than 0.8 ⁇ m.
  • Each of the TTV, LTIR, and LTV described above is an index quantitatively indicating a degree of flatness of first main surface 10 a of silicon carbide single crystal substrate 10 .
  • This index can be measured by using “Tropel FlatMaster®” provided by Corning Tropel, for example.
  • a value obtained by dividing the LTIR in central square region 1 by the LTV in central square region 1 is not less than 0.8 and not more than 1.2.
  • a value obtained by dividing the LTIR in central square region 1 by the LTV in central square region 1 is not less than 0.9 and not more than 1.1.
  • a value obtained by dividing the LTV in outer square region 2 by the LTV in central square region 1 is not less than 1 and not more than 3.
  • a value obtained by dividing the LTV in outer square region 2 by the LTV in central square region 1 is not less than 1 and not more than 2.
  • a value obtained by dividing the LTIR in outer square region 2 by the LTV in outer square region 2 is not less than 0.8 and not more than 1.2.
  • a value obtained by dividing the LTIR in outer square region 2 by the LTV in outer square region 2 is not less than 0.9 and not more than 1.1.
  • first main surface 10 a may further include a second outer square region 3 , a third outer square region 4 , and a fourth outer square region 5 .
  • Third outer square region 4 is located opposite to outer square region 2 when viewed from central square region 1 .
  • Third outer square region 4 is a region surrounded by a square that has a side parallel to a straight line perpendicular to a straight line connecting intersection O 1 to a certain position C 4 on outer edge 10 c of first main surface 10 a and that has a center O 4 corresponding to a position separated away by 10.5 mm from certain position C 4 toward intersection O 1 .
  • Second outer square region 3 and fourth outer square region 5 cross a straight line perpendicular to a straight line passing through center O 2 and center O 4 when viewed in thickness direction TD.
  • Second outer square region 3 is a region surrounded by a square that has a side parallel to a straight line perpendicular to a straight line connecting intersection O 1 to a certain position C 3 on outer edge 10 c of first main surface 10 a and that has a center O 3 corresponding to a position separated away by 10.5 mm from certain position C 3 toward intersection O 1 .
  • fourth outer square region 5 is a region surrounded by a square that has a side parallel to a straight line perpendicular to a straight line connecting intersection O 1 to a certain position C 5 on outer edge 10 c of first main surface 10 a and that has a center O 5 corresponding to a position separated away by 10.5 mm from certain position C 5 toward intersection O 1 .
  • Each of second outer square region 3 , third outer square region 4 , and fourth outer square region 5 has a side of 15 mm.
  • a value obtained by dividing a LTV in second outer square region 3 by the LTV in central square region 1 is preferably not less than 1 and not more than 3, more preferably, not less than 1 and not more than 2.
  • a value obtained by dividing a LTV in third outer square region 4 by the LTV in central square region 1 is preferably not less than 1 and not more than 3, more preferably, not less than 1 and not more than 2.
  • a value obtained by dividing a LTV in fourth outer square region 5 by the LTV in central square region 1 is preferably not less than 1 and not more than 3, more preferably, not less than 1 and not more than 2.
  • a value obtained by dividing a LTIR in second outer square region 3 by the LTV in second outer square region 3 is preferably not less than 0.8 and not more than 1.2, more preferably, not less than 0.9 and not more than 1.1.
  • a value obtained by dividing a LTIR in third outer square region 4 by the LTV in third outer square region 4 is preferably not less than 0.8 and not more than 1.2, more preferably, not less than 0.9 and not more than 1.1.
  • a value obtained by dividing a LTIR in fourth outer square region 5 by the LTV in fourth outer square region 5 is preferably not less than 0.8 and not more than 1.2, more preferably, not less than 0.9 and not more than 1.1.
  • a flaw 6 may be formed in first main surface 10 a .
  • Flaw 6 may be a scratch formed by first main surface 10 a being partially cut by diamond abrasive grains during polishing of first main surface 10 a .
  • flaw 6 when viewed in thickness direction TD, flaw 6 may be a line-like flaw extending along a direction in which first main surface 10 a extends.
  • a depth of flaw 6 in thickness direction TD of silicon carbide single crystal substrate 10 is not less than 0.5 nm, for example.
  • An area density of the flaw in first main surface 10 a is not more than 0.085/cm 2 , for example.
  • the size of flaw 6 in thickness direction TD may be smaller than the size of flaw 6 in the direction along first main surface 10 a .
  • the area density of flaw 6 can be measured using a differential interference microscope, for example.
  • first main surface 10 a is a surface on which an epitaxial layer is to be forming when manufacturing a silicon carbide semiconductor device using silicon carbide single crystal substrate 10 .
  • a gate oxide film 36 (see FIG. 12 ) of the silicon carbide semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is to be formed at the first main surface 10 a side. Details of the silicon carbide semiconductor device will be described later.
  • Silicon carbide single crystal substrate 10 is prepared by slicing, using a wire saw, an ingot composed of silicon carbide single crystal produced by a sublimation method, for example.
  • Silicon carbide single crystal substrate 10 is composed of hexagonal silicon carbide of polytype 4H, for example.
  • Silicon carbide single crystal substrate 10 has first main surface 10 a and second main surface 10 b opposite to first main surface 10 a .
  • First main surface 10 a corresponds to the ⁇ 0001 ⁇ plane or the plane angled off by about 4° or less relative to the ⁇ 0001 ⁇ plane, for example.
  • first main surface 10 a and second main surface 10 b are subjected to mechanical polishing and CMP (Chemical Mechanical Polishing).
  • a polishing apparatus 30 is a CMP apparatus, for example.
  • polishing apparatus 30 mainly includes an outer gear 11 , a carrier 12 , an inner gear 13 , an upper surface plate 23 , a lower surface plate 24 , polishing cloths 21 , 22 , and shafts 25 , 26 .
  • Carrier 12 is provided between inner gear 13 and outer gear 11 .
  • Carrier 12 is provided with a plurality of pockets 12 a .
  • Polishing cloth 21 is fixed to upper surface plate 23 .
  • Upper surface plate 23 is fixed to shaft 25 .
  • Polishing cloth 22 is fixed to lower surface plate 24 .
  • Lower surface plate 24 is fixed to shaft 26 .
  • polishing cloths 21 , 22 a nonwoven fabric can be used, for example.
  • Each of polishing cloths 21 , 22 has an Asker-C hardness of not less than 70 and not more than 90, for example.
  • the Asker-C hardness is a hardness measured by an Asker-C hardness meter defined in the Society of Rubber Industry, Japan Standard (SRIS) 0101.
  • SRIS Society of Rubber Industry, Japan Standard
  • Each of polishing cloths 21 , 22 has a compression ratio of not less than 2% and not more than 6%, for example. The compression ratio is measured based on “JIS L 1096”.
  • As each of upper surface plate 23 and lower surface plate 24 a metal such as stainless steel can be used, for example.
  • polishing cloths 21 , 22 are not deformed much along the shapes of the surfaces (i.e., first main surface 10 a and second main surface 10 b ) of silicon carbide single crystal substrate 10 . Therefore, polishing cloths 21 , 22 are in point contact with only projections of the surfaces, and are substantially in no contact with recesses thereof. As a result, the projections of the surfaces are polished more preferentially than the recesses thereof. Accordingly, it is considered that the surfaces are more likely to be flat.
  • silicon carbide single crystal substrate 10 is disposed in each of the plurality of pockets 12 a .
  • first main surface 10 a faces polishing cloth 21
  • second main surface 10 b faces polishing cloth 22 .
  • outer gear 11 is rotated in a rotation direction R 2
  • inner gear 13 is rotated in a rotation direction R 1 .
  • carrier 12 rotates around inner gear 13 in a rotation direction R 3 while revolving on its axis.
  • silicon carbide single crystal substrate 10 rotates around inner gear 13 .
  • Slurry is supplied to between first main surfaces 10 a and polishing cloth 21 and between second main surface 10 b and polishing cloth 22 .
  • the slurry includes diamond abrasive grains and a solution, for example.
  • the solution contains a solvent and a dispersant.
  • the solvent is ethylene glycol, for example.
  • the dispersant can serve to adjust pH and refractive index of the solution.
  • FIG. 11 shows a relation between grain sizes and frequency of the diamond abrasive grains.
  • D 50 represents a grain size of 50% (half) of the total number of diamond abrasive grains when the diamond abrasive grains are added in an order from one with the smallest grain size.
  • D 95 represents a grain size of 95% of the total number of diamond abrasive grains.
  • the grain sizes of the diamond abrasive grains are adjusted to achieve a D 50 of not more than 1 ⁇ m and a D 95 of not more than 1.8 ⁇ m.
  • the refractive index of the solution of the slurry is not less than 1.36 and not more than 1.37, for example.
  • the refractive index can be measured using a digital refractometer (model number: RX-5000 ⁇ -Plus) provided by ATAGO Co. Ltd, for example.
  • a solution having a high refractive index has a high density, resulting in bad smoothness. Since polishing cloths 21 , 22 each having a relatively high hardness are used in the present embodiment, a flaw is likely to be formed in the surface.
  • a solution having a good smoothness in other words, low refractive index
  • the pH (hydrogen ion exponent) of the solution is not less than 7.0 and not more than 8.5, for example.
  • An abrasive grain concentration which is determined by dividing the mass (gram) of the abrasive grains by the volume (liter) of the solution, is not less than 3.60 g/L and 4.00 g/L, for example. Since the diamond abrasive grains each having a relatively small grain size are used in the present embodiment, a polishing rate becomes low. Hence, by increasing the abrasive grain concentration, it is desirable to increase the polishing rate.
  • first main surface 10 a and second main surface 10 b are polished simultaneously by carrier 12 revolving on its axis and rotating with polishing cloth 21 being pressed against first main surface 10 a and polishing cloth 22 being pressed against second main surface 10 b .
  • a load applied to each of first main surface 10 a and second main surface 10 b is 300 g/cm 2 , for example.
  • Upper surface plate 23 and polishing cloth 21 may be unmoved or may be rotated around shaft 25 in a rotation direction R 4 , for example.
  • Lower surface plate 24 and polishing cloth 22 are rotated around shaft 26 in a rotation direction R 5 , for example.
  • Both of upper surface plate 23 and lower surface plate 24 may be rotated or one of upper surface plate 23 and lower surface plate 24 may be rotated and the other may be unmoved.
  • carrier 12 is rotated at 10 rpm
  • lower surface plate 24 and polishing cloth 22 are rotated at 30 rpm
  • a rotating speed of upper surface plate 23 relative to silicon carbide single crystal substrate 10 is 10 rpm
  • a rotating speed of lower surface plate 24 relative to silicon carbide single crystal substrate 10 is 20 rpm (30 rpm ⁇ 10 rpm).
  • the speed of polishing cloth 21 relative to silicon carbide single crystal substrate 10 (i.e., speed of upper surface plate 23 relative to first main surface 10 a ) is desirably slower than the speed of polishing cloth 22 relative to silicon carbide single crystal substrate 10 (i.e., speed of lower surface plate 24 relative to second main surface 10 b ). Accordingly, flaw 6 (see FIG. 7 ) formed in first main surface 10 a can be reduced. Moreover, roughness of first main surface 10 a can be reduced.
  • the speed of upper surface plate 23 relative to silicon carbide single crystal substrate 10 is desirably not more than 1 ⁇ 2 of the speed of lower surface plate 24 relative to silicon carbide single crystal substrate 10 .
  • the value obtained by dividing the LTIR in central square region 1 by the LTV in central square region 1 is not less than 0.8 and not more than 1.2.
  • the LTIR is different from the LTV in terms of its reference plane. Therefore, there may be a case where the LTIR is small and the LTV is large, or a case where the LTIR is large and the LTV is small. Hence, by using only one of these parameters, it is difficult to determine the flatness with precision. Therefore, by calculating a ratio of the LTIR and the LTV and controlling the ratio to fall within the above-described range, the flatness in central square region 1 can be controlled with precision.
  • the value obtained by dividing the LTV in outer square region 2 by the LTV in central square region 1 is not less than 1 and not more than 3.
  • maximum diameter W is not less than 150 mm.
  • maximum diameter W is not less than 200 mm.
  • a flaw 6 having a depth of not less than 0.5 nm in thickness direction TD is formed in first main surface 10 a .
  • Flaw 6 has an area density of not more than 0.085/cm 2 .
  • a value obtained by dividing a LTIR in outer square region 2 by the LTV in outer square region 2 is not less than 0.8 and not more than 1.2.
  • the LTIR is different from the LTV in terms of its reference plane. Therefore, there may be a case where the LTIR is small and the LTV is large, or a case where the LTIR is large and the LTV is small. Hence, by using only one of these parameters, it is difficult to determine the flatness with precision. Therefore, by calculating a ratio of the LTIR and the LTV and controlling the ratio to fall within the above-described range, the flatness in outer square region 2 can be controlled with precision.
  • a MOSFET 100 mainly includes a silicon carbide substrate 70 , a gate oxide film 36 , a gate electrode 40 , an interlayer insulating film 60 , source electrodes 41 , a front surface protecting electrode 42 , a drain electrode 45 , and a backside surface protecting electrode 47 .
  • Silicon carbide substrate 70 has a silicon carbide single crystal substrate 10 and a silicon carbide epitaxial layer 35 , for example. Silicon carbide single crystal substrate 10 is configured as described in the first embodiment.
  • Silicon carbide substrate 70 has a third main surface 70 a and second main surface 10 b opposite to third main surface 70 a .
  • Third main surface 70 a corresponds to the ⁇ 0001 ⁇ plane or a plane angled off by about 4° or less relative to the ⁇ 0001 ⁇ plane.
  • third main surface 70 a corresponds to the (0001) plane or the plane angled off by about 4° or less relative to the (0001) plane
  • second main surface 10 b corresponds to the (000-1) plane or the plane angled off by about 4° or less relative to the (000-1) plane.
  • Silicon carbide single crystal substrate 10 constitutes second main surface 10 b
  • silicon carbide epitaxial layer 35 constitutes third main surface 70 a.
  • Silicon carbide epitaxial layer 35 is provided on silicon carbide single crystal substrate 10 .
  • Silicon carbide epitaxial layer 35 includes a drift region 31 , body regions 32 , source regions 33 , and contact regions 34 , for example.
  • Drift region 31 includes an n type impurity such as N (nitrogen), and has n type conductivity. The concentration of the n type impurity in drift region 31 may be lower than the concentration of the n type impurity in silicon carbide single crystal substrate 10 .
  • Each of body regions 32 includes a p type impurity such as Al (aluminum) or B (boron), and has p type (second conductivity type) conductivity. The concentration of the p type impurity in body region 32 may be higher than the concentration of the n type impurity in drift region 31 .
  • Each of source regions 33 includes an impurity such as P (phosphorus), and has n type conductivity.
  • Source region 33 is separated from drift region 31 by body region 32 .
  • Source region 33 forms a portion of third main surface 70 a .
  • source region 33 may be surrounded by body region 32 .
  • the concentration of the n type impurity in source region 33 may be higher than the concentration of the n type impurity in drift region 31 .
  • Each of contact regions 34 includes a p type impurity such as Al (aluminum) or B (boron), and has p type (second conductivity type) conductivity.
  • Contact region 34 is provided to extend through source region 33 and in contact with both third main surface 70 a and body region 32 .
  • the concentration of the p type impurity in contact region 34 may be higher than the concentration of the p type impurity in body region 32 .
  • Gate oxide film 36 is provided on silicon carbide substrate 70 . Gate oxide film 36 is in contact with each of source region 33 , body region 32 , and drift region 31 on third main surface 70 a . Gate oxide film 36 is composed of silicon dioxide, for example.
  • Gate electrode 40 is provided on gate oxide film 36 . Gate electrode 40 faces each of source region 33 , body region 32 , and drift region 31 . Gate electrode 40 is composed of a conductor such as Al or polysilicon having an impurity implanted therein.
  • source electrode 41 may be provided in contact with source region 33 and contact region 34 .
  • Source electrode 41 may be in contact with gate oxide film 36 .
  • Source electrode 41 is composed of a material including Ti, Al, and Si, for example.
  • source electrode 41 is in ohmic junction with source region 33 .
  • source electrode 41 is in ohmic junction with contact region 34 .
  • Interlayer insulating film 60 covers gate electrode 40 .
  • Interlayer insulating film 60 is in contact with gate electrode 40 and gate oxide film 36 .
  • Interlayer insulating film 60 electrically insulates gate electrode 40 from source electrode 41 .
  • Front surface protecting electrode 42 covers interlayer insulating film 60 .
  • Front surface protecting electrode 42 is composed of a material including Al, for example. Front surface protecting electrode 42 is electrically connected to source electrode 41 .
  • Drain electrode 45 is provided in contact with second main surface 10 b .
  • Drain electrode 45 is composed of a material including NiSi, for example. Drain electrode 45 is in ohmic junction with silicon carbide single crystal substrate 10 , for example.
  • Backside surface protecting electrode 47 is in contact with drain electrode 45 .
  • Backside surface protecting electrode 47 is composed of a material including Al, for example. Backside surface protecting electrode 47 is electrically connected to drain electrode 45 .
  • the method for manufacturing the MOSFET mainly includes: a step (S 10 : FIG. 13 ) of preparing a silicon carbide single crystal substrate; and a step (S 20 : FIG. 13 ) of processing the silicon carbide single crystal substrate.
  • a step (S 10 : FIG. 13 ) of preparing the silicon carbide single crystal substrate silicon carbide single crystal substrate 10 described in the first embodiment is prepared.
  • silicon carbide epitaxial layer 35 is epitaxially grown on first main surface 10 a of silicon carbide single crystal substrate 10 (see FIG. 14 ).
  • silane (SiH 4 ) and propane (C 3 H 8 ) are used as a source material gas, whereas hydrogen (H 2 ) is used as carrier gas, for example.
  • the temperature of silicon carbide single crystal substrate 10 during the epitaxial growth is about not less than 1400° C. and not more than 1700° C., for example.
  • Silicon carbide single crystal substrate 10 and silicon carbide epitaxial layer 35 constitute silicon carbide substrate 70 .
  • an ion implantation step is performed.
  • Al (aluminum) ions are implanted into third main surface 70 a of silicon carbide substrate 70 , thereby forming body region 32 of p type conductivity in silicon carbide epitaxial layer 35 .
  • P (phosphorus) ions are implanted into body region 32 at a depth shallower than the depth in which the Al ions have been implanted, thereby forming source region 33 of n type conductivity.
  • Al ions are further implanted into source region 33 , thereby forming contact region 34 having p type conductivity and extending to body region 32 through source region 33 .
  • silicon carbide epitaxial layer 35 a region in which none of body region 32 , source region 33 , and contact region 34 is formed serves as drift region 31 (see FIG. 15 ).
  • Silicon carbide substrate 70 is heated at a temperature of, for example, 1700° C. for about 30 minutes, thereby activating the impurity ions implanted in the ion implantation step. Accordingly, desired carriers are generated in the regions having the impurity ions implanted therein.
  • a gate oxide film forming step is performed.
  • silicon carbide substrate 70 is heated in an atmosphere including oxygen, whereby gate oxide film 36 including silicon dioxide is formed on third main surface 70 a of silicon carbide substrate 70 .
  • Silicon carbide substrate 70 is heated at a temperature of, for example, about 1300° C. for about 60 minutes.
  • Gate oxide film 36 is formed in contact with each of drift region 31 , body region 32 , source region 33 , and contact region 34 on third main surface 70 a.
  • gate electrode 40 composed of polysilicon including an impurity is formed on gate oxide film 36 .
  • Gate electrode 40 is formed at a position facing each of gate oxide film 36 , source region 33 , body region 32 , and drift region 31 (see FIG. 16 ).
  • interlayer insulating film forming step is performed.
  • interlayer insulating film 60 is formed in contact with gate oxide film 36 to cover gate electrode 40 .
  • Interlayer insulating film 60 is composed of a material including silicon dioxide, for example.
  • a source electrode forming step is performed. For example, etching is performed to remove interlayer insulating film 60 and gate oxide film 36 from a region in which source electrode 41 is to be formed. This leads to formation of a region in which source region 33 and contact region 34 are exposed through gate oxide film 36 .
  • a metal layer including TiAlSi (titanium aluminum silicon) is formed on the region in which source region 33 and contact region 34 are exposed (see FIG. 17 ).
  • the metal layer is heated to, for example, about 1000° C. to result in silicidation of at least a portion of the metal layer. Accordingly, source electrode 41 is formed in ohmic junction with source region 33 .
  • a front surface protecting electrode forming step is performed.
  • front surface protecting electrode 42 is formed in contact with source electrode 41 to cover interlayer insulating film 60 .
  • Front surface protecting electrode 42 is composed of a material including aluminum, for example.
  • a front surface electrode 50 including source electrode 41 and front surface protecting electrode 42 is formed in contact with third main surface 70 a of silicon carbide substrate 70 .
  • drain electrode 45 is formed in contact with second main surface 10 b . Drain electrode 45 includes NiSi, for example.
  • backside surface protecting electrode 47 is formed in contact with drain electrode 45 .
  • Backside surface protecting electrode 47 is composed of a material including aluminum, for example.
  • silicon carbide substrate 70 is diced into a plurality of semiconductor chips.
  • the step of processing silicon carbide single crystal substrate 10 is not limited to the step described above.
  • the step of processing silicon carbide single crystal substrate 10 may be: a step of forming a semiconductor layer on silicon carbide single crystal substrate 10 ; a step of cutting silicon carbide single crystal substrate 10 ; a step of forming an electrode electrically connected to silicon carbide single crystal substrate 10 ; or the like.
  • the first conductivity type is n type and the second conductivity type is p type; however, the first conductivity type may be p type and the second conductivity type may be n type.
  • the silicon carbide semiconductor device is a MOSFET; however, the silicon carbide semiconductor device may be an IGBT (Insulated Gate Bipolar Transistor), a SBD (Schottky Barrier Diode), a LED (Light Emitting Diode), a JFET (Junction Field Effect Transistor), or the like.
  • Silicon carbide single crystal substrates 10 are polished under polishing conditions for groups 1 to 5. Specifically, polishing apparatus 30 described in FIG. 10 is used to polish each silicon carbide single crystal substrate 10 . Upper surface plate 23 is fixed whereas lower surface plate 24 is rotated. As shown in Table 1, the rotating speeds (rpm) of lower surface plate 24 for groups 1, 2, 3, 4, and 5 are respectively 30, 40, 20, 20, and 20. The relative speed ratio (the upper surface plate to the lower surface plate) of the surface plates for groups 1, 2, 3, 4, and 5 are respectively 1:2, 1:3, 1:1, 2:1, and 1:2.
  • the refractive indices of lubricants (slurry solutions) for groups 1, 2, 3, 4, and 5 are respectively 1.365, 1.36, 1.245, 1.245, and 1.245.
  • the pHs of the lubricants for groups 1, 2, 3, 4, and 5 are respectively 7.6, 7.1, 7.6, 7.1, and 7.1.
  • the Asker-C hardnesses of the polishing cloths for groups 1, 2, 3, 4, and 5 are respectively 82, 82, 82, 52, and 60.
  • the loads (g/cm 2 ) of the upper surface plate and the lower surface plate for groups 1, 2, 3, 4, and 5 are respectively 300, 300, 200, 300, and 200.
  • First main surfaces 10 a and second main surfaces 10 b of silicon carbide single crystal substrates 10 are polished under the polishing conditions above.
  • silicon carbide single crystal substrates 10 are produced for each group.
  • a sample 1-1, a sample 1-2, and a sample 1-3 are silicon carbide single crystal substrates 10 produced under the polishing condition for group 1.
  • a sample 2-1, a sample 2-2, and a sample 2-3 are silicon carbide single crystal substrates 10 produced under the polishing condition for group 2.
  • Maximum diameter W (see FIG. 1 ) of first main surface 10 a of each of silicon carbide single crystal substrates 10 is 100 mm.
  • TTV, LTV, and LTIR of each of silicon carbide single crystal substrates 10 polished in accordance with the polishing methods for corresponding groups are measured.
  • the TTV, LTV, and LTIR are measured using “Tropel FlatMaster®” provided by Corning Tropel.
  • the definitions of the TTV, LTV, and LTIR are described in the above-described embodiment.
  • First main surface 10 a is observed optically with the entire surface of second main surface 10 b being made flat as a result of being adsorbed onto a vacuum chuck, thereby measuring the TTV, LTV, and LTIR.
  • the LTV and LTIR are measured in each of central square region 1 and outer square region 2 of first main surface 10 a .
  • the definitions of central square region 1 and outer square region 2 are described in the above-described embodiment.
  • Each of Table 2 and Table 3 shows results of measurement of: the TTV; the LTV in central square region 1 (indicated as LTV(central) in Table 2 and Table 3); the LTV in outer square region 2 (indicated as LTV(outer) in Table 2 and Table 3); the LTIR in central square region 1 (indicated as LTIR(central) in Table 2 and Table 3); and the LTIR in outer square region 2 (indicated as LTIR(outer) in Table 2 and Table 3).
  • a LTV(outer)/LTV(central) is calculated by dividing the LTV(outer) by the LTV(central).
  • a LTIR(central)/LTV(central) is calculated by dividing the LTIR(central) by the LTV(central).
  • a LTIR(outer)/LTV(outer) is calculated by dividing the LTIR(outer) by the LTV(outer).
  • Table 2 shows the TTV, LTV(outer)/LTV(central), LTIR(central)/LTV(central), and LTIR(outer)/LTV(outer) of each of the samples produced under the polishing conditions for groups 1 and 2.
  • the TTV of each of silicon carbide single crystal substrates 10 for sample 1-1 to sample 2-3 is not less than 1.15 and not more than 1.30. That is, the TTV of each of silicon carbide single crystal substrate 10 for sample 1-1 to sample 2-3 is not more than 5.
  • the LTV(outer)/LTV(central) of each of silicon carbide single crystal substrates 10 for sample 1-1 to sample 2-3 is not less than 1.13 and not more than 2.33.
  • the LTV(outer)/LTV(central) of each of silicon carbide single crystal substrates 10 for samples 1-1 to sample 2-3 is not less than 1 and not more than 3.
  • the LTIR(central)/LTV(central) of each of silicon carbide single crystal substrates 10 for sample 1-1 to sample 2-3 is not less than 0.80 and not more than 0.87. That is, the LTIR(central)/LTV(central) of each of silicon carbide single crystal substrates 10 for sample 1-1 to sample 2-3 is not less than 0.8 and not more than 1.2.
  • the LTIR(outer)/LTV(outer) of each of silicon carbide single crystal substrates 10 for sample 1-1 to sample 2-3 is not less than 0.80 and not more than 0.87. That is, the LTIR(outer)/LTV(outer) of each of silicon carbide single crystal substrates 10 for sample 1-1 to sample 2-3 is not less than 0.8 and not more than 1.2.
  • Table 3 shows the TTV, LTV(outer)/LTV(central), LTIR(central)/LTV(central), and LTIR(outer)/LTV(outer) of each of the samples produced under the polishing conditions for groups 3, 4, and 5.
  • the TTV of each of silicon carbide single crystal substrates 10 for sample 3-1 to sample 5-3 is not less than 1.57 and not more than 4.33. That is, the TTV of each of silicon carbide single crystal substrates 10 produced under the polishing conditions for groups 3, 4, and 5 is larger than the TTV of each of silicon carbide single crystal substrates 10 produced under the polishing conditions for groups 1 and 2.
  • the LTV(outer)/LTV(central) of silicon carbide single crystal substrate 10 for sample 3-2 is less than 1.
  • the LTV(outer)/LTV(central) of each of silicon carbide single crystal substrates 10 for sample 3-1 and sample 4-1 is larger than 3.
  • the LTIR(central)/LTV(central) of each of silicon carbide single crystal substrates 10 for sample 3-1, sample 3-2, sample 3-3, sample 4-2, sample 4-3, sample 5-1, sample 5-2, and sample 5-3 is less than 0.8.
  • the LTIR(central)/LTV(central) of silicon carbide single crystal substrate 10 for sample 4-1 is larger than 1.2.
  • the LTIR(outer)/LTV(outer) of each of silicon carbide single crystal substrates 10 for sample 3-1, sample 3-2, sample 3-3, sample 4-1, sample 4-2, sample 4-3, sample 5-2, and sample 5-3 is less than 0.8.

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