US8951809B2 - Method of transfer by means of a ferroelectric substrate - Google Patents

Method of transfer by means of a ferroelectric substrate Download PDF

Info

Publication number
US8951809B2
US8951809B2 US12/936,582 US93658209A US8951809B2 US 8951809 B2 US8951809 B2 US 8951809B2 US 93658209 A US93658209 A US 93658209A US 8951809 B2 US8951809 B2 US 8951809B2
Authority
US
United States
Prior art keywords
substrate
components
layer
placing
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US12/936,582
Other versions
US20110104829A1 (en
Inventor
Jean-Sebastien Moulet
Lea Di Cioccio
Marion Migette
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES reassignment COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DI CIOCCIO, LEA, MIGETTE, MARION, MOULET, JEAN-SEBASTIEN
Publication of US20110104829A1 publication Critical patent/US20110104829A1/en
Application granted granted Critical
Publication of US8951809B2 publication Critical patent/US8951809B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • H01L21/187Joining of semiconductor bodies for junction formation by direct bonding
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S414/00Material or article handling
    • Y10S414/135Associated with semiconductor wafer handling
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S414/00Material or article handling
    • Y10S414/135Associated with semiconductor wafer handling
    • Y10S414/141Associated with semiconductor wafer handling includes means for gripping wafer

Definitions

  • the invention relates to substrate transfer techniques, which are used in particular in microelectronics.
  • a temporary support also known as a “handle”.
  • On such a support may be temporarily fixed one or more components, which may then again be transferred onto another, definitive support.
  • the support or the handle substrate may then be reused for another transfer.
  • the problem is often posed of being able to detach in a simple manner the component(s) that have been fixed temporarily onto the handle substrate.
  • components tend to be smaller and smaller, and known transfer techniques, and thus the substrates commonly used as handles, are not always adapted to constantly decreasing dimensions.
  • the invention relates to a method of carrying out a transfer of one or more first components or of a first layer on a first substrate to a second substrate, comprising the following steps:
  • Step a) implements the internal field of the substrate made of ferroelectric material, which is charged in an intrinsic manner.
  • the dismantling of the first substrate may be assisted:
  • the ferroelectric material of the first substrate is LTO (LiTaO 3 ) or a material of same structure as LTO, such as LiNbO 3 , BaTiO 3 , or SrTiO 3 , or LaAlO 3 , or LiAlO 3 , or any other ferroelectric material.
  • One or more of said components, or said layer may have undergone, before step a), or undergo, between step a) and step b), a treatment by etching, and/or ion implantation, and/or deposition and/or a thermal treatment.
  • a fragilization area is formed in at least one of said components or said layer, along which a fracture is made during step c).
  • a fragilization area is formed in at least one of said components or said layer, along which a fracture is made between step a) and step b).
  • the layer transferred during step c) may be more or less thick.
  • a layer may be deposited on the surface of the ferroelectric material, to promote the bonding, for example a layer of silicon oxide SiO 2 or a polymer (PDMS, BCB) with weak or very weak strength or adhesion.
  • a layer of silicon oxide SiO 2 or a polymer (PDMS, BCB) with weak or very weak strength or adhesion for example a layer of silicon oxide SiO 2 or a polymer (PDMS, BCB) with weak or very weak strength or adhesion.
  • the transfer operation may be carried out in several stages, in particular by means of the same first ferroelectric substrate, a layer being thus transferred, or components being thus transferred, onto an already transferred layer, or onto already transferred components, which makes it possible to form stacks or stages of components on a same second substrate.
  • the object of the invention is also a method of carrying out a transfer of at least two stages of components and/or layer onto a second substrate, comprising the following steps:
  • the transfer of a second stage may be carried out by:
  • the transfer of the first stage may be carried out with the same substrate, made of a ferroelectric material, as the transfer of the second stage.
  • a method according to the invention enables a novel method of handling a film or stamps, while having a temporary support, by electrostatic bonding.
  • FIGS. 1A-1D represent a first embodiment of the invention
  • FIGS. 2A-2B represent a second embodiment of the invention, with transfer of two stages
  • FIGS. 3A-3D represent a method according to the invention, with transfer of a layer
  • FIGS. 4A-4D represent another method of transfer of a portion of a layer, according to the invention, comprising a step of implantation and a step of fracture of said layer,
  • FIGS. 5A-5C represent yet another method of transfer of a portion of a layer, according to the invention, comprising a step of implantation and a step of fracture of said layer,
  • FIGS. 6A-6C represent another method of transfer of parts of stamps, according to the invention, comprising a step of implantation and a step of fracture of said stamps,
  • FIGS. 7A-7C represent yet another method of transfer of parts of stamps according to the invention, comprising a step of implantation and a step of fracture of said stamps.
  • a first example of method according to the invention will be given with reference to FIGS. 1A-1C , starting with a first substrate 2 , solid or in thin film, made of ferroelectric material, for example LiTaO 3 .
  • ferroelectric material for example LiTaO 3 .
  • This type of material just as the other ferroelectric materials that can be used cited above, have an intrinsic polarisation that is going to be able to be exploited within the scope of the present invention.
  • Components 8 , 10 for example of the “stamp” type (hereafter, the term component or stamp are used indiscriminately) are deposited on this substrate 2 ( FIG. 1A ).
  • These components are for example substrates of semi-conductor materials, comprising, or not, circuits. They are mainly based on silicon or germanium or AsGa or InP or other materials.
  • the reference 30 designates possible alignment marks on the substrate 2 , which will make it possible to achieve later a good alignment on a second substrate 20 , or transfer substrate, particularly if alignment marks are also provided on the second substrate 20 .
  • These components 8 , 10 may be of all sizes, they are for example chips. Each side of one of these components may measure between several micrometers and several millimeters or several centimeters, for example between 1 ⁇ m or 5 ⁇ m and 1 mm or 5 mm or 5 cm.
  • each component may be such that they cannot be handled individually.
  • its thickness may be of the order of several nanometers to several tens of nanometers, for example between 5 nm or 10 nm and 50 nm. This is the case, in particular, of certain stamps or certain chips.
  • a transfer technique according to the invention makes this stamp or this chip handleable.
  • the thickness of the components may also be higher, for example 750 ⁇ m or more, or even several millimeters.
  • the surfaces 8 ′, 10 ′ ( FIG. 1A ) of the various components may be arranged substantially at the same height h in relation to the surface 2 ′ of the first substrate 2 on which these components are deposited.
  • these surfaces 8 ′ and 10 ′ may not be at the same height h in relation to this same surface 2 ′ of the substrate 2 .
  • at least one of the components comprises at least one surface made of a material having an elasticity or compliant, for example a polymer. It has been shown by Jourdain et al. “ BCB Collective Hybrid Bonding for 3 D - Stacking ” Conference on Wafer Bonding for MEMS Technologies and Wafer Level Integration, 2007 that a compliant polymer layer, for example made of BCB, can accept during transfers height differences of more than 3 mm.
  • the components 8 , 10 may have undergone a step of treatment for the purpose of promoting the contact or the adhesion with the surface 2 ′ of the first substrate 2 , for example a treatment by polishing or by plasma activation.
  • This type of treatment may reveal, at the interface between the stamps and the surface 2 ′ of the substrate 2 , several monolayers of water.
  • each component or stamp 8 , 10 on the first substrate 2 is obtained by the natural electrical charges of this substrate 2 .
  • the spontaneous polarisation of the latter may be reinforced by the application of an electric field.
  • the components 8 , 10 may undergo one or more treatments, for example an etching, and/or an ion implantation, and/or a deposition, etc.; in the case of steps with elevation of temperature, the ramp(s) are chosen, during the thermal budget, in such a way as not to have a polarisation inversion phenomenon of the first substrate (ferroelectric); typically, one or more ramp(s) less than 5° C./minute are used.
  • the temperature is limited to a value less than the Curie temperature Tc of the ferroelectric material (for tantalate, this Curie temperature is equal to around 600° C.; for niobate it is around 1200° C.).
  • the components 8 , 10 may be prepared for the purpose of a direct or molecular bonding with the surface 20 ′ of the second transfer substrate 20 , if necessary after, or in combination with, one or more of the previous treatments.
  • the assembly obtained may thus also, as illustrated in FIG. 1B , then be positioned facing such a transfer substrate 20 , on which the components or the stamps are going to be transferred.
  • the alignment mark(s) 30 may aid the relative positioning of the two substrates 2 , 20 .
  • the transfer substrate 20 is for example made of silicon or another semi-conductor material, or any other material such as fused silica or quartz.
  • the surface 8 ′, 10 ′ of the components or stamps 8 , 10 and the surface 20 ′ of the second substrate 20 are placed in contact.
  • the adhesion of the stamps on the latter is of molecular bonding type, which makes it possible to maintain them on the support or the second substrate 20 , in a firmer manner than they are held, by electrostatic effect, on the first substrate 2 .
  • the latter may thus be removed ( FIG. 1D ), the components being transferred onto the substrate 20 .
  • the disbondment may be obtained by thermal effect, or instead a thermal effect may assist the mechanical effect to disbond the stamps from the substrate 2 .
  • a step of heating makes it possible to carry out the separation of the components 8 , 10 from the substrate 2 .
  • This heating (to temperature of several hundreds of ° C., for example between 100° C. or 500° C. and 1200° C., for a time between several minutes and several hours, for example between 1 h or 4 h and 10 h or even 30 h) also makes it possible to reinforce the direct or molecular adhesion of the components 8 , 10 on the second substrate 20 , compared to the adhesion on the substrate 2 .
  • differences between the thermal expansion coefficients of the materials of the substrates 2 and 20 and/or between the thermal expansion coefficients of the materials of the substrate or substrates 2 and/or 20 and the stamps 8 , 10 may also promote a disbondment of the first substrate. This is in particular the case if the thermal expansion coefficient of the material of the first substrate is greater than that of the stamps 8 , 10 .
  • This condition is met for LTO (just as for the other ferroelectric materials already envisaged for the substrate 2 ), which expands in general more than the stamps (mainly made of semi-conductor material). The latter thus do not move or barely move.
  • an increasing thermal ramp may be applied.
  • a thermal ramp greater than 5° C./min an accumulation of charges in the material of the substrate 2 enables a discharge of the latter and thus enables or promotes the disbondment.
  • a disbondment of the substrate 2 is thus carried out by thermal effect or by combination of mechanical and thermal or electrical and thermal effects.
  • FIG. 1D Another embodiment of the invention will be explained starting with a second substrate 20 , identical or similar to that of FIG. 1D , thus to which a plurality of stamps 8 , 10 , forming a first stage, already adhere.
  • Components 8 ′′, 10 ′′, for example of the same type as those mentioned above, are going to be deposited on this first stage.
  • the second stage of components 8 ′′, 10 ′′, etc. may be deposited on the first stage of components 8 , 10 .
  • the bond between 8 and 8 ′′, 10 and 10 ′′ may be of the same nature as the previous bond between substrate 20 and components 8 , 10 , it may also be achieved by means of adhesive.
  • This transfer of a second stage may be carried out by means of the same ferroelectric substrate 2 as the transfer of the first stage.
  • Marks 30 , 30 ′ are identified in the substrates 2 , 20 of FIG. 2A .
  • This alternative of the invention makes it possible to form stacks or stages of components on the second substrate 20 .
  • FIG. 2B a component or a stamp 8 ′′, 10 ′′ is indicated in superposition of each component or stamp 8 , 10 , but this is not obligatory, the distribution of the components or stamps 8 ′′, 10 ′′ on the first stage may be different.
  • the substrate 2 is represented, as explained above, after having been disbonded or separated by the components 8 ′′, 10 ′′ by thermal effect or by combination of mechanical and thermal or electrical and thermal effects.
  • FIGS. 3A-3C it is possible to maintain a complete layer 18 , for example made of at least one of the semi-conductor materials already cited, on the ferroelectric substrate 2 (if necessary provided, once again, with alignment marks 30 ). Then, a transfer is carried out on the substrate 20 ( FIGS. 3B and 3C ), with assistance of one or more of the effects already mentioned (mechanical, and/or thermal, and/or electrostatic). The first stage is thereby formed.
  • a second stage may be transferred onto the layer 18 of FIG. 3C , this may be a stage of components or stamps 8 ′′, 10 ′′ or a stage comprising a second layer.
  • FIG. 3D represents the result of a double transfer, firstly that of a layer 18 , then, on this layer, components 8 ′′, 10 ′′.
  • This transfer of a second stage may be carried out by means of the same ferroelectric substrate 2 as the transfer of the first stage, and according to one of the methods described above.
  • Another embodiment implements a method of substrate fracture, such as the “Smart CutTM” method, for example described in the article of B. Aspar and A. J. Auberton—Hervé “Silicon Wafer Bonding Technology for VLSI and MEMS applications”, edited by S. S. Iyer and A. J. Auberton—Hervé, 2002, INSPEC, London, Chapter 3, pages 35-52, or instead in the documents already cited above.
  • Smart CutTM a method of substrate fracture
  • FIGS. 4A to 4D illustrate an example of implementation of such a thin film producing or transferring method. These figures are cross-sectional views.
  • FIG. 4A shows the ferroelectric substrate of FIG. 3A , with its layer 18 as described above, but in an enlarged manner in FIG. 4A , undergoing a step of implantation of a gaseous species, symbolised by the arrows 3 .
  • a silicon layer 18 it is possible for example to implant hydrogen at an energy of 200 keV and a dose of the order of 6.10 16 H + /cm 2 .
  • a buried area 19 is then formed constituting a fragilized area, which delimits two parts in the layer 18 :
  • An assembly of the implanted layer 18 is then carried out, by its face 18 ′ through which the implantation has been carried out, with the transfer substrate 20 ( FIG. 4B ).
  • FIG. 4C illustrates a step of separation, induced by thermal and/or mechanical effect, of the thin film 21 and the remaining part 23 of the layer 18 , along the fragilized area 19 .
  • the structure of FIG. 4D remains, namely the thin film 21 on the transfer substrate 20 .
  • FIGS. 5A to 5C an implantation in a layer (or a substrate) 18 is firstly carried out.
  • a layer (or a substrate) 18 In the case of silicon, reference will be made to the implantation values given above.
  • a buried area 19 ′ is thus obtained constituting a fragilized area, which separates the layer 18 into two parts:
  • FIG. 5B An assembly ( FIG. 5B ) of the implanted layer 18 is then carried out, by its face 18 ′′ through which the implantation has been carried out, with the ferroelectric substrate 2 .
  • FIG. 5B The structure of FIG. 5B is obtained. This structure is then subjected to a separation, induced by thermal and/or mechanical effect, of the thin film 23 ′ and the remaining part 21 ′ of the layer 18 , along the fragilized area 19 ′. The result of this step is represented in FIG. 5C , the layer 23 ′ being assembled with the substrate 2 .
  • FIGS. 6A to 6C illustrate an example of implementation of a method of transferring implanted stamps.
  • the assembly of stamps with a ferroelectric substrate 2 is of the type described above with reference to FIG. 1A .
  • the stamps 80 , 100 of FIG. 6A are represented in an enlarged manner compared to those of FIG. 1A .
  • the implantation takes place after this assembly with the substrate 2 and a fragilization area 80 ′, 100 ′ is thereby formed in each of the stamps 80 , 100 .
  • FIG. 6B represents the assembly obtained after transfer of the stamps from substrate 2 onto the substrate 20 , but before the step of separation.
  • a structure results comprising, on the transfer substrate 20 , a plurality of thin films 82 , 102 , each one of which results from the fracture of one of the stamps 80 , 100 along the plane 80 ′, 100 ′.
  • FIGS. 7A to 7C illustrate an example of implementation of a method of transferring implanted stamps.
  • a fragilization area 80 ′, 100 ′ has thus been formed in each of the stamps 80 , 100 , but this fragilization area is this time close to the surface of said stamps, which is assembled with the substrate 2 .
  • FIG. 7B represents the assembly obtained after transfer of the stamps from the substrate 2 onto the substrate 20 , but before the step of separation.
  • a structure results comprising, on the transfer substrate 20 , a plurality of thin films 82 , 102 , each one of which results from the fracture of one of the stamps 80 , 100 along the plane 80 ′, 100 ′.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Laminated Bodies (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)
  • Inorganic Insulating Materials (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A method of carrying out a transfer of one or more first components or of a first layer onto a second substrate including: a) application and maintaining, by electrostatic effect, of the one or more first components or of the first layer, on a first substrate, made of a ferroelectric material, electrically charged, b) placing in contact, direct or by molecular adhesion, and transfer of the components or the layer onto a second substrate, and c) dismantling of the first substrate, leaving at least one part of the components or the layer on the second substrate.

Description

TECHNICAL FIELD AND PRIOR ART
The invention relates to substrate transfer techniques, which are used in particular in microelectronics.
In this field, it is often aimed to use a temporary support, also known as a “handle”. On such a support may be temporarily fixed one or more components, which may then again be transferred onto another, definitive support. The support or the handle substrate may then be reused for another transfer.
The problem is often posed of being able to detach in a simple manner the component(s) that have been fixed temporarily onto the handle substrate.
Moreover, components tend to be smaller and smaller, and known transfer techniques, and thus the substrates commonly used as handles, are not always adapted to constantly decreasing dimensions.
DESCRIPTION OF THE INVENTION
The invention relates to a method of carrying out a transfer of one or more first components or of a first layer on a first substrate to a second substrate, comprising the following steps:
a) the placing in contact, against the first substrate, made of a ferroelectric material, of the first component(s) or the first layer, and maintaining them by electrostatic effect against this first substrate,
b) a placing in contact, direct or by molecular adhesion, of these first components or this first layer with the second substrate,
c) a separation or a dismantling of the first substrate, leaving at least one part of each of said components or of said layer on the second substrate.
Step a) implements the internal field of the substrate made of ferroelectric material, which is charged in an intrinsic manner.
Consequently, there are no leaks of charges and the polarisation may be maintained as is as long as there are no discharges by an exterior intervention. There is thus no time limit to the use of the assembly between the first substrate and the components or the first layer.
The dismantling of the first substrate may be assisted:
    • thermally, in particular by effect of the difference in thermal expansion between the first and the second substrate, or by application of a rapid thermal ramp (greater than or equal to 5° C./min), which introduces a discharge effect by accumulation of charges. A rise in temperature moreover enables the direct contact to be reinforced,
    • and/or mechanically, in particular by an effect of bending the second substrate, which induces a disbondment of the first substrate 1, the bonding of the components being stronger at the interface with the second substrate. The direct contact of the component(s) on the second substrate is going to make it possible to retain them on it when the first substrate is going to be moved away,
    • and/or in an electrostatic manner, in particular by inversion of the polarisation by heating or by an inverse polarisation.
Advantageously, the ferroelectric material of the first substrate is LTO (LiTaO3) or a material of same structure as LTO, such as LiNbO3, BaTiO3, or SrTiO3, or LaAlO3, or LiAlO3, or any other ferroelectric material.
Advantageously, it is possible to carry out on the surface of the second substrate a preparation for the purpose of a molecular bonding, the components or the layer then being placed in contact with this prepared surface and assembled with it by molecular bonding.
One or more of said components, or said layer, may have undergone, before step a), or undergo, between step a) and step b), a treatment by etching, and/or ion implantation, and/or deposition and/or a thermal treatment.
In the case of a treatment by ion implantation before step a), or between step a) and step b), a fragilization area is formed in at least one of said components or said layer, along which a fracture is made during step c).
In the case of a treatment by ion implantation before step a), a fragilization area is formed in at least one of said components or said layer, along which a fracture is made between step a) and step b).
Depending on the depth of the implantation and the face of the components or the layer traversed by the implantation, the layer transferred during step c) may be more or less thick.
A layer may be deposited on the surface of the ferroelectric material, to promote the bonding, for example a layer of silicon oxide SiO2 or a polymer (PDMS, BCB) with weak or very weak strength or adhesion.
The transfer operation may be carried out in several stages, in particular by means of the same first ferroelectric substrate, a layer being thus transferred, or components being thus transferred, onto an already transferred layer, or onto already transferred components, which makes it possible to form stacks or stages of components on a same second substrate.
Thus the object of the invention is also a method of carrying out a transfer of at least two stages of components and/or layer onto a second substrate, comprising the following steps:
    • carrying out a transfer of a first stage of one or more first components or of a first layer onto said second substrate, according to the invention disclosed above, by means of a first substrate, made of a ferroelectric material,
    • then the carrying out of a transfer of a second stage of one or more second components or of a second layer, onto said first stage.
The transfer of a second stage may be carried out by:
a′) the application and the maintaining, by electrostatic effect, of said one or more second components or said second layer, on said first stage, by means of a substrate, made of a ferroelectric material, electrically charged,
b′) a placing in contact and a transfer of these components or this layer onto said first stage,
c′) a dismantling of said substrate made of a ferroelectric material, leaving the component(s) or said second layer on the first stage.
The transfer of the first stage may be carried out with the same substrate, made of a ferroelectric material, as the transfer of the second stage.
Whatever the embodiment, a method according to the invention enables a novel method of handling a film or stamps, while having a temporary support, by electrostatic bonding.
BRIEF DESCRIPTION OF DRAWINGS
FIGS. 1A-1D represent a first embodiment of the invention,
FIGS. 2A-2B represent a second embodiment of the invention, with transfer of two stages,
FIGS. 3A-3D represent a method according to the invention, with transfer of a layer,
FIGS. 4A-4D represent another method of transfer of a portion of a layer, according to the invention, comprising a step of implantation and a step of fracture of said layer,
FIGS. 5A-5C represent yet another method of transfer of a portion of a layer, according to the invention, comprising a step of implantation and a step of fracture of said layer,
FIGS. 6A-6C represent another method of transfer of parts of stamps, according to the invention, comprising a step of implantation and a step of fracture of said stamps,
FIGS. 7A-7C represent yet another method of transfer of parts of stamps according to the invention, comprising a step of implantation and a step of fracture of said stamps.
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
A first example of method according to the invention will be given with reference to FIGS. 1A-1C, starting with a first substrate 2, solid or in thin film, made of ferroelectric material, for example LiTaO3. This type of material, just as the other ferroelectric materials that can be used cited above, have an intrinsic polarisation that is going to be able to be exploited within the scope of the present invention.
Components 8, 10, for example of the “stamp” type (hereafter, the term component or stamp are used indiscriminately) are deposited on this substrate 2 (FIG. 1A). These components are for example substrates of semi-conductor materials, comprising, or not, circuits. They are mainly based on silicon or germanium or AsGa or InP or other materials.
The reference 30 designates possible alignment marks on the substrate 2, which will make it possible to achieve later a good alignment on a second substrate 20, or transfer substrate, particularly if alignment marks are also provided on the second substrate 20.
These components 8, 10 may be of all sizes, they are for example chips. Each side of one of these components may measure between several micrometers and several millimeters or several centimeters, for example between 1 μm or 5 μm and 1 mm or 5 mm or 5 cm.
The dimensions, and in particular the thickness of each component, may be such that they cannot be handled individually. In particular, its thickness may be of the order of several nanometers to several tens of nanometers, for example between 5 nm or 10 nm and 50 nm. This is the case, in particular, of certain stamps or certain chips. A transfer technique according to the invention makes this stamp or this chip handleable.
The thickness of the components may also be higher, for example 750 μm or more, or even several millimeters.
The surfaces 8′, 10′ (FIG. 1A) of the various components may be arranged substantially at the same height h in relation to the surface 2′ of the first substrate 2 on which these components are deposited.
In an alternative, these surfaces 8′ and 10′ may not be at the same height h in relation to this same surface 2′ of the substrate 2. This is the case in particular if at least one of the components comprises at least one surface made of a material having an elasticity or compliant, for example a polymer. It has been shown by Jourdain et al. “BCB Collective Hybrid Bonding for 3D-Stacking” Conference on Wafer Bonding for MEMS Technologies and Wafer Level Integration, 2007 that a compliant polymer layer, for example made of BCB, can accept during transfers height differences of more than 3 mm.
Prior to the deposition, the components 8, 10 may have undergone a step of treatment for the purpose of promoting the contact or the adhesion with the surface 2′ of the first substrate 2, for example a treatment by polishing or by plasma activation. This type of treatment may reveal, at the interface between the stamps and the surface 2′ of the substrate 2, several monolayers of water.
Advantageously, it is possible to carry out the same type of preparation on the surface 20′ of the second substrate 20, for the purpose of a molecular bonding. But said bonding 20-20′ may also be achieved by means of adhesive.
The electrostatic adhesion of each component or stamp 8, 10 on the first substrate 2 is obtained by the natural electrical charges of this substrate 2. The spontaneous polarisation of the latter may be reinforced by the application of an electric field.
Once maintained on the substrate 2, the components 8, 10 may undergo one or more treatments, for example an etching, and/or an ion implantation, and/or a deposition, etc.; in the case of steps with elevation of temperature, the ramp(s) are chosen, during the thermal budget, in such a way as not to have a polarisation inversion phenomenon of the first substrate (ferroelectric); typically, one or more ramp(s) less than 5° C./minute are used. Moreover, the temperature is limited to a value less than the Curie temperature Tc of the ferroelectric material (for tantalate, this Curie temperature is equal to around 600° C.; for niobate it is around 1200° C.).
In an alternative, the components 8, 10 may be prepared for the purpose of a direct or molecular bonding with the surface 20′ of the second transfer substrate 20, if necessary after, or in combination with, one or more of the previous treatments.
The assembly obtained may thus also, as illustrated in FIG. 1B, then be positioned facing such a transfer substrate 20, on which the components or the stamps are going to be transferred. The alignment mark(s) 30 may aid the relative positioning of the two substrates 2, 20.
The transfer substrate 20 is for example made of silicon or another semi-conductor material, or any other material such as fused silica or quartz.
The surface 8′, 10′ of the components or stamps 8, 10 and the surface 20′ of the second substrate 20 (FIG. 1C) are placed in contact. The adhesion of the stamps on the latter is of molecular bonding type, which makes it possible to maintain them on the support or the second substrate 20, in a firmer manner than they are held, by electrostatic effect, on the first substrate 2. The latter may thus be removed (FIG. 1D), the components being transferred onto the substrate 20. There is thus a disbondment, or a separation, of the substrate 2 by mechanical effect, or due to the difference of adhesion force between the adhesion of the components or stamps 8, 10 on the ferroelectric substrate 2 and their adhesion on the substrate 20, the latter being greater. This may moreover bring about a difference of bending between the two substrates, which induces, or promotes, the disbondment. All of these steps are preferably carried out at ambient temperature, between 20° C. and 30° C. for example, except for the treatments of implantation and/or deposition type.
In an alternative, the disbondment may be obtained by thermal effect, or instead a thermal effect may assist the mechanical effect to disbond the stamps from the substrate 2.
More specifically, a step of heating makes it possible to carry out the separation of the components 8, 10 from the substrate 2. This heating (to temperature of several hundreds of ° C., for example between 100° C. or 500° C. and 1200° C., for a time between several minutes and several hours, for example between 1 h or 4 h and 10 h or even 30 h) also makes it possible to reinforce the direct or molecular adhesion of the components 8, 10 on the second substrate 20, compared to the adhesion on the substrate 2.
Under the effect of temperature, differences between the thermal expansion coefficients of the materials of the substrates 2 and 20 and/or between the thermal expansion coefficients of the materials of the substrate or substrates 2 and/or 20 and the stamps 8, 10 may also promote a disbondment of the first substrate. This is in particular the case if the thermal expansion coefficient of the material of the first substrate is greater than that of the stamps 8, 10. This condition is met for LTO (just as for the other ferroelectric materials already envisaged for the substrate 2), which expands in general more than the stamps (mainly made of semi-conductor material). The latter thus do not move or barely move.
During the disbondment step, an increasing thermal ramp may be applied. In particular, under the effect of a thermal ramp greater than 5° C./min, an accumulation of charges in the material of the substrate 2 enables a discharge of the latter and thus enables or promotes the disbondment.
A disbondment of the substrate 2 is thus carried out by thermal effect or by combination of mechanical and thermal or electrical and thermal effects.
Another embodiment of the invention will be explained starting with a second substrate 20, identical or similar to that of FIG. 1D, thus to which a plurality of stamps 8, 10, forming a first stage, already adhere. Components 8″, 10″, for example of the same type as those mentioned above, are going to be deposited on this first stage.
By the same transfer technique as that already described by means of the ferromagnetic substrate 2, the second stage of components 8″, 10″, etc. may be deposited on the first stage of components 8, 10. The bond between 8 and 8″, 10 and 10″ may be of the same nature as the previous bond between substrate 20 and components 8, 10, it may also be achieved by means of adhesive. This transfer of a second stage may be carried out by means of the same ferroelectric substrate 2 as the transfer of the first stage.
Once again, an appropriate marking made for example both on the substrate 2 and the substrate 20, makes it possible to achieve a good alignment and a good superposition of the components on top of each other. Marks 30, 30′ are identified in the substrates 2, 20 of FIG. 2A.
This alternative of the invention makes it possible to form stacks or stages of components on the second substrate 20.
In FIG. 2B a component or a stamp 8″, 10″ is indicated in superposition of each component or stamp 8, 10, but this is not obligatory, the distribution of the components or stamps 8″, 10″ on the first stage may be different. In this figure, the substrate 2 is represented, as explained above, after having been disbonded or separated by the components 8″, 10″ by thermal effect or by combination of mechanical and thermal or electrical and thermal effects.
What has been described for individual components or stamps applies to a single layer: as illustrated in FIGS. 3A-3C, it is possible to maintain a complete layer 18, for example made of at least one of the semi-conductor materials already cited, on the ferroelectric substrate 2 (if necessary provided, once again, with alignment marks 30). Then, a transfer is carried out on the substrate 20 (FIGS. 3B and 3C), with assistance of one or more of the effects already mentioned (mechanical, and/or thermal, and/or electrostatic). The first stage is thereby formed.
A second stage may be transferred onto the layer 18 of FIG. 3C, this may be a stage of components or stamps 8″, 10″ or a stage comprising a second layer. FIG. 3D represents the result of a double transfer, firstly that of a layer 18, then, on this layer, components 8″, 10″.
This transfer of a second stage may be carried out by means of the same ferroelectric substrate 2 as the transfer of the first stage, and according to one of the methods described above.
Another embodiment implements a method of substrate fracture, such as the “Smart Cut™” method, for example described in the article of B. Aspar and A. J. Auberton—Hervé “Silicon Wafer Bonding Technology for VLSI and MEMS applications”, edited by S. S. Iyer and A. J. Auberton—Hervé, 2002, INSPEC, London, Chapter 3, pages 35-52, or instead in the documents already cited above.
FIGS. 4A to 4D illustrate an example of implementation of such a thin film producing or transferring method. These figures are cross-sectional views.
FIG. 4A shows the ferroelectric substrate of FIG. 3A, with its layer 18 as described above, but in an enlarged manner in FIG. 4A, undergoing a step of implantation of a gaseous species, symbolised by the arrows 3. For a silicon layer 18, it is possible for example to implant hydrogen at an energy of 200 keV and a dose of the order of 6.1016 H+/cm2. A buried area 19 is then formed constituting a fragilized area, which delimits two parts in the layer 18:
    • a thin film 21, of thickness between several nm and several hundreds of micrometers, for example between 10 nm and 200 μm, situated between the face 18′, through which the implantation has taken place, and the fragilized area 19,
    • and the remaining part 23 of the layer 18, situated between the fragilized area 19 and the substrate 20.
An assembly of the implanted layer 18 is then carried out, by its face 18′ through which the implantation has been carried out, with the transfer substrate 20 (FIG. 4B).
For these operations, the techniques used are those already described above.
FIG. 4C illustrates a step of separation, induced by thermal and/or mechanical effect, of the thin film 21 and the remaining part 23 of the layer 18, along the fragilized area 19. The structure of FIG. 4D remains, namely the thin film 21 on the transfer substrate 20.
In an alternative (FIGS. 5A to 5C), an implantation in a layer (or a substrate) 18 is firstly carried out. In the case of silicon, reference will be made to the implantation values given above.
A buried area 19′ is thus obtained constituting a fragilized area, which separates the layer 18 into two parts:
    • a thin film 23′, of thickness between several nm and several hundreds of micrometers, for example between 10 nm and 200 μm, situated between the face 18″ through which the implantation has taken place and the fragilized area 19′,
    • and the remaining part 21′ of the layer, situated between the fragilized area 19′ and the face 18′ opposite to that by which the previous implantation took place.
An assembly (FIG. 5B) of the implanted layer 18 is then carried out, by its face 18″ through which the implantation has been carried out, with the ferroelectric substrate 2.
The structure of FIG. 5B is obtained. This structure is then subjected to a separation, induced by thermal and/or mechanical effect, of the thin film 23′ and the remaining part 21′ of the layer 18, along the fragilized area 19′. The result of this step is represented in FIG. 5C, the layer 23′ being assembled with the substrate 2.
An assembly of the layer 23′ is then carried out, by its free face 23′-1, with the transfer substrate 20: these are the steps described above with reference to FIG. 3A and following figures.
FIGS. 6A to 6C illustrate an example of implementation of a method of transferring implanted stamps.
The assembly of stamps with a ferroelectric substrate 2 is of the type described above with reference to FIG. 1A. The stamps 80, 100 of FIG. 6A are represented in an enlarged manner compared to those of FIG. 1A. The implantation takes place after this assembly with the substrate 2 and a fragilization area 80′, 100′ is thereby formed in each of the stamps 80, 100.
The corresponding steps are similar to those described above for FIGS. 4A-4E, but with stamps 80, 100 instead of a layer such as the layer 18. Thus FIG. 6B represents the assembly obtained after transfer of the stamps from substrate 2 onto the substrate 20, but before the step of separation.
After separation, a structure (FIG. 6C) results comprising, on the transfer substrate 20, a plurality of thin films 82, 102, each one of which results from the fracture of one of the stamps 80, 100 along the plane 80′, 100′.
FIGS. 7A to 7C illustrate an example of implementation of a method of transferring implanted stamps.
The implantation takes place this time before assembly with the ferroelectric substrate 2 (thus before the step represented in FIG. 7A). A fragilization area 80′, 100′ has thus been formed in each of the stamps 80, 100, but this fragilization area is this time close to the surface of said stamps, which is assembled with the substrate 2.
The corresponding steps are similar to those described above for FIGS. 5A-5C, but with stamps 80, 100 instead of a layer such as the layer 18. Thus FIG. 7B represents the assembly obtained after transfer of the stamps from the substrate 2 onto the substrate 20, but before the step of separation.
After separation, a structure (FIG. 7C) results comprising, on the transfer substrate 20, a plurality of thin films 82, 102, each one of which results from the fracture of one of the stamps 80, 100 along the plane 80′, 100′.

Claims (22)

The invention claimed is:
1. A method of carrying out a transfer of one or more first components or of a first layer, from a first substrate to a second substrate, comprising:
a) placing in contact, against the first substrate, made of a ferroelectric material, the one or more first components or the first layer, and maintaining them by electrostatic effect against the first substrate, the first substrate being electrically charged;
b) placing in contact, direct or by molecular adhesion, the one or more first components or the first layer with the second substrate; and
c) separating or dismantling the first substrate, leaving at least one part of each of the one or more first components or the first layer on the second substrate,
wherein the separating or dismantling the first substrate is performed either
(i) by inversion of the polarization of the first substrate, or
(ii) by heating at a temperature of between 100° C. and 1,200° C.
2. The method according to claim 1, the c) separating or dismantling being assisted thermally and/or mechanically and/or in an electrostatic manner.
3. The method according to claim 2, the c) separating or dismantling being assisted by a rise in temperature.
4. The method according to claim 3, the rise in temperature being carried out by application of an increasing thermal ramp, of gradient greater than 5° C./min.
5. The method according to claim 1, the c) separating or dismantling being assisted by a difference between adhesion forces of the one or more first components or of the first layer on the first substrate and on the second substrate.
6. The method according to of claim 1, the first substrate being charged in an intrinsic or assisted manner.
7. The method according to claim 1, the ferroelectric material of the first substrate being made of LiTaO3, or LiNbO3, or BaTiO3, or SrTiO3, or LaAlO3, or LiAlO3.
8. The method according to claim 1, the second substrate being at least partially made of semi-conductor material, or silicon, or fused silica, or quartz.
9. The method according to claim 1, the one or more first components or the first layer being at least partially made of semi-conductor material.
10. The method according to claim 1, the one or more first components, or the first layer, having undergone before the a) placing, or undergoing, between the a) placing and the b) placing, a treatment by etching, and/or ion implantation, and/or deposition, and/or a thermal treatment.
11. The method according to claim 10, the one or more first components, or the first layer, having undergone before the a) placing, or undergoing, between the a) placing and the b) placing, a treatment by ion implantation, defining in at least one of the one or more first components or in the first layer, a fragilization area, along which a fracture is formed during the c) separating or dismantling.
12. The method according to claim 10, the one or more first components, or the first layer, having undergone, before the a) placing, a treatment by ion implantation, defining in at least one of the one or more first components or in the first layer, a fragilization area, along which a fracture is formed between the a) placing and the b) placing.
13. The method according to claim 10, the thermal treatment not inducing polarization inversion of the material of the first substrate.
14. The method according to claim 13, the thermal treatment being carried out by application of an increasing thermal ramp, of gradient less than 5° C./min.
15. The method according to claim 1, at least one of the one or more first components, or the first layer, and/or a surface of the first substrate having undergone at least one treatment for promoting contact or adhesion of the component with the surface.
16. The method according to claim 1, a surface of the second substrate and/or a surface of at least one of the one or more first components or of the first layer, having undergone, before the b) placing, a preparation for molecular bonding.
17. The method according to claim 1, a surface of one of the one or more first components not being at a same height as a surface of at least another one of the one or more first components in relation to a surface of the second substrate on which the one or more first components are deposited.
18. The method according to claim 1, at least one of the one or more components comprising at least one surface made of a compliant or elastic material.
19. A method of carrying out a transfer of at least two stages of components and/or of layers onto a second substrate, comprising:
carrying out a first transfer of a first stage of one or more first components or of a first layer from a first substrate onto said second substrate, comprising:
a) placing in contact, against the first substrate, made of a ferroelectric material, the one or more first components or the first layer, and maintaining them by electrostatic effect against the first substrate, the first substrate being electrically charged;
b) placing in contact, direct or by molecular adhesion, the one or more first components or the first layer with the second substrate; and
c) separating or dismantling the first substrate, leaving at least one part of each of the one or more first components or of the first layer on the second substrate,
then carrying out a second transfer of a second stage of one or more second components or of a second layer, onto the first stage.
20. The method according to claim 19, the transfer of the second stage being carried out by:
a′) applying and maintaining, by electrostatic effect, the one or more second components or the second layer, on the first stage, by a third substrate, made of the ferroelectric material and being electrically charged;
b′) placing in contact and transferring the one or more second components or the second layer onto the first stage; and
c′) separating or dismantling the third substrate, leaving the one or more second components or the second layer on the first stage.
21. The method according to claim 20, wherein the third substrate and the first substrate are the same substrate.
22. A method of carrying out a transfer of one or more first components or of a first layer, from a first substrate to a second substrate, comprising:
a) placing in contact, against the first substrate, made of a ferroelectric material, the one or more first components or the first layer, and maintaining them by electrostatic effect against the first substrate, the first substrate being electrically charged;
b) placing in contact, direct or by molecular adhesion, the one or more first components or the first layer with the second substrate; and
c) separating or dismantling the first substrate, leaving at least one part of each of the one or more first components or the first layer on the second substrate,
wherein the one or more first components, or the first layer, having undergone, before the a) placing, a treatment by ion implantation, defining in at least one of the one or more first components or in the first layer, a fragilization area, along which a fracture is formed between the a) placing and the b) placing.
US12/936,582 2008-04-07 2009-04-03 Method of transfer by means of a ferroelectric substrate Expired - Fee Related US8951809B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0852302A FR2929758B1 (en) 2008-04-07 2008-04-07 TRANSFER METHOD USING A FERROELECTRIC SUBSTRATE
FR0852302 2008-04-07
PCT/EP2009/054007 WO2009124886A1 (en) 2008-04-07 2009-04-03 Method of transfer using a ferroelectric substrate

Publications (2)

Publication Number Publication Date
US20110104829A1 US20110104829A1 (en) 2011-05-05
US8951809B2 true US8951809B2 (en) 2015-02-10

Family

ID=40118822

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/936,582 Expired - Fee Related US8951809B2 (en) 2008-04-07 2009-04-03 Method of transfer by means of a ferroelectric substrate

Country Status (6)

Country Link
US (1) US8951809B2 (en)
EP (1) EP2263251B1 (en)
JP (2) JP2011517103A (en)
AT (1) ATE542237T1 (en)
FR (1) FR2929758B1 (en)
WO (1) WO2009124886A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150194550A1 (en) * 2012-07-03 2015-07-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Detachment of a self-supporting layer of silicon <100>

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015210384A1 (en) 2015-06-05 2016-12-08 Soitec Method for mechanical separation for a double-layer transfer
WO2017052646A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Island transfer for optical, piezo and rf applications
FR3078822B1 (en) * 2018-03-12 2020-02-28 Soitec PROCESS FOR THE PREPARATION OF A THIN LAYER OF ALKALINE BASED FERROELECTRIC MATERIAL
US10926521B2 (en) * 2018-12-28 2021-02-23 Palo Alto Research Center Incorporated Method and system for mass assembly of thin film materials

Citations (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04100256A (en) 1990-08-20 1992-04-02 Fujitsu Ltd Treater provided with electrostatic suction mechanism and separation of materiel to be sucked
EP0621130A2 (en) 1993-04-23 1994-10-26 Canon Kabushiki Kaisha Solid phase bonding method
US5467002A (en) 1993-11-05 1995-11-14 Reliance Medical Products, Inc. Adjustable chair having programmable control switches
US5652173A (en) 1996-05-09 1997-07-29 Philips Electronics North America Corporation Monolithic microwave circuit with thick conductors
US5874747A (en) 1996-02-05 1999-02-23 Advanced Technology Materials, Inc. High brightness electroluminescent device emitting in the green to ultraviolet spectrum and method of making the same
WO1999041776A1 (en) 1998-02-13 1999-08-19 Picogiga, Societe Anonyme Semiconductor material epitaxial structures formed on thin-film substrates
JPH11307413A (en) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd Method for reusing peeled wafer and silicon wafer to be provided for reuse
US6010579A (en) 1997-05-12 2000-01-04 Silicon Genesis Corporation Reusable substrate for thin film separation
WO2000015885A1 (en) 1998-09-10 2000-03-23 France Telecom Method for obtaining a monocrystalline germanium layer on a monocrystalline silicon substrate, and resulting products
WO2000077846A1 (en) 1999-06-14 2000-12-21 France Telecom Method for making a silicon substrate comprising a buried thin silicon oxide film
WO2001015215A1 (en) 1999-08-20 2001-03-01 S.O.I.Tec Silicon On Insulator Technologies Method for treating substrates for microelectronics and substrates obtained according to said method
EP1156531A1 (en) 1999-11-29 2001-11-21 Shin-Etsu Handotai Company Limited Method for recycled separated wafer and recycled separated wafer
WO2001093325A1 (en) 2000-05-30 2001-12-06 Commissariat A L'energie Atomique Embrittled substrate and method for making same
WO2002027783A1 (en) 2000-09-29 2002-04-04 International Business Machines Corporation PREPARATION OF A RELAXED SiGe LAYER ON AN INSULATOR
JP2002141282A (en) 2000-08-24 2002-05-17 Nichia Chem Ind Ltd Method for growing nitride semiconductor and nitride semiconductor substrate
US6426270B1 (en) 1999-02-02 2002-07-30 Canon Kabushiki Kaisha Substrate processing method and method of manufacturing semiconductor substrate
US20020125475A1 (en) 1999-03-12 2002-09-12 Chu Jack Oon High speed composite p-channel Si/SiGe heterostructure for field effect devices
US6468923B1 (en) 1999-03-26 2002-10-22 Canon Kabushiki Kaisha Method of producing semiconductor member
US6500732B1 (en) 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
US20030010275A1 (en) 1998-02-17 2003-01-16 Radojevic Antonije M. Method for fabricating ultra thin single-crystal metal oxide wave retarder plates and waveguide polarization mode converter using the same
US6573126B2 (en) 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US6690043B1 (en) 1999-11-26 2004-02-10 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20040029365A1 (en) 2001-05-07 2004-02-12 Linthicum Kevin J. Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby
US20040053477A1 (en) 2002-07-09 2004-03-18 S.O.I. Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
WO2004061943A1 (en) 2003-01-07 2004-07-22 S.O.I.Tec Silicon On Insulator Technologies Recycling by mechanical means of a wafer comprising a taking-off structure after taking-off a thin layer thereof
US20040185638A1 (en) 2003-02-14 2004-09-23 Canon Kabushiki Kaisha Substrate manufacturing method
US20050026426A1 (en) 2003-07-29 2005-02-03 Christophe Maleville Method for producing a high quality useful layer on a substrate
US20050029224A1 (en) 2001-04-13 2005-02-10 Bernard Aspar Detachable substrate or detachable structure and method for the production thereof
JP2005064194A (en) 2003-08-11 2005-03-10 Seiko Epson Corp Semiconductor substrate having soi structure, manufacturing method thereof and semiconductor device
US20050083634A1 (en) * 2001-11-16 2005-04-21 Kalus Breitschwerdt Retaining device, especially for fixing a semiconductor wafer in a plasma etching device, and method for supply heat to or discharging heat from a substrate
US6890835B1 (en) 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
US6936523B2 (en) 2002-12-10 2005-08-30 S.O.I.Tec Silicon On Insulator Technologies S.A. Two-stage annealing method for manufacturing semiconductor substrates
US20050196937A1 (en) 2004-03-05 2005-09-08 Nicolas Daval Methods for forming a semiconductor structure
US20050248378A1 (en) 2004-03-20 2005-11-10 Neil Gibson Method of generating a pulsed output signal from a periodic ramp signal and a reference voltage, and a switch mode power converter
US7052979B2 (en) 2001-02-14 2006-05-30 Toyoda Gosei Co., Ltd. Production method for semiconductor crystal and semiconductor luminous element
WO2006093817A2 (en) 2005-02-28 2006-09-08 Silicon Genesis Corporation Substrate stiffness method and resulting devices
US20060270188A1 (en) * 2005-05-20 2006-11-30 Sony Corporation Device transferring system, device transferring method, and display manufacturing method
US20070048891A1 (en) * 2001-04-11 2007-03-01 Sony Corporation Device transferring method, and device arraying method
US20070087526A1 (en) 2005-10-18 2007-04-19 Nabil Chhaimi Method of recycling an epitaxied donor wafer
EP1777735A2 (en) 2005-10-18 2007-04-25 S.O.I.Tec Silicon on Insulator Technologies Recycling process of an epitaxial donor wafer
US7256075B2 (en) 2003-01-07 2007-08-14 S.O.I.Tec Silicon On Insulator Technologies Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer
JP2007208031A (en) 2006-02-02 2007-08-16 Nikon Corp Wafer holder, and method for manufacturing semiconductor device
US7268060B2 (en) 2002-04-23 2007-09-11 S.O.I.Tec Silicon On Insulator Technologies Method for fabricating a substrate with useful layer on high resistivity support
US7297611B2 (en) 2003-08-12 2007-11-20 S.O.I.Tec Silicon On Insulator Technologies Method for producing thin layers of semiconductor material from a donor wafer
JP2008041927A (en) 2006-08-07 2008-02-21 Shinko Electric Ind Co Ltd Manufacturing method of electrostatic chuck
US20080271835A1 (en) 2005-12-27 2008-11-06 Commissariat A L'energie Atomique Method for Relaxing a Stressed Thin Film
US20090325362A1 (en) 2003-01-07 2009-12-31 Nabil Chhaimi Method of recycling an epitaxied donor wafer
US20110033976A1 (en) 2008-04-09 2011-02-10 Commiss. A L'energie Atom. Et Aux Energ. Alterna. Self-assembly of chips on a substrate

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04206948A (en) * 1990-11-30 1992-07-28 Kyocera Corp Electrostatic chuck
JP3076727B2 (en) * 1994-10-19 2000-08-14 東芝機械株式会社 Sample holder fixing device
JP3864612B2 (en) * 1999-03-16 2007-01-10 富士ゼロックス株式会社 Method and apparatus for manufacturing microstructure
JP3910081B2 (en) * 2002-02-26 2007-04-25 東京応化工業株式会社 Electrostatic chuck device and method for removing from electrostatic chuck device
JP3885939B2 (en) * 2002-03-13 2007-02-28 日本碍子株式会社 Manufacturing method of optical waveguide device
JP2004349665A (en) * 2003-05-23 2004-12-09 Creative Technology:Kk Electrostatic chuck
FR2855909B1 (en) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator PROCESS FOR THE CONCURRENT PRODUCTION OF AT LEAST ONE PAIR OF STRUCTURES COMPRISING AT LEAST ONE USEFUL LAYER REPORTED ON A SUBSTRATE
JP2008216869A (en) * 2007-03-07 2008-09-18 Matsushita Electric Ind Co Ltd Manufacturing method of optical element

Patent Citations (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04100256A (en) 1990-08-20 1992-04-02 Fujitsu Ltd Treater provided with electrostatic suction mechanism and separation of materiel to be sucked
EP0621130A2 (en) 1993-04-23 1994-10-26 Canon Kabushiki Kaisha Solid phase bonding method
US5536354A (en) 1993-04-23 1996-07-16 Canon Kabushiki Kaisha Solid phase bonding method
US5467002A (en) 1993-11-05 1995-11-14 Reliance Medical Products, Inc. Adjustable chair having programmable control switches
US5874747A (en) 1996-02-05 1999-02-23 Advanced Technology Materials, Inc. High brightness electroluminescent device emitting in the green to ultraviolet spectrum and method of making the same
WO1997042654A2 (en) 1996-05-09 1997-11-13 Philips Electronics N.V. A method of making a monolithic microwave circuit with thick conductors
US5652173A (en) 1996-05-09 1997-07-29 Philips Electronics North America Corporation Monolithic microwave circuit with thick conductors
US6010579A (en) 1997-05-12 2000-01-04 Silicon Genesis Corporation Reusable substrate for thin film separation
WO1999041776A1 (en) 1998-02-13 1999-08-19 Picogiga, Societe Anonyme Semiconductor material epitaxial structures formed on thin-film substrates
FR2775121A1 (en) 1998-02-13 1999-08-20 Picogiga Sa METHOD FOR MANUFACTURING THIN FILM SUBSTRATES OF SEMICONDUCTOR MATERIAL, EPITAXIAL STRUCTURES OF SEMICONDUCTOR MATERIAL FORMED ON SUCH SUBSTRATES, AND COMPONENTS OBTAINED FROM SUCH STRUCTURES
US20030010275A1 (en) 1998-02-17 2003-01-16 Radojevic Antonije M. Method for fabricating ultra thin single-crystal metal oxide wave retarder plates and waveguide polarization mode converter using the same
JPH11307413A (en) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd Method for reusing peeled wafer and silicon wafer to be provided for reuse
US6284628B1 (en) 1998-04-23 2001-09-04 Shin-Etsu Handotai Co., Ltd. Method of recycling a delaminated wafer and a silicon wafer used for the recycling
WO2000015885A1 (en) 1998-09-10 2000-03-23 France Telecom Method for obtaining a monocrystalline germanium layer on a monocrystalline silicon substrate, and resulting products
US6537370B1 (en) 1998-09-10 2003-03-25 FRANCE TéLéCOM Process for obtaining a layer of single-crystal germanium on a substrate of single-crystal silicon, and products obtained
US6426270B1 (en) 1999-02-02 2002-07-30 Canon Kabushiki Kaisha Substrate processing method and method of manufacturing semiconductor substrate
US20020125475A1 (en) 1999-03-12 2002-09-12 Chu Jack Oon High speed composite p-channel Si/SiGe heterostructure for field effect devices
US6468923B1 (en) 1999-03-26 2002-10-22 Canon Kabushiki Kaisha Method of producing semiconductor member
WO2000077846A1 (en) 1999-06-14 2000-12-21 France Telecom Method for making a silicon substrate comprising a buried thin silicon oxide film
US6500732B1 (en) 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
WO2001015215A1 (en) 1999-08-20 2001-03-01 S.O.I.Tec Silicon On Insulator Technologies Method for treating substrates for microelectronics and substrates obtained according to said method
US6690043B1 (en) 1999-11-26 2004-02-10 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
EP1156531A1 (en) 1999-11-29 2001-11-21 Shin-Etsu Handotai Company Limited Method for recycled separated wafer and recycled separated wafer
US6596610B1 (en) 1999-11-29 2003-07-22 Shin-Etsu Handotai Co. Ltd. Method for reclaiming delaminated wafer and reclaimed delaminated wafer
WO2001093325A1 (en) 2000-05-30 2001-12-06 Commissariat A L'energie Atomique Embrittled substrate and method for making same
US6573126B2 (en) 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
JP2002141282A (en) 2000-08-24 2002-05-17 Nichia Chem Ind Ltd Method for growing nitride semiconductor and nitride semiconductor substrate
US6524935B1 (en) 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
WO2002027783A1 (en) 2000-09-29 2002-04-04 International Business Machines Corporation PREPARATION OF A RELAXED SiGe LAYER ON AN INSULATOR
US6890835B1 (en) 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
US7052979B2 (en) 2001-02-14 2006-05-30 Toyoda Gosei Co., Ltd. Production method for semiconductor crystal and semiconductor luminous element
US20070048891A1 (en) * 2001-04-11 2007-03-01 Sony Corporation Device transferring method, and device arraying method
US20050029224A1 (en) 2001-04-13 2005-02-10 Bernard Aspar Detachable substrate or detachable structure and method for the production thereof
US20040029365A1 (en) 2001-05-07 2004-02-12 Linthicum Kevin J. Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby
US20050083634A1 (en) * 2001-11-16 2005-04-21 Kalus Breitschwerdt Retaining device, especially for fixing a semiconductor wafer in a plasma etching device, and method for supply heat to or discharging heat from a substrate
US7268060B2 (en) 2002-04-23 2007-09-11 S.O.I.Tec Silicon On Insulator Technologies Method for fabricating a substrate with useful layer on high resistivity support
US20040053477A1 (en) 2002-07-09 2004-03-18 S.O.I. Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
US6936523B2 (en) 2002-12-10 2005-08-30 S.O.I.Tec Silicon On Insulator Technologies S.A. Two-stage annealing method for manufacturing semiconductor substrates
US7602046B2 (en) 2003-01-07 2009-10-13 S.O.I.Tec Silicon On Insulator Technologies Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof
US20050150447A1 (en) 2003-01-07 2005-07-14 Bruno Ghyselen Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof
US20050189323A1 (en) 2003-01-07 2005-09-01 Bruno Ghyselen Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof
US7375008B2 (en) 2003-01-07 2008-05-20 S.O.I.Tec Silicon On Insulator Technologies Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof
EP1588415A1 (en) 2003-01-07 2005-10-26 S.O.I.Tec Silicon on Insulator Technologies Recycling by mechanical means of a wafer comprising a taking-off structure after taking-off a thin layer thereof
WO2004061943A1 (en) 2003-01-07 2004-07-22 S.O.I.Tec Silicon On Insulator Technologies Recycling by mechanical means of a wafer comprising a taking-off structure after taking-off a thin layer thereof
US7256075B2 (en) 2003-01-07 2007-08-14 S.O.I.Tec Silicon On Insulator Technologies Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer
US20100167500A1 (en) 2003-01-07 2010-07-01 S.O.Tec Silicon On Insulator Technologies Method of recycling an epitaxied donor wafer
US20090325362A1 (en) 2003-01-07 2009-12-31 Nabil Chhaimi Method of recycling an epitaxied donor wafer
US20040185638A1 (en) 2003-02-14 2004-09-23 Canon Kabushiki Kaisha Substrate manufacturing method
US20050026426A1 (en) 2003-07-29 2005-02-03 Christophe Maleville Method for producing a high quality useful layer on a substrate
JP2005064194A (en) 2003-08-11 2005-03-10 Seiko Epson Corp Semiconductor substrate having soi structure, manufacturing method thereof and semiconductor device
US7297611B2 (en) 2003-08-12 2007-11-20 S.O.I.Tec Silicon On Insulator Technologies Method for producing thin layers of semiconductor material from a donor wafer
US20050196937A1 (en) 2004-03-05 2005-09-08 Nicolas Daval Methods for forming a semiconductor structure
US20050248378A1 (en) 2004-03-20 2005-11-10 Neil Gibson Method of generating a pulsed output signal from a periodic ramp signal and a reference voltage, and a switch mode power converter
WO2006093817A2 (en) 2005-02-28 2006-09-08 Silicon Genesis Corporation Substrate stiffness method and resulting devices
US20060270188A1 (en) * 2005-05-20 2006-11-30 Sony Corporation Device transferring system, device transferring method, and display manufacturing method
FR2892228A1 (en) 2005-10-18 2007-04-20 Soitec Silicon On Insulator METHOD FOR RECYCLING AN EPITAXY DONOR PLATE
EP1777735A2 (en) 2005-10-18 2007-04-25 S.O.I.Tec Silicon on Insulator Technologies Recycling process of an epitaxial donor wafer
US20070087526A1 (en) 2005-10-18 2007-04-19 Nabil Chhaimi Method of recycling an epitaxied donor wafer
US20080271835A1 (en) 2005-12-27 2008-11-06 Commissariat A L'energie Atomique Method for Relaxing a Stressed Thin Film
JP2007208031A (en) 2006-02-02 2007-08-16 Nikon Corp Wafer holder, and method for manufacturing semiconductor device
JP2008041927A (en) 2006-08-07 2008-02-21 Shinko Electric Ind Co Ltd Manufacturing method of electrostatic chuck
US20110033976A1 (en) 2008-04-09 2011-02-10 Commiss. A L'energie Atom. Et Aux Energ. Alterna. Self-assembly of chips on a substrate

Non-Patent Citations (10)

* Cited by examiner, † Cited by third party
Title
A. Jourdain, et al., "BCB Collective Hybrid Bonding for 3D-Stacking", Conference on Wafer Bonding for MEMS Technologies and Wafer Level Integration, Dec. 9-11, 2007, pp. 57-58 (plus cover page).
B. Aspar, et al., "Silicon Wafer Bonding Technology for VLSI and MEMS applications", edited by S. S. Iyer, et al., INSPEC, Chapter 3, ("Smart Cut : the technology used for high volume SOI wafer production"), 2002, pp. 35-52.
B. Holländer, et al., "Strain relaxation of pseudomorphic Si1-xGex/Si(100) heterostructures after hydrogen or helium ion implantation for virtual substrate fabrication", Nuclear Instruments and Methods in Physics Research B 175-177, (Elsevier), 2001, pp. 357-367.
Decision of Rejection issued Sep. 29, 2014 in Japanese Patent Application No. 2011-503408 (with English translation).
French preliminary Search Report issued Dec. 22, 2008, in Patent Application No. FR 0852302 (with English translation of Cited Documents).
L. J. Huang, et al., "SiGe-on insulator prepared by wafer bonding and layer transfer for high-performance field-effect transistors", Applied Physics Letters, vol. 78, No. 9, Feb. 26, 2001, pp. 1267-1269.
Office Action issued Dec. 3, 2013 in Japanese Patent Application No. 2011-503408 with English language translation.
R. T. Leonard, et al., "Photoassisted dry etching of GaN", Applied Physics. Lett., vol. 68, No. 6, Feb. 5, 1996, pp. 794-796.
S. J. Pearton, et al., "Low bias electron cyclotron resonance plasma etching of GaN, AlN, and InN", Applied Physics. Lett., vol. 64, No. 17, Apr. 25, 1994, pp. 2294-2296.
Shuji Nakamura, "InGaN/GaN/AlGaN-Based Laser Diodes with an Estimated Lifetime of Longer than 10,000 Hours", MRS Bulletin, vol. 23, No. 5, May 1998, pp. 37-43.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150194550A1 (en) * 2012-07-03 2015-07-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Detachment of a self-supporting layer of silicon <100>
US9698289B2 (en) * 2012-07-03 2017-07-04 Commissariat à l'Energie Atomique et aux Energies Alternatives Detachment of a self-supporting layer of silicon <100>

Also Published As

Publication number Publication date
FR2929758A1 (en) 2009-10-09
ATE542237T1 (en) 2012-02-15
FR2929758B1 (en) 2011-02-11
JP2011517103A (en) 2011-05-26
JP2015092632A (en) 2015-05-14
EP2263251B1 (en) 2012-01-18
WO2009124886A1 (en) 2009-10-15
EP2263251A1 (en) 2010-12-22
US20110104829A1 (en) 2011-05-05

Similar Documents

Publication Publication Date Title
JP7522555B2 (en) Method for transferring a thin layer to a supporting substrate having a different thermal expansion coefficient - Patents.com
US7960248B2 (en) Method for transfer of a thin layer
US7498245B2 (en) Embrittled substrate and method for making same
US7351644B2 (en) Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process
KR100491356B1 (en) Process of moving the thin film from the initial board to the final board
US20070029043A1 (en) Pre-made cleavable substrate method and structure of fabricating devices using one or more films provided by a layer transfer process
US8951809B2 (en) Method of transfer by means of a ferroelectric substrate
TWI598238B (en) Manufacturing a flexible structure by transfers of layers
CN111919290A (en) Process for transferring a piezoelectric layer onto a carrier substrate
JP2005505935A (en) Method for manufacturing a thin film layer containing microcomponents
US20230363279A1 (en) Use of an electric field for detaching a piezoelectric layer from a donor substrate
CN111341904A (en) Piezoelectric film, preparation method thereof and method for determining piezoelectric crystal axis direction
KR20050060111A (en) Method of detaching a thin film at moderate temperature after co­implantation
CN112768354B (en) Annealing method, composite film and electronic element
US7863156B2 (en) Method of producing a strained layer
TWI762755B (en) Detachable structure and detachment process using said structure
CN111527584B (en) Method for preparing remainder of donor substrate, substrate produced by the method and use thereof
JP2023519166A (en) Method for manufacturing laminated structure
CN113574654A (en) Method for transferring a useful layer to a carrier substrate

Legal Events

Date Code Title Description
AS Assignment

Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MOULET, JEAN-SEBASTIEN;DI CIOCCIO, LEA;MIGETTE, MARION;REEL/FRAME:025540/0907

Effective date: 20101102

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20190210