JP2007208031A - Wafer holder, and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wafer holder having a reference alignment mark which is observed from both surfaces, is not deformed even in thermal processing, and is repetitively used. <P>SOLUTION: The reference alignment mark of the wafer holder 210 is attached to a mark 141, where a transmission shape pattern 171 or a metallic pattern 161 is formed in a mark base material 151. Ceramic is used for a mark pattern in a mark base material 155, and a penetration mark pattern 165 is formed when the mark base material 155 is molded, or a silicon wafer is used in a mark base material 153 and a mark pattern 163 is formed with metal on a front surface, or a silicon membrane is used in a mark base material 157 and a penetration pattern 167 is formed by etching. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a stacked semiconductor device, and more particularly to a mark for alignment between wafers, which is suitable for a step of stacking and connecting wafers on which high-definition semiconductor devices are formed.

    In recent years, portable electronic devices such as mobile phones, notebook computers, portable audio devices, and digital cameras have made remarkable progress. Along with this, in addition to improving the performance of the chip itself as well as the performance of the chip itself, improvements in the chip mounting technology are also sought. There is a need for improved packaging technology.

  In order to reduce the chip mounting area, stacking chips is used to increase the amount of mounted chips without increasing the mounting area, thereby reducing the effective mounting area. For example, JP-A-2001-257307, 2002-050735, and JP-A-2000-349228 disclose such techniques. The first one is based on a wire bond system in which a chip and a chip or a chip and a mounting substrate are connected by a wire. The second one is based on a flip chip method in which a chip and a chip or a chip and a mounting substrate are connected via a micro bump provided on the back surface of the chip. In the third method, the chip and the chip or the chip and the mounting substrate are connected by using both the wire bond method and the flip chip method.

  In order to increase the driving speed of a semiconductor device, a method realized by reducing the thickness of the chip and using a through electrode is effective. For example, Japanese Patent Laid-Open No. 2000-208702 shows an example of mounting with a thickness of micron.

  In the wire bond method, a wire is stretched around the semiconductor bare chip. For this reason, a large occupied area larger than the occupied area of the semiconductor bare chip itself is required, and it takes time because the wires are stretched one by one. On the other hand, in the flip-chip method, since the connection is made by the micro bump formed on the back surface of the semiconductor bare chip, the area for connection is not particularly required, and the area necessary for mounting the semiconductor bare chip is the semiconductor bare chip. It can be almost equal to its own area. Further, since the connection surface can have all the bumps necessary for connection, connection to the wiring board can be performed in a lump. Therefore, the flip-chip method is the most suitable method for minimizing the occupation area necessary for mounting the semiconductor bare chip to achieve high-density mounting, reducing the size of the electronic device and shortening the construction period.

  In addition to the improvement of the chip-mounting substrate and the connection method between the chip and the chip, as a means of reducing the manufacturing cost, a rewiring layer or the like is formed before separating the wafer on which the semiconductor chip is formed into individual chips. Connection bumps are formed, and in some cases, sealing with resin is performed. A semiconductor device in which processing at the wafer level is effective is a semiconductor device having a high manufacturing yield and a small number of pins, and has many advantages particularly in the production of memory. (NIKKEI MICRODEVICE February 2000, page 56 and NIKKEI ELECTRONICS 2003.9.1 P.127).

  On the other hand, development of a manufacturing apparatus for manufacturing such a semiconductor device has also been earnestly performed. For example, the literature introduces an apparatus for aligning and bonding wafers to be bonded. (P. Lindner et al .: 2002 Electronic Component and Technology Conference P.1439). In addition, a similar technique is disclosed in Japanese Patent Laid-Open No. 9-148207.

By the way, when a stacked three-dimensional semiconductor device is manufactured by stacking at a wafer level, alignment of wafers to be stacked (a plurality of semiconductor devices on which a predetermined circuit pattern is formed) is necessary. However, the following methods are being studied for this purpose.
First, the wafer to be laminated is held on the wafer holder, and the positional relationship between the alignment mark on the wafer and the reference alignment mark on the holder is measured. Next, the wafers held in the respective holders face each other, and the reference alignment mark positions on the holders are measured. If the positional relationship between the respective wafers is obtained based on the obtained reference alignment mark positions on the two holders, the two wafers to be stacked can be aligned.

A more specific description will be given with reference to FIG. Reference is made to FIG. The first wafer 211 to be laminated is held in the first wafer holder 210, and the second wafer 213 is held in the second wafer holder 212 by, for example, an electrostatic chuck. Alignment marks 222 and 224 are formed on the wafer surface for both the first wafer and the second wafer, and reference alignment marks 231 and 233 are provided for both the first wafer holder and the second wafer holder. With respect to these wafers, the microscope 230 observes the alignment mark 222 on the wafer, the reference alignment mark 231 on the wafer holder, the alignment mark 224 and the reference alignment mark 233 on the holder. Since a plurality of alignment marks 222 and reference alignment marks 231 are arranged as shown in FIG. 3C, the wafer surface is measured while measuring the position coordinates of the wafer holder by a distance measuring system (for example, a laser interferometer) (not shown). By observing all the alignment marks 222 arranged above, the positions of the wafer 211 with respect to the reference alignment mark 231 and the wafer 213 with respect to the reference alignment mark 233 on the wafer holder are determined. Next, as shown in FIG. 3B, the wafer holder 212 is turned over to face the wafer holder 212. In this state, the microscope 230 obtains the positional relationship between the reference alignment mark 231 on the holder 210 and the reference alignment mark 233 on the holder 212. There are two methods for determining the positional relationship between the reference alignment marks 231 and 233. In the first method, the reference alignment mark 231 on the wafer holder 210 is observed with the microscope 230 to determine the coordinate value of the reference alignment mark 231 (for example, the coordinate in the coordinate system with the microscope as the origin), and then the inverted wafer holder 212. This is a method of determining the positional relationship between the two alignment marks by obtaining the coordinate value of the upper reference alignment mark 233. The second method is a method in which both the reference alignment marks 231 and the two wafer holders face each other. In this method, the positional relationship is determined by observing 233 simultaneously. When the positional relationship between the two reference alignment marks is determined, the positional relationship between the two wafers is determined based on the positional relationship between each wafer and the wafer holder. In either method, one reference alignment mark is observed from the opposite direction (back surface), not the direction observed when measuring the positional relationship between the wafer and the holder. For example, Patent Document 1 discloses a positional relationship measurement method in the wafer bonding process.
Japanese Patent Laid-Open No. 7-014982

  By the way, as described above, bump bonding is generally formed in flip chip electrode bonding, and bonding between the bump and the pad and between the bump and the bump is performed. For this joining, a low melting point metal sympathetic bonding method such as solder, a mechanical pressing method using shrinkage during curing of a nonconductive resin, an anisotropic conductive material in which conductive fine particles are dispersed. There are a method of bonding with conductive fine particles with a conductive resin interposed, and a method of metal diffusion bonding in which bump bumps are heated and pressed to diffuse the metal molecules of the bumps. A room temperature bonding method has been developed in which the surfaces to be bonded are cleaned and bonding is performed using the bonding force between metal molecules, but a method involving heat treatment is common and has been put to practical use.

  However, when the wafers held by the respective wafer holders are aligned and overlapped by the method as described above, and then an electrode bonding step involving heat treatment is performed, the reference alignment mark itself on the wafer holder itself is It has been found that the following problems occur. When making a wafer holder with a reference alignment mark, ceramics (or low thermal expansion glass) is used as the wafer holder material, and the mark base material on which the mark is formed is bonded to the opening of the wafer holder. At this time, if a low-expansion glass such as Zerodur is used as the mark base material and a Cr-plated one is used as a reference alignment mark, the Cr pattern is deformed by the heating process, and the mark cannot be used again. I have. Therefore, as a method of avoiding this, a method of forming a reference alignment mark by directly processing a pattern on a mark base material without using Cr can be considered. For example, it is a method of forming a concavo-convex pattern on the surface of a glass substrate by etching to form a reference alignment mark. However, the pattern contrast is low and the position measurement accuracy is not sufficient. In addition, when ceramic was used as the mark base material instead of glass, and it was formed by etching, irregularities were formed at the boundary of the pattern etched by pores (voids) inside the ceramic, and the position measurement accuracy was not sufficient.

  The present invention has been made in order to solve such problems, and is a wafer holder having a reference alignment mark, which can be observed from both sides, and is not deformed even when subjected to heat treatment. An object of the present invention is to provide a wafer holder which is a reference alignment mark that can be used repeatedly.

In order to solve the above problems, the present invention uses the following means.
The means of the present invention is a wafer holder,
A holder substrate;
A mark portion formed of a through hole formed on the substrate;
A reference alignment mark attached to the mark portion;
Have
The mark pattern of the reference alignment mark is
A penetration pattern formed by injection molding or machining using a ceramic material as a base material;
A metal pattern formed on the surface of a silicon wafer as a base material;
A through pattern formed by etching using a silicon membrane as a base material,
It is a wafer holder which is any one of the above.
According to this means of the present invention,
Even in the case of using ceramic, the mark pattern is formed by injection molding or machining, so the occurrence of pores on the mark surface when formed by etching is greatly reduced, and formation and observation of the mark pattern is achieved. Will not be adversely affected. Moreover, since it is a penetration mark, observation from both sides is easy.

  When a metal mark pattern formed on a silicon wafer is used, a metal whose melting point is much higher than the heating temperature in the subsequent heat treatment step is used as the metal forming the mark pattern. Suitable metals are Cu (copper) and Ti (titanium). When this silicon wafer is used as a base material, it is possible to observe the mark pattern from the commonly used infrared rays and easily observe the mark from both sides.

  With a mark in which a penetration pattern is formed using thin silicon as a base material, the penetration mark is easily formed by etching, the positional accuracy of the penetration pattern on both sides is high, and it is easy to observe from both sides. Become.

  The wafer holder having the reference alignment mark as described above in the mark portion is less likely to break the mark and there is no hindrance to the observation of the mark pattern. Make it possible without cost.

  In addition, if this holder is used for alignment when manufacturing a stacked type three-dimensional semiconductor device, there is no problem in optical observation, and it can withstand repeated heat treatments, thereby avoiding the consumption of alignment marks. .

  When the alignment process in the process of manufacturing the laminated semiconductor device using the wafer holder of the present invention is performed, the mark pattern can be observed optically better from both sides, and the heat resistance is high and it can withstand repeated use. As a result, the usage period during which the mark is consumed becomes longer, and the cost can be reduced.

  First, the reference alignment mark will be described with reference to FIG. FIG. 1 (a) shows a wafer holder 210, and a reference alignment mark is formed by forming a transmission shape pattern 171 or a metal pattern 161 on a mark base material 151 (see FIGS. 1 (b) and 1 (c)). 141. A plurality of the reference alignment marks are attached to the holder 210 as shown in FIG. The outer shape of the alignment mark substrate 151 (outer shape of the alignment mark) is not particularly defined, but a circular shape as shown in FIG. 1B or a rectangular shape as shown in FIG. . Incidentally, the wafer holder 210 having the reference alignment mark of the present invention has an electrostatic chuck electrode 291 for attracting the wafer, and in some cases, a heater 293 for heating the attracted wafer.

Here, a configuration example of the mark pattern will be described.
As a first configuration example of the mark pattern, as shown in FIG. 1E, ceramic is used for the mark base material 155, and a penetrating mark pattern 165 is formed at the time of forming the mark base material. Moreover, you may form a penetration pattern mechanically after shaping | molding. The thickness of the mark base material 155 is preferably 200 μm to 400 μm as an example from the viewpoint of strength, processing accuracy, and processability. In addition, the size and shape of the mark itself are designed taking into consideration the field of view of the microscope for observation, and the diameter (or one side of the square) is preferably about 16 mm when the inner diameter of the mark portion is taken into consideration as described above. . The relationship between the material of the holder 210 and the material of the mark base material 151 is preferably the one having substantially the same coefficient of thermal expansion. For example, the holder 210 is made of silicon carbide or aluminum nitride, and the same material is preferably used for the mark base material 155. . As a method of attaching the alignment mark base material 155 to the mark portion 141 of the holder, there are a method of bonding with an adhesive and a method of pressing with a mechanical force, for example, a leaf spring. FIG. 1 (g) shows a state in which the mark base material 155 is pressed and fixed to the wafer holder 210 by the leaf spring 181 fixed to the attachment portion 183.

  As a second configuration example of the mark pattern, a silicon wafer is used as the mark base material 153, and the mark pattern 163 is formed of metal on the surface as shown in FIG. The metal is preferably, for example, copper or titanium in consideration of the heating temperature in the subsequent heating step (about 400 ° C.) and the point of being observed with infrared rays through silicon. The thickness of the mark substrate 153 is preferably 700 μm to 500 μm from the viewpoints of ease of manufacture, mechanical strength, and infrared transmittance. The size and shape of the mark itself is designed taking into consideration the field of view of the microscope for observation, and the diameter (or one side of the square) is 16 mm when the inner diameter of the mark portion is 5 mm as in the previous embodiment. The degree is preferred. The relationship between the material of the holder 210 and the material of the mark base material 151 is preferably a material having substantially the same coefficient of thermal expansion. For example, the material of the holder 210 is preferably silicon carbide or aluminum nitride. As a method of attaching the alignment mark base material 153 to the mark portion 141 of the holder, there are a method of bonding with an adhesive and a method of pressing with a mechanical force, for example, a leaf spring. As shown in FIG. 1G, the mark base material 153 is pressed against the wafer holder 210 by the plate spring 181 fixed to the mounting portion 183.

  As a third configuration example of the mark pattern, as shown in FIG. 1F, a silicon membrane is used for the mark base material 157, and the through pattern 167 is formed by etching. This mark base material 157 is obtained by etching a part of a 700 μ-thick silicon wafer to form a silicon membrane. The thickness of the mark base material 157 is reduced from the viewpoint of mechanical strength of the membrane, ease of manufacture, and reduction of mark pattern errors. Is preferably 10 μ to 50 μ. The size and shape of the mark itself is designed taking into consideration the field of view of the microscope for observation, and the diameter (or one side of the square) is 16 mm when the inner diameter of the mark portion is 5 mm as in the previous embodiment. The degree is preferred. The relationship between the material of the holder 210 and the material of the mark base material 151 is preferably a material having substantially the same coefficient of thermal expansion. For example, the material of the holder 210 is preferably silicon carbide or aluminum nitride. As a method of attaching the alignment mark base material 157 to the mark portion 141 of the holder, there are a method of bonding with an adhesive and a method of pressing with a mechanical force, for example, a leaf spring. As shown in FIG. 1G, the mark base material 157 is pressed against the wafer holder 210 by the plate spring 181 fixed to the attachment portion 183.

Next, the requirements for the mark portion and the coping method of the present invention will be described.
The mark portion 141 takes the form of a through-hole penetrating the wafer holder 210, and the shape of the through-hole may be any of a cylindrical shape, a prismatic shape, or a conical shape. The specification required for this through-hole is that the observation light of the mark pattern 161 is not blocked. A description will be added with reference to FIG. The reference alignment mark has a mark pattern 161 that is observed from both sides by the objective lens 511. As shown in FIG. 2, when observing without passing through the mark portion 141 (in the figure, when the mark pattern 161 is observed from above with the lens system 511), the mark pattern 161 can be observed without any problem. I can do it. However, when observing via the mark part 141 (in the figure, when the mark pattern 161 is observed from below with the lens system 511), the lower end part 521 of the mark part 141 contributes to image formation depending on conditions. May block some. For example, if a part of the light beam 541 incident on the objective lens 513 indicated by the broken line is blocked by the lower end portion 521 of the mark portion 141, the mark pattern cannot be imaged with high resolution. In order to prevent this from happening, the radius R of the lower end 521 of the mark portion 141 needs to satisfy R> t · tan θ. Here, t is the thickness of the wafer holder 210, and θ is sin θ indicating the numerical aperture of the observation microscope. As an example, when the thickness of the wafer holder is 13 mm and the numerical aperture is 0.35, R = about 5 mm is preferable. Needless to say, if the mark portion 141 has a tapered surface as shown in FIG. 2B, the alignment mark substrate 151 can be stably held.

Next, a manufacturing method of a stacked three-dimensional semiconductor device that performs an alignment process using the wafer holder of the present invention will be described.
FIG. 4 is a flowchart showing a manufacturing method of a stacked three-dimensional semiconductor device to which the present invention is applied. The manufacturing method includes steps S1, S2, S3, S4 and S5. Each process will be briefly described.
S1: A wafer preparation step of preparing a predetermined number of wafers on which a plurality of semiconductor devices are formed,
Reference is made to FIG. A wafer 511 on which circuit elements 513 are formed by reducing and projecting a circuit pattern on a mask on a resist-coated wafer using a normal semiconductor exposure apparatus, developing the resist, and performing etching or thermal diffusion treatment of impurities. Get.
S2: Alignment process for measuring the positional relationship between the wafers to be laminated Since this process has already been described with reference to FIG. In some cases, the alignment may determine the positional relationship between the wafer and the already laminated wafer (wafer laminate). That is, one of the wafers may be in the form of a wafer stack formed by superimposing a plurality of wafers, possibly thinned by grinding or the like. The same applies to the subsequent steps.
S3: A wafer superimposing step of superimposing wafers whose positional relationship is measured,
When the wafer is held by the wafer holder (FIG. 5B) and the alignment of the two adjacent wafers is completed, the two wafers are superimposed as shown in FIG. . After the contact, in order to maintain the superimposed positional relationship, the holders are temporarily fixed (for example, a clamping mechanism) temporarily or temporarily fixed by an adhesive having a weak bonding force. The temporarily fixed holder and wafer laminated body 321 are transferred from the alignment / overlay execution unit 411 to the electrode bonding execution unit 413 by the robot arm 415. (FIG. 5 (d)).
S4: An electrode joining step for joining the connection electrodes on the superimposed wafers,
The aligned and temporarily fixed wafer stack is mounted with a pressure / heating device. The parallelism of the upper pressurizer 551, the lower pressurizer 553, and the wafer laminate 561 is adjusted, and when this is completed, the wafer laminate 561 is pressurized by the two pressurizers 551 and 553. At the same time, heating is performed by the heaters 541 and 543 incorporated in the holder according to the sequence determined. By applying a predetermined pressure for a predetermined time, the electrodes (metal bump and pad, metal bump and metal bump) on the wafer are bonded. At this time, in some cases, the resin may be sealed between the wafers and heated. (FIG. 5 (e)).

This alignment process, wafer overlay process, and electrode bonding process are repeated as many times as the number of wafers to be laminated. In some cases, a sealing resin may be encapsulated between the laminated wafers or a process of thinning the laminated wafers by grinding, polishing, or etching after lamination bonding.
S5: A dicing process for separating individual semiconductor devices from a predetermined number of stacked wafers. Wafers stacked and bonded at the wafer level are cut according to a dicing line and separated as chips. For example, cutting is performed according to the broken line in FIG. In general, a dicing saw method in which cutting is performed using a dicing blade, a method in which the wafer surface is melted and split by a laser beam, and a method in which a cutting line is drawn by a diamond cutter are used. However, a dicing saw method is preferable as a method for separating the wafer stack into chips.

  When alignment between wafers is performed using a wafer holder having the alignment mark of the present invention as a reference alignment mark in the alignment step of the manufacturing method of the stacked semiconductor device, the reference alignment mark is not deteriorated and optically observed. Sometimes a good image is observed without any obstacles such as scattering. Accordingly, there is no extra cost, a highly accurate alignment accuracy is obtained, and a manufacturing method that can prevent a decrease in manufacturing yield is obtained.

  The high density of the elements and the high speed driving of the elements by the stacked three-dimensional semiconductor device are inevitable trends in accordance with the progress of portable devices. The present invention is a technique for manufacturing this semiconductor device at a low cost and a high yield, and has a great potential for industrial use.

The appearance of the mark of the present invention and the positional relationship with the holder are shown. The state in the case of observing the alignment mark of this invention from both surfaces is shown. A method for aligning wafers using the wafer holder of the present invention will be described. ~ An example of a method for manufacturing a stacked three-dimensional semiconductor device using the wafer holder of the present invention will be described.

Explanation of symbols

151, 153, 155, 157... Mark base material 161, 163, 165, 167,... Mark pattern 211, 213, 511, wafers 210, 212, 521 to be stacked wafer holders 222, 224, 523 ... Alignment marks 231, 233, 525 on wafer ... Reference alignment mark 230 ... Microscope 561 ... Wafer stacks 541, 543 ... Heaters 551, 553 ... Pressurizer

Claims (4)

A wafer holder,
A holder substrate;
A mark portion formed of a through hole formed on the substrate;
A reference alignment mark attached to the mark portion;
Have
The mark pattern of the reference alignment mark is
A penetration pattern formed by injection molding or machining using a ceramic material as a base material;
A metal pattern formed on the surface of a silicon wafer as a base material;
A through pattern formed by etching using a silicon membrane as a base material,
Either
A wafer holder characterized by that. The wafer holder according to claim 1, wherein the metal is copper or titanium. A wafer holder according to claim 1 or 2,
The size of the through hole does not block the light beam for observing the reference alignment mark.
A wafer holder characterized by that. A method of manufacturing a three-dimensional semiconductor device by laminating wafers on which a plurality of semiconductor devices are formed,
Preparing a predetermined number of wafers on which a plurality of semiconductor devices are formed, a wafer preparation step,
An alignment process for measuring the positional relationship between wafers to be laminated,
A wafer superposition process, which superimposes wafers whose positional relationship has been measured,
An electrode joining process for joining the connection electrodes on the stacked wafers;
A dicing process for separating individual semiconductor devices from a predetermined number of stacked wafers;
A method for manufacturing a stacked three-dimensional semiconductor device, wherein the wafer holder according to claim 1 or 3 is used in the alignment step.

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