US8947152B2 - Multi-chip package - Google Patents

Multi-chip package Download PDF

Info

Publication number
US8947152B2
US8947152B2 US14/038,363 US201314038363A US8947152B2 US 8947152 B2 US8947152 B2 US 8947152B2 US 201314038363 A US201314038363 A US 201314038363A US 8947152 B2 US8947152 B2 US 8947152B2
Authority
US
United States
Prior art keywords
slice
chip
signal
chip package
activation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US14/038,363
Other languages
English (en)
Other versions
US20140306748A1 (en
Inventor
Jae-Bum Ko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
SK Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SK Hynix Inc filed Critical SK Hynix Inc
Assigned to SK Hynix Inc. reassignment SK Hynix Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KO, JAE-BUM
Publication of US20140306748A1 publication Critical patent/US20140306748A1/en
Application granted granted Critical
Publication of US8947152B2 publication Critical patent/US8947152B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a multi-chip package.
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • the multi-chip package represents one chip having a plurality of semiconductor chips.
  • the multi-chip package increases a memory capacity using a plurality of memory chips or improves a performance using a semiconductor chip having different functions.
  • the multi-chip package is classified to a single-layered multi-chip package and a multi-layered multi-chip package.
  • the single-layered multi-chip package represents that a plurality of semiconductor chips are laterally arrayed on a plane.
  • the multi-layered multi-chip package represents that a plurality of semiconductor chips are stacked.
  • FIG. 1 shows a diagram illustrating a conventional multi die package.
  • the conventional multi die package 100 includes a plurality of semiconductor chips CP_ 1 to CP_N and a substrate 110 .
  • the plurality of semiconductor chips CP_ 1 to CP_N are vertically stacked.
  • Each of the plurality of semiconductor chips CP_ 1 to CP_N is coupled to the substrate 110 .
  • a pad of each of the plurality of semiconductor chips CP_ 1 to CP_N is arrayed on an edge of each of the plurality of semiconductor chips CP_ 1 to CP_N.
  • the substrate 110 is electrically coupled to the pad of each of the plurality of semiconductor chips CP_ 1 to CP_N using a Tire.
  • the interconnection is arrayed along an edge of the plurality of semiconductor chips CP_ 1 to CP_N, an area of the plurality of semiconductor chips CP_ 1 to CP_N may be increased, and an interposer layer may be requested to be arrayed between the plurality of semiconductor chips CP_ 1 to CP_N.
  • the multi die package may have merits than the single-layered multi-chip package, it may have demerits in view of a footprint because a form factor is increased.
  • a gold wire is arrayed between pads to improve a quality of a signal transferred through a wire
  • a transfer speed of data is lowered and a skew of a signal may occur in stacked dies.
  • this concern may cause a power over-consumption and lower the reliability of a signal.
  • Exemplary embodiments of the present invention are directed to a multi-chip package having a through-silicon-via (TSV).
  • TSV through-silicon-via
  • exemplary embodiments of the present invention are directed to a multi-chip package for performing various operations according to an activation mode without adding a through-silicon-via (TSV).
  • TSV through-silicon-via
  • a multi-chip package having a plurality of slice chips coupled through a through-via at least one slice chip may include an input unit suitable for receiving a slice activation signal, and outputting the slice activation signal to the through-via in response to a slice identification corresponding to the slice chip, a first output unit suitable for outputting the activation signal transferred through the through-via to an internal circuit of the slice chip in response to the corresponding slice identification, and a second output unit suitable for selectively outputting the activation signal transferred through the through-via to the internal circuit of the slice chip in a predetermined activation mode for the multi-chip package.
  • a multi-chip package system may include a multi-chip package having a plurality of slice chips coupled each other by using a first through-via and a second through-via, wherein at least one slice chip includes, a first signal transfer unit, and a second signal transfer unit, wherein the first signal transfer unit is suitable for transferring a first slice activation signal to the first through-via and an internal circuit of the slice chip, and the second signal transfer unit is suitable for transferring a second slice activation signal to the second through-via and the internal circuit of the slice chip, and a controller suitable for providing the first slice activation signal to the multi-chip package or the first and the second slice activation signals to the multi-chip package, and controlling a predetermined activation mode for the multi-chip package.
  • a multi-chip package having a plurality of slice chips coupled through a through-via at least one slice chip may include a first signal transfer unit having a first output unit and a second output unit, wherein the second output unit is suitable for outputting a first slice activation signal transferred through a first through-via to an internal circuit of the slice chip in a predetermined activation mode for the multi-chip package, and a second signal transfer unit suitable for outputting a predetermined signal transferred through a second through-via to the internal circuit of the slice chip, wherein the second signal transfer unit includes an output unit suitable for outputting the predetermined signal to the internal circuit, and a dummy output unit connected to the second through-via.
  • FIG. 1 is a diagram illustrating a conventional multi die package.
  • FIG. 2 is a diagram illustrating a multi-chip package using a through-silicon-via (TSV) in accordance with an embodiment of the present invention.
  • TSV through-silicon-via
  • FIG. 3 is a diagram illustrating a multi-chip package in accordance with an embodiment of the present invention.
  • FIG. 4 is a diagram illustrating a multi-chip package in accordance with another embodiment of the present invention.
  • FIG. 5 is a block diagram illustrating a multi-chip package system using a multi-chip package in accordance with an embodiment of the present invention.
  • FIG. 2 is diagram illustrating a multi-chip package using a through-silicon-via (TSV) in accordance with an embodiment of the present invention.
  • TSV through-silicon-via
  • a multi-chip package 200 includes a plurality of semiconductor chips CP_ 1 to CP_N and a substrate 210 .
  • the plurality of semiconductor chips CP_ 1 to CP_N are vertically stacked and electrically coupled through the TSV.
  • the plurality of semiconductor chips CP_ 1 to CP_N includes a master chip CP_ 1 and a plurality of slave chips CP_ 2 to CP_N.
  • the master chip CP_ 1 is coupled to the substrate 210 , and controls the plurality of slave chips CP_ 2 to CP_N using signals transferred through the substrate 210 .
  • a structure of a multi-chip package using the TSV may be useful for a high speed operation and a low power consumption. Also, a structure of a multi-chip package using the TSV may be minimized in size, compared to a structure of a multi-chip package using a wire, because an interconnection distance between a plurality of semiconductor chips is reduced.
  • a plurality of semiconductor chips CP_ 1 to CP_N are referred to as ‘a plurality of slice chips’. That is, the multi-chip package 200 includes a plurality of slice chips CP_ 1 to CP_N, which are coupled to each other through the TSV.
  • a multi-chip package in accordance with an embodiment of the present invention may select and activate one of a plurality of slice chips without adding a TSV.
  • a plurality of slice chips are activated in response to a clock enable signal.
  • the clock enable signal is a signal for controlling an activation state of a clock signal provided to a corresponding slice chip.
  • the clock enable signal is a signal that is most early activated for an operation of the corresponding slice chip. That is, each of the plurality of slice chips is activated when the clock enable signal is input.
  • FIG. 3 is a diagram illustrating a multi-chip package in accordance with an embodiment of the present invention. For the convenience of the descriptions, it is assumed that four slice chips 310 to 340 are selectively activated in response to a first clock enable signal CKE 1 and a second clock enable signal CKE 2 .
  • a multi-chip package 300 includes a first slice chip 310 , a second slice chip 320 , a third slice chip 330 and a fourth slice chip 340 .
  • the first to fourth slice chips 310 to 340 are coupled to each other through a first TSV TSV 1 and a second TSV TSV 2 .
  • the first TSV TSV 1 is used for transferring the first clock enable signal CKE 1 .
  • the second TSV TSV 2 is used for transferring the second clock enable signal CKE 2 .
  • first slice chip 310 and the third slice chip 330 are arrayed on an odd number layer
  • second slice chip 320 and the fourth slice chip 340 are arrayed on an even number layer.
  • the first slice chip 310 includes a first signal transfer unit 311 , a second signal transfer unit 312 , and a slice identification generation unit 313 .
  • the first signal transfer unit 311 transfers the first clock enable signal CKE 1 to the first TSV TSV 1 and an internal circuit (not shown) of the first slice chip 310 .
  • the first signal transfer unit 311 includes a first input unit 311 A, a first output unit 311 B, and a second output unit 311 C.
  • the first input unit 311 A outputs the first clock enable signal CKE 1 to the first TSV TSV 1 in response to a selection control signal EN_SL.
  • the first output unit 311 B outputs a signal transferred through the first TSV TSV 1 to the internal circuit (not shown) of the first slice chip 310 in response to an odd control signal OD.
  • the second output unit 311 C outputs a signal transferred through the first TSV TSV 1 to the internal circuit (not shown) of the first slice chip 310 in response to an activation mode signal MD.
  • the activation mode signal MD is a signal corresponding to an activation operation of the first to the fourth slice chips 310 to 340 , and includes a 3-dimension structure (3DS) mode and a quad die package (QDP) mode.
  • the 3DS mode represents that the first to the fourth slice chips 310 to 340 are activated in response to the first clock enable signal CKE 1 .
  • the QDP mode represents that the first and third slice chips 310 and 330 and the second and the fourth slice chips 320 and 340 are separately activated in response to the first clock enable signal CKE 1 and the second clock enable signal CKE 2 .
  • the second signal transfer unit 312 transfers the second clock enable signal CKE 2 to the second TSV TSV 2 and the internal circuit (not shown) of the first slice chip 310 .
  • the second signal transfer unit 312 includes an input unit 312 A and an output unit 312 B.
  • the input unit 312 A outputs the second dock enable signal CKE 2 to the second TSV TSV 2 in response to the selection control signal EN_SL.
  • the output unit 312 B outputs a signal transferred through the second TSV TSV 2 to the internal circuit (not shown) of the first slice chip 310 in response to an even control signal EV.
  • the slice identification generation unit 313 controls the signal transmission of the first signal transfer unit 311 and the second signal transfer unit 312 .
  • the slice identification generation unit 313 generates the odd control signal OD, the even control signal EV and the selection control signal EN_SL according to a stacked sequence of the first to the fourth slice chips 310 to 340 . That is, the slice identification generation unit 313 allocates the identification corresponding to a first layer to the first slice chip 310 .
  • a slice identification generation unit (not shown) of the second slice chip 320 allocates the identification corresponding to a second layer to the second slice chip 320 .
  • a slice identification generation unit (not shown) of the third slice chip 330 allocates the identification corresponding to a third layer to the third slice chip 330 .
  • a slice identification generation unit (not shown) of the fourth slice chip 340 allocates the identification corresponding to a fourth layer to the fourth slice chip 340 .
  • the first slice chip 310 receives the identification corresponding to the first layer.
  • the odd control signal ODD corresponding to an odd layer is activated.
  • the even control signal EV corresponding to an even layer is inactivated.
  • the second slice chip 320 receives the identification corresponding to the second layer.
  • the even control signal EV corresponding to the even layer is activated.
  • the odd control signal OD corresponding to the odd layer is inactivated.
  • the selection control signal EN_SL is activated in, for example, only the identification corresponding to the first layer and is not activated in the other identification corresponding to the other layers.
  • the multi-chip package 300 receives the first clock enable signal CKE 1 and the second clock enable signal CKE 2 , and controls an activation operation of the first and the third slice chips 310 and 330 and the second and the fourth slice chips 320 and 340 , respectively.
  • the multi-chip package 300 receives, for example, only the first clock enable signal CKE 1 and controls an activation operation of the first to the fourth slice chips 310 to 340 .
  • the odd control signal OD of the slice chip arrayed on the first layer is activated, and the selection control signal EV is inactivated.
  • the even control signal EV of the slice chip arrayed on the even layer is activated and the odd control signal OD is inactivated.
  • the multi-chip package 300 receives the first dock enable signal CKE 1 and the second dock enable signal CKE 2 .
  • the first dock enable signal CKE 1 is input to the first input unit 311 A of the first slice chip 310 , and is transferred to the first TSV TSV 1 . Then, the first clock enable signal CKE 1 is transferred to an internal circuit (not shown) of the first slice chip 310 through the first output unit 311 B in response to an activated odd control signal OD. The first slice chip 310 is activated in response to the first clock enable signal CKE 1 transferred through the first output unit 311 B.
  • the second clock enable signal CKE 2 is input to the input unit 312 A of the first slice chip 310 , and is transferred to the second TSV TSV 2 . But, since the even control signal EV is not activated, the second clock enable signal CKE 2 is not transferred to an internal circuit (not shown) of the first slice chip 310 through the output unit 312 B.
  • the second slice chip 320 arrayed on the even layer is operated contrary to the first slice chip 310 . That is, the second clock enable signal CKE 2 transferred through the second TSV TSV 2 is transferred to the internal circuit (not shown) of the second slice chip 320 through the first output unit 321 B. The first clock enable signal CKE 1 transferred through the first TSV TSV 1 is not transferred to the internal circuit (not shown) of the second slice chip 320 .
  • first and the third slice chips 310 and 330 are activated in response to the first clock enable signal CKE 1 .
  • the second and the fourth slice chips 320 and 340 are activated in response to the second clock enable signal CKE 2 .
  • an activation mode signal MD is inactivated.
  • the first clock enable signal CKE 1 transferred through the first TSV TSV 1 is not transferred to the internal circuit (not shown) through the second output unit 311 C, 321 C, 331 C and 341 C of each of the first to the fourth slice chips 310 to 340 .
  • the activation mode MD is activated and, for example, only the first clock enable signal CKE 1 is received.
  • the first clock enable signal CKE 1 is input to the first input unit 311 A of the first slice chip 310 , and is transferred to the first TSV TSV 1 . Then, the first clock enable signal CKE 1 is transferred to the internal circuit (not shown) of the first slice chip 310 through the first output unit 311 B in response to an activated odd control signal OD. The first slice chip 310 is activated in response to the first clock enable signal CKE 1 transferred through the first output unit 311 B.
  • the second slice chip 320 arrayed on the even layer receives the first clock enable signal CKE 1 transferred through the first TSV TSV 1 .
  • the first clock enable signal CKE 1 is transferred to the internal circuit (not shown) of the second slice chip 320 through the second output unit 321 C in response to an activated activation mode signal MD.
  • the second slice chip is activated in response to the first clock enable signal CKE 1 .
  • the first clock enable signal CKE 1 controls an activation operation of the first to the fourth slice chips 310 to 340 .
  • the multi-chip package in accordance with an embodiment of the present invention may perform compatibility of the 3DS mode for receiving, for example, only the first clock enable signal CKE 1 and the QDP mode for receiving the first and the second enable signals CKE 1 and the CKE 2 .
  • FIG. 4 is a diagram illustrating a multi-chip package in accordance with another embodiment of the present invention. For the convenience of the descriptions, a fourth slice chip 410 among a plurality of slice chips is shown in FIG. 4 .
  • the fourth slice chip 410 includes a first signal transfer unit 411 and a second signal transfer unit 412 .
  • the first signal transfer unit 411 transfers a first clock enable signal CKE 1 an internal circuit (not shown) of the fourth slice chip 410 in response to an activation mode signal MD.
  • the first signal transfer unit 411 includes a first input unit 411 A, a first output unit 411 B and a second output unit 411 C. Since the first input unit 411 A, the first output unit 411 B and the second output unit 411 C shown in FIG. 4 are same as the first input unit 311 A, the first output unit 311 B and the second output unit 311 C shown in FIG. 3 , the detailed descriptions of the first input unit 411 A, the first output unit 411 B and the second output unit 411 C will be omitted.
  • the second signal transfer unit 412 transfers the second clock enable signal CKE 2 to an internal circuit (not shown) of the fourth slice chip 410 .
  • the second signal transfer unit 412 includes an input unit 412 A, an output unit 412 B and a dummy output unit 412 C.
  • the input unit 412 A and the output unit 412 B are used for transferring the second clock enable signal CKE 2 .
  • the dummy output unit 412 C is used in a same loading of the first clock enable signal CKE 1 transferred to the first signal transfer unit 411 and the second clock enable signal CKE 2 transferred to the second signal transfer unit 412 .
  • the multi-chip package in accordance with an embodiment of the present invention may reduce a skew difference between the first clock enable CKE 1 and the second dock enable CKE 2 by further having the dummy output unit 412 C on a transfer path of the second signal transfer unit 412 , and matching a loading of the first signal transfer unit 411 and the second signal transfer unit 412 .
  • the dummy output unit 412 is installed on a transfer path of the second clock enable signal CKE 2 in the embodiment of the present invention shown in FIG. 4
  • the dummy output unit 412 may be installed on a transfer path of other signals or other command signals except the second dock enable signal CKE 2 , in the multi-chip package in accordance with the embodiment of the present invention.
  • FIG. 5 is a block diagram illustrating a multi-chip package system using a multi-chip package in accordance with an embodiment of the present invention.
  • a multi-chip package system 500 includes a controller 510 and a multi-chip package 520 .
  • the controller 510 generates and provides an activation mode signal MD, a first clock enable signal CKE 1 and a second clock enable signal CKE 2 to the multi-chip package 520 .
  • the multi-chip package 520 receives the activation mode signal MD, the first clock enable signal CKE 1 and the second clock enable signal CKE 2 , and performs an activation operation of a plurality of slice chips according to a 3DS mode or a QDP mode.
  • the multi-chip package system in accordance with an embodiment of the present invention may select a QDP mode or a 3DS mode using a controller.
  • a multi-chip package in accordance with an embodiment of the present invention may minimize a TSV, and perform a QDP mode or a 3DS mode according to an activation mode.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
US14/038,363 2013-04-11 2013-09-26 Multi-chip package Active US8947152B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020130040054A KR101996474B1 (ko) 2013-04-11 2013-04-11 멀티 칩 패키지
KR10-2013-0040054 2013-04-11

Publications (2)

Publication Number Publication Date
US20140306748A1 US20140306748A1 (en) 2014-10-16
US8947152B2 true US8947152B2 (en) 2015-02-03

Family

ID=51686380

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/038,363 Active US8947152B2 (en) 2013-04-11 2013-09-26 Multi-chip package

Country Status (2)

Country Link
US (1) US8947152B2 (ko)
KR (1) KR101996474B1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111354718B (zh) * 2020-03-23 2022-02-25 江苏中科智芯集成科技有限公司 含多芯片封装结构的芯片排列布线方法、装置及电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4661979A (en) * 1985-09-24 1987-04-28 Northern Telecom Limited Fault protection for integrated subscriber line interface circuits
US20040239400A1 (en) * 2003-05-27 2004-12-02 Infineon Technologies Ag Integrated circuit and method for operating the integrated circuit
US20110128072A1 (en) 2009-11-30 2011-06-02 Hynix Semiconductor Inc. Repair circuit and semiconductor apparatus including the same
US20110267137A1 (en) * 2010-04-30 2011-11-03 Hynix Semiconductor Inc. Semiconductor apparatus
US8686777B1 (en) * 2013-01-03 2014-04-01 Texas Instruments Incorporated Methods and circuits for enabling slew rate programmability and compensation of input/output circuits

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100871381B1 (ko) * 2007-06-20 2008-12-02 주식회사 하이닉스반도체 관통 실리콘 비아 칩 스택 패키지
KR20110072549A (ko) * 2009-12-23 2011-06-29 주식회사 하이닉스반도체 반도체 장치
KR20110107626A (ko) * 2010-03-25 2011-10-04 엘에스산전 주식회사 슬레이브 장치 및 그 아이디 할당 방법
KR101145312B1 (ko) * 2010-07-06 2012-05-14 에스케이하이닉스 주식회사 반도체 집적회로
KR101124251B1 (ko) * 2010-07-07 2012-03-27 주식회사 하이닉스반도체 적층된 칩들에 아이디를 부여하는 시스템, 반도체 장치 및 그 방법
KR20120121426A (ko) * 2011-04-25 2012-11-06 에스케이하이닉스 주식회사 반도체 집적회로
KR101857677B1 (ko) * 2011-07-21 2018-05-14 에스케이하이닉스 주식회사 반도체 집적회로 및 그의 신호 전달 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4661979A (en) * 1985-09-24 1987-04-28 Northern Telecom Limited Fault protection for integrated subscriber line interface circuits
US20040239400A1 (en) * 2003-05-27 2004-12-02 Infineon Technologies Ag Integrated circuit and method for operating the integrated circuit
US20110128072A1 (en) 2009-11-30 2011-06-02 Hynix Semiconductor Inc. Repair circuit and semiconductor apparatus including the same
US20110267137A1 (en) * 2010-04-30 2011-11-03 Hynix Semiconductor Inc. Semiconductor apparatus
US8686777B1 (en) * 2013-01-03 2014-04-01 Texas Instruments Incorporated Methods and circuits for enabling slew rate programmability and compensation of input/output circuits

Also Published As

Publication number Publication date
KR101996474B1 (ko) 2019-07-05
US20140306748A1 (en) 2014-10-16
KR20140122948A (ko) 2014-10-21

Similar Documents

Publication Publication Date Title
US8760181B2 (en) Semiconductor system and device for identifying stacked chips and method thereof
US8837191B2 (en) Semiconductor apparatus
US9336857B2 (en) Semiconductor memory device including stacked memory chips
US20120051113A1 (en) Semiconductor integrated circuit
TW201926612A (zh) 具有一控制器及一記憶體堆疊之彈性記憶體系統
US20190363049A1 (en) Multiple die package using an embedded bridge connecting dies
US11600308B2 (en) Semiconductor memory device, processing system including the same and power control circuit for the same
US10050017B2 (en) Semiconductor apparatus and semiconductor system including the same
US9275984B2 (en) Multi-chip package system
US8947152B2 (en) Multi-chip package
US9959184B2 (en) Input/output (I/O) line test device and method for controlling the same
US9466555B2 (en) Semiconductor chip and stack type semiconductor apparatus using the same
US9600424B2 (en) Semiconductor chips, semiconductor chip packages including the same, and semiconductor systems including the same
US8923081B2 (en) Semiconductor memory system and operating method thereof
US20140175439A1 (en) Semiconductor integrated circuit and multi-chip package including the same
US20170200507A1 (en) Memory system including memory device
US9613716B2 (en) Semiconductor device and semiconductor system including the same
US10340255B2 (en) Semiconductor apparatus and semiconductor system including the same
US10256799B2 (en) Semiconductor apparatus and system including plurality of channels
US9202802B2 (en) Semiconductor apparatus having through via capable of testing connectivity of through via
US9183918B2 (en) Stacked semiconductor apparatus for generating refresh signal
US20140353664A1 (en) Semiconductor chip, semiconductor apparatus having the same and method of arranging the same
KR101923727B1 (ko) 적층형 반도체 모듈
US20160097812A1 (en) Semiconductor package
US9269414B2 (en) Semiconductor integrated circuit

Legal Events

Date Code Title Description
AS Assignment

Owner name: SK HYNIX INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KO, JAE-BUM;REEL/FRAME:031292/0398

Effective date: 20130909

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551)

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8