US8786531B2 - Pixel circuit and display device - Google Patents

Pixel circuit and display device Download PDF

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US8786531B2
US8786531B2 US13/635,740 US201013635740A US8786531B2 US 8786531 B2 US8786531 B2 US 8786531B2 US 201013635740 A US201013635740 A US 201013635740A US 8786531 B2 US8786531 B2 US 8786531B2
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voltage
pixel
control
row
transistor
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US20130010015A1 (en
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Yoshimitsu Yamauchi
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Sharp Corp
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Sharp Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/10—Special adaptations of display systems for operation with variable images
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/022—Power management, e.g. power saving in absence of operation, e.g. no data being entered during a predetermined time
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3618—Control of matrices with row and column drivers with automatic refresh of the display panel using sense/write circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

Definitions

  • the present invention relates to a pixel circuit and a display device including the pixel circuit and, more particularly, relates to an active matrix liquid crystal display device.
  • FIG. 14 illustrates an equivalent circuit of a pixel circuit of a common active matrix liquid crystal display device.
  • FIG. 15 illustrates an example of a circuit arrangement in an active matrix liquid display device of m ⁇ n pixels.
  • a switching element formed with a thin film transistor (TFT) is provided at each intersection of m source lines (data signal lines) and n scanning lines (scan signal lines) and, as illustrated in FIG. 14 , a liquid crystal element LC and a retentive capacity Cs are connected in parallel through the TFT.
  • the liquid crystal element LC adopts a layered structure in which a liquid crystal layer is provided between a pixel electrode and a counter electrode (common electrode).
  • the retentive capacity Cs provides an effect of suppressing fluctuation of the pixel data voltage held in the pixel electrode due to a leak current of a TFT, fluctuation of an electrical capacitance of the liquid crystal element LC between black display and white display due to dielectric anisotropy of liquid crystal particles, and voltage fluctuation caused by parasitic capacitance between the pixel electrode and a surrounding wiring.
  • Power consumption for driving a liquid crystal display device is mostly occupied by power consumption for driving source lines by a source driver, and can be roughly expressed by a relational expression shown in following equation 1.
  • P represents power consumption
  • f represents a refresh rate (the number of times of refresh operations in one frame per unit time)
  • C represents a load capacitance driven by a source driver
  • V represents a driving voltage of the source driver
  • n represents the number of scanning lines
  • m represents the number of source lines.
  • the refresh operation is directed to canceling fluctuation produced in a voltage (absolute value) corresponding to pixel data applied to the liquid crystal element LC by writing the pixel data again, and returning the voltage to the original voltage state corresponding to the pixel data.
  • Patent Documents 1 and 2 disclose configurations as a method of solving a problem that display quality decreases due to a decrease in the refresh frequency upon constant display of a still image. According to the configurations disclosed in Patent Documents 1 and 2, a switching element of a pixel circuit illustrated in FIG.
  • TFT 14 is formed with a series circuit of two TFTs (transistors T 1 and T 2 ), an intermediate node N 2 between the two TFTs is driven to have the same potential as a pixel electrode N 1 using a buffer amplifier 50 of a unity gain, and a problem that display quality decreases is solved by substantially suppressing the leak current of the TFT by preventing the voltage from being applied between a source and a drain of the TFT (T 2 ) arranged on a pixel electrode side (see FIGS. 16 and 17 ).
  • Patent Document 1 Japanese Patent Application Laid-Open Publication No. 5-142573
  • Patent Document 2 Japanese Patent Application Laid-Open Publication No. 10-62817
  • the threshold voltage is closer to 0 V, power consumption becomes higher, thereby contradicting with a request for lower power consumption.
  • the buffer amplifier of the unity gain is formed using an operational amplifier, not only a circuit scale increases, thereby contradicting with a request for lower power consumption, but also the ratio a circuit element area occupies in a pixel circuit is high, an aperture ratio in a transmissive mode decreases and brightness of a display image decreases.
  • the present invention provides a pixel circuit having; a display element unit having a unit liquid crystal display element; an internal node forming part of the display element unit and holding a pixel data voltage applied to the display element unit; a first switch circuit having a series circuit of first and second transistor elements, one end connected with a data signal line, and the other end connected with the internal node, and transferring to the internal node the pixel data voltage supplied from the data signal line through the series circuit; a second switch circuit having a third transistor element, one end connected with a predetermined voltage supply line, and the other end connected with an intermediate node which is a connection point where the first and second transistor elements in the series circuit are connected in series; and a control circuit formed with a series circuit of a fourth transistor element and a first capacitative element, holding the pixel data voltage held in the internal node, at one end of the first capacitative element through the fourth transistor element, and controlling conduction of the third transistor element by a boost voltage applied to the other end of the first
  • each of the first to fourth transistor elements has a first terminal, a second terminal, and a control terminal that controls conduction between the first and second terminals
  • the control terminal of the first transistor element is connected with a first scan signal line setting the first transistor element to a conducted state upon an operation of transferring the pixel data voltage to the internal node
  • the control terminal of the second transistor element is connected with a second scan signal line setting the second transistor element to a conducted state upon an operation of transferring the pixel data voltage to the internal node
  • the control terminal of the third transistor element, the second terminal of the fourth transistor element and the one end of the first capacitative element are connected to each other, and form an output node of the control circuit
  • the first terminal of the fourth transistor element is connected with the internal node
  • the control terminal of the fourth transistor element is connected with a first control line
  • the other end of the first capacitative element is connected with a second control line supplying the boost voltage
  • a first control voltage equal to or more than a maximum voltage of the pixel data voltage held in the internal node is applied to the voltage supply line, a voltage setting the first transistor element to a non-conducted state is applied to the first scanning line, and a voltage setting the second transistor element to a conducted state is applied to the second scanning line, and, in a state where the internal node and the output node have the same potential through the fourth transistor element, the fourth transistor element transitions from a conducted state to a non-conducted state, and thereafter the boost voltage is applied to the other end of the first capacitative element, thereby boosting the voltage of the output node to a second control voltage obtained by adding a threshold voltage of the third transistor element to the pixel data voltage held in the internal node.
  • the pixel circuit having the above features is preferably configured such that, the first switch circuit consists of the series circuit of the first and second transistor elements, and the first terminal of the first transistor element is connected with the data signal line, the second terminal of the first transistor element and the first terminal of the second transistor element are connected with the intermediate node, and the second terminal of the second transistor element is connected with the internal node, and further, the second switch circuit consists of the third transistor element, and the first terminal of the third transistor element is connected with the voltage supply line, and the second terminal of the third transistor element is connected with the intermediate node.
  • the pixel circuit having the above features preferably further has a second capacitative element having one end connected to the internal node and the other end connected to a third control line or the voltage supply line.
  • the present invention provides a display device having a first feature that
  • a plurality of pixel circuits having the above described features are arranged in a row direction and a column direction to form a pixel circuit array
  • the data signal line is provided for each of columns, the scan signal line is provided for each of rows, the one ends of the first switch circuits in the pixel circuits arranged in the same column are connected to the common data signal line, the control terminals of the first transistor elements in the pixel circuits arranged in the same row are connected to the common first scan signal line, and the control terminals of the second transistor elements in the pixel circuits arranged in the same row are connected to the common second scan signal line, the one ends of the second switch circuits in the pixel circuits arranged in the same row or the same column are connected to the common voltage supply line, the control terminals of the fourth transistor elements in the pixel circuits arranged in the same row or the same column are connected to the common first control line, the other ends of the first capacitative elements in the pixel circuits arranged in the same row or the same column are connected to the common second control line, and
  • the display device has a data signal line drive circuit individually driving the data signal lines, a scan signal line drive circuit individually driving the first scan signal lines and individually or commonly driving the second scan signal lines, a voltage supply line drive circuit individually or commonly driving the voltage supply lines, and a control line drive circuit individually or commonly driving the first control lines and individually or commonly driving the second control lines.
  • the display device having the first feature is preferably configured such that, in the pixel circuits arranged in the same row, the one ends of the second switch circuits are connected to the common voltage supply line; in the pixel circuits arranged in the same row, the control terminals of the fourth transistor elements are connected to the common first control line, and in the pixel circuits arranged in the same row, the other ends of the first capacitative elements are connected to the common second control line.
  • the display device having the first feature includes a second feature that, upon a writing operation of writing pixel data having two tones or more individually in the pixel circuits arranged in one selected row,
  • the scan signal line drive circuit applies a predetermined selected row voltage to the first and second scan signal lines in the selected row to set the first and second transistor elements arranged in the selected row to a conducted state so as to activate the first switch circuits, and applies a predetermined unselected row voltage to the first scan signal line in a row other than the selected row to set the first transistor elements arranged in the anyway row other than the selected row to a non-conducted state so as to deactivate the first switch circuits, and the data signal line drive circuit individually applies a pixel data voltage corresponding to pixel data to be written in the pixel circuit in each column of the selected row, to each of the data signal lines.
  • the display device having the second feature includes a third feature that, upon the writing operation, the voltage supply line drive circuit applies a first control voltage equal to or more than the maximum voltage of the pixel data voltage held in the internal node, to the voltage supply line connected to the pixel circuits arranged in the selected row, and the control line drive circuit applies a first switch voltage to the first control line connected to the pixel circuits arranged in the selected row, and a first boost voltage to the second control line connected to the pixel circuits arranged in the selected row.
  • the display device having the third feature is preferably configured such that, upon the writing operation, the voltage supply line drive circuit applies the first control voltage to the voltage supply line connected to the pixel circuits arranged in the row other than the selected row, and the control line drive circuit applies the first switch voltage to the first control line connected to the pixel circuits arranged in the row other than the selected row, and the first boost voltage to the second control line connected to the pixel circuits arranged in the row other than the selected row.
  • the display device having the third feature is preferably configured such that the first switch voltage is a sufficient voltage to make the fourth transistor element enter a conducted state, and make the internal node and the output node have the same potential.
  • the display device having one of the first to third features includes a fourth feature that, upon the self-refresh operation which is performed, after a writing operation of writing pixel data individually having two tones or more in the pixel circuits arranged in one selected row is finished in each row or all rows of the pixel circuit array, with respect to the pixel circuits for which the writing operation is finished,
  • the scan signal line drive circuit applies the unselected row voltage to the first scan signal line in at least one control target row for which the writing operation is finished to set the first transistor elements of the pixel circuits arranged in the control target row to a non-conducted state, and applies the selected row voltage to the second scan signal line in the control target row to set the second transistor elements of the pixel circuits arranged in the control target row to a conducted state,
  • the voltage supply line drive circuit applies a first control voltage equal to or more than the maximum voltage of the pixel data voltage held in the internal node, to the voltage supply line connected to the pixel circuits arranged in the control target row, and,
  • the control line drive circuit applies a first switch voltage setting the fourth transistor elements to a conducted state, to the first control line connected to the pixel circuits arranged in the control target row so that the internal node and the output node have the same potential
  • the control line drive circuit applies a second switch voltage setting the fourth transistor elements to a non-conducted state to electrically separate the internal node and the output node, and, subsequently, changes a voltage of the second control line connected to the pixel circuits arranged in the control target row from a first boost voltage to a second boost voltage, and boosts a voltage of the output node to a second control voltage obtained by adding a threshold voltage of the third transistor element to the pixel data voltage held in the internal node by way of capacitive coupling through the first capacitative element.
  • the display device having the fourth feature may be configured such that, upon the self-refresh operation, when a certain period of time passes after the voltage of the second control line connected to the pixel circuits arranged in the control target row is changed from a first boost voltage to a second boost voltage, the control line drive circuit performs a refresh canceling operation of returning the voltage of the second control line connected to the pixel circuits arranged in the control target row from the second boost voltage to the first boost voltage and, subsequently, returning the voltage of the first control line connected to the pixel circuits arranged in the control target row from the second switch voltage to the first switch voltage so as to make the internal node and the output node have the same potential, and when a certain period of time passes after the refresh canceling operation, the control line drive circuit performs at least once or more a repeating operation of changing the voltage of the first control line connected to the pixel circuits arranged in the control target row from the first switch voltage to the second switch voltage, changing the voltage of the second control line connected to the pixel circuits arranged
  • the display device having the fourth feature may be configured such that, upon the self-refresh operation, when a certain period of time passes after the voltage of the second control line connected to the pixel circuits arranged in the control target row is changed from a first boost voltage to a second boost voltage, the control line drive circuit performs a refresh canceling operation of changing the voltage of the second scan signal line connected to the pixel circuits arranged in the control target row from the selected row voltage to the unselected row voltage, and returning the voltage of the second control line connected to the pixel circuits arranged in the control target row from the second boost voltage to the first boost voltage, and when a certain period of time passes after the refresh canceling operation, the control line drive circuit performs at least once or more a repeating operation of changing the voltage of the second scan signal line in the control target row from the unselected row voltage to the selected row voltage, changing the voltage of the second control line connected to the pixel circuits arranged in the control target row from a first boost voltage to a second boost voltage and, subsequently, after a
  • the display device having the fourth feature may be configured such that the control line drive circuit performs a first operation of applying the first switch voltage to the first control line connected to the pixel circuits arranged in the control target row so as to make the internal node and the output node have the same potential upon the writing operation with respect to the pixel circuits arranged in the control target row.
  • the display device having the fourth feature may be configured such that, when the control terminals of the fourth transistor elements of the pixel circuits arranged in the same row are connected to the common first control line and the other ends of the first capacitative elements of the pixel circuits arranged in the same row are connected to the common second control line, every time the writing operation is finished with respect to each row of the pixel circuit array, the self-refresh operation may be started for the pixel circuits in the control target row for which the writing operation is finished, without waiting for the writing operation for all rows to be finished.
  • the display device having the fourth feature may be configured such that, when the self-refresh operation is performed after the writing operation is finished for all rows of the pixel circuit array, a first reset voltage equal to or less than a minimum voltage of the pixel data voltage held in the internal node is applied to all of the data signal lines.
  • the pixel circuit and the display device having the above features can write pixel data in the internal node from a data signal line using the first switch circuit upon either normal display or constant display. That is, in the pixel circuit, conduction/non-conduction of the first and second transistor elements forming the first switch circuit is controlled from an outside through the first and second scan signal lines, and the voltage supplied to the data signal line is controlled from an outside, so that it is possible to control the voltage held in the internal node of each pixel circuit. Consequently, it is naturally possible to perform a refresh operation for a voltage held in the internal node by a writing operation of pixel data according to control from an outside.
  • the pixel circuit having the above features does not use the second switch circuit for the writing operation and does not also use the control circuit for the original purpose, and therefore functions in the same manner as the pixel circuit illustrated in FIG. 14 .
  • the normal display mode by performing fine control of the voltage supplied to the data signal line, it is possible to write pixel data with a high tone of full color display by color display using three pixel circuits. Further, by controlling the voltage supplied to the data signal line in multiple tones even upon a constant display mode, it is possible to write pixel data of multiple tones in color display.
  • the pixel circuit according to the present invention forms a sub pixel which is a minimum display unit and corresponds to each color of three primary colors (RGB) in case of color display.
  • pixel data is individual tone data of three primary colors.
  • a sub pixel is formed for the added color.
  • the pixel circuit having the features has the second switch circuit and the control circuit, and, consequently, can maintain the potential of the intermediate node in the first switch circuit in the pixel circuit after the writing operation is finished at the same level as the potential of the internal node immediately after the writing operation, by performing the self-refresh operation according to the following procedure.
  • the first transistor element of the first switch circuit to a non-conducted state and setting the second transistor element to a conducted state, it is possible to compensate for voltage fluctuation of the internal node produced after the writing operation is finished, from the intermediate node through the second transistor element.
  • the voltage is not applied between the first terminal and the second terminal (that is, the source and the drain) of the transistor element (second transistor element) positioned between the intermediate node and the internal node in a voltage holding state of the internal node where the first and second transistor elements of the first switch circuit are set to a non-conducted state, so that it is possible to suppress the leak current flowing in the transistor element. Consequently, it is possible to suppress fluctuation of the pixel data voltage held in the internal node due to the leak current of the transistor element forming the pixel circuit, and suppress a decrease in display quality.
  • the pixel data voltage held in the internal node can be sampled and held in the output node of the control circuit at which the control terminal of the third transistor element, the second terminal of the fourth transistor element, and one end of the first capacitative element are connected mutually, so that it is possible to set the potential of the output node to a potential which is higher than the potential of the internal node by a threshold voltage of the third transistor element forming the second switch circuit by setting the fourth transistor element to the non-conducted state without influencing the pixel data voltage and adjusting the boost voltage inputted to the other end of the first capacitative element through the second control line.
  • the pixel circuit having the features can substantially suppress the leak current of the second transistor element, suppress fluctuation of the pixel data voltage and suppress a decrease in display quality.
  • the second switch circuit and the control circuit do not have a direct current path unlike the configuration of the above conventional technique provided with the buffer amplifier and, consequently, can realize the operation with very low power consumption.
  • the threshold voltage of the transistor is defined as a voltage at which the transistor enters an on state where the drain electrode and the source electrode of the transistor are conducted when the voltage having the absolute value equal to or more than the absolute value of the threshold voltage based on the source electrode or the drain electrode (corresponding to the first or second terminal) is applied to the gate electrode of the transistor (corresponding to the control terminal) so that the current flows between the electrodes when the voltage is applied therebetween, and at which the transistor enters an off state where the drain electrode and the source electrode of the transistor are not conducted when the voltage less than the threshold voltage is applied.
  • the threshold voltage of an N channel type transistor is defined as a positive value
  • the threshold voltage of a P channel type transistor is defined as a negative value.
  • the threshold voltage is defined as a voltage at which a current exceeding the leak current starts flowing between the drain electrode and the source electrode following an increase in the voltage applied to the gate electrode. Meanwhile, the leak current varies among transistors. Therefore, when the leak current causes a problem, it is necessary to purposely-define the threshold voltage according to a function of a target transistor.
  • the features of the circuit configuration include boosting the voltage of the output node (the control terminal (gate electrode) of the third transistor element) to the second control voltage obtained by adding a threshold voltage Vth of the third transistor element to the pixel data voltage held in the internal node. Further, the resulting function and effect are as follows. A case will be described below assuming that the third transistor element is an N channel type transistor.
  • the terminal of the third transistor element on the intermediate node side is the source electrode and the terminal on the voltage supply line side is the drain electrode
  • the voltage of the intermediate node which is a potential difference with respect to a predetermined reference potential, and has the same significance as the “potential” when the reference potential is 0 V
  • the voltage between the gate electrode and the source electrode of the third transistor element increases by the voltage fluctuation ⁇ V higher than the threshold voltage Vth, so that the third transistor element enters the on state.
  • the current follows from the voltage supply line side to the intermediate node side, and the decreased voltage of the intermediate node increases.
  • the voltage fluctuation ⁇ V decreases, and therefore the voltage between the gate electrode and the source electrode of the third transistor element decreases toward the threshold voltage Vth.
  • the third transistor element is in a state where the third transistor element is about to transition from the on state to the off state, and the current supplied from the voltage supply line side to the intermediate node side decreases to the leak current level.
  • an object of purposely-defining the threshold voltage Vth according to the function of the target third transistor element is to decrease the voltage fluctuation ⁇ V compared to the original voltage fluctuation ⁇ V, and make the decreased voltage fluctuation ⁇ V small to such an extent that display quality of pixels is not decreased in terms of the visual perception of people.
  • the threshold voltage Vth is defined as a voltage at which the voltage fluctuation ⁇ V of the intermediate node is 0 V by boosting the voltage of the control terminal (gate electrode) of the third transistor element to the second control voltage obtained by adding the threshold voltage Vth of the third transistor element to the pixel data voltage held in the internal node.
  • the voltage fluctuation ⁇ V matches with the object of the present invention, and the voltage fluctuation ⁇ V of the threshold voltage Vth according to the above definition is also interpreted as 0 V including an error within a certain allowable voltage range.
  • a certain allowable voltage range for example, about several mV to 50 mV
  • FIG. 1 is a block diagram illustrating an example of a schematic configuration of a display device according to the present invention.
  • FIG. 2 is a partial cross-sectional schematic structure diagram of a liquid crystal display device.
  • FIG. 3 is a circuit diagram illustrating a basic circuit configuration (first type) of a pixel circuit according to the present invention.
  • FIG. 4 is a circuit diagram illustrating a circuit configuration example (first type) of the pixel circuit according to the present invention.
  • FIG. 5 is a circuit diagram illustrating a basic circuit configuration (second type) of the pixel circuit according to the present invention.
  • FIG. 6 is a circuit diagram illustrating a circuit configuration example (second type) of the pixel circuit according to the present invention.
  • FIG. 7 is a timing diagram of a writing operation of the pixel circuit according to the present invention in a constant display mode.
  • FIG. 8 is a timing diagram illustrating an embodiment of a self-refresh operation of the pixel circuit according to the present invention with respect to each frame.
  • FIG. 9 is a timing diagram illustrating another embodiment of self-refresh operation of the pixel circuit according to the present invention with respect to each frame.
  • FIG. 10 is a timing diagram illustrating an embodiment of a writing operation and a self-refresh operation of the pixel circuit according to the present invention with respect to each row.
  • FIG. 11 is a timing diagram illustrating another embodiment of a writing operation and a self-refresh operation of the pixel circuit according to the present invention with respect to each row.
  • FIG. 12 is a timing diagram of a writing operation of a normal display mode of the pixel circuit according to the present invention.
  • FIG. 13 is a circuit diagram illustrating another embodiment of a basic circuit configuration of the pixel circuit according to the present invention.
  • FIG. 14 illustrates an equivalent circuit of a pixel circuit of a common active matrix liquid crystal display device.
  • FIG. 15 illustrates an example of a circuit arrangement in an active matrix liquid display device of m ⁇ n pixels.
  • FIG. 16 is an equivalent circuit diagram illustrating an example of a conventional pixel circuit having a buffer amplifier of a unity gain.
  • FIG. 17 is an equivalent circuit diagram illustrating another example of a conventional pixel circuit having a buffer amplifier of a unity gain.
  • a display device (hereinafter, simply “display device”) and a circuit configuration of a pixel circuit according to the present invention (hereinafter, “pixel circuit”) will be described.
  • FIG. 1 illustrates a schematic configuration of a display device 1 .
  • the display device 1 has an active matrix substrate 10 , a counter electrode 30 , a display control circuit 11 , a counter electrode drive circuit 12 , a source driver 13 , a gate driver 14 and various signal lines.
  • On the active matrix substrate 10 a plurality of pixel circuits 2 are arranged in a row direction and a column direction to form a pixel circuit array.
  • the pixel circuits 2 are displayed in block units to avoid complication of drawings.
  • FIG. 1 illustrates the active matrix substrate 10 above the counter electrode 30 for the sake of convenience to clearly display that various signal lines are formed on the active matrix substrate 10 .
  • the display device 1 employs a configuration which can display a screen in two display modes of a normal display mode and a constant display mode using the same pixel circuit 2 .
  • the normal display mode is a display mode which displays a movie or a still image in full color display, and uses transmissive liquid crystal display using a backlight.
  • the constant display mode it is possible to further combine a plurality of sets of three adjacent pixel circuits and increase the number of display colors by area coverage modulation.
  • the constant display mode according to the present embodiment is a technique which can be used by transmissive liquid crystal display and reflective liquid crystal display.
  • a minimum display unit corresponding to one pixel circuit 2 is referred to as a “pixel”, and “pixel data” written in each pixel circuit is tone data of each color in case of color display using three primary colors (R, G and B).
  • pixel data is tone data of each color in case of color display using three primary colors (R, G and B).
  • tone data of this another color and brightness data are also included in pixel data.
  • the display device 1 can perform a “self-refresh operation” described below in the constant display mode of a still image, substantially reduce power consumption compared to a case where a conventional “refresh operation” is executed.
  • the display device 1 is also naturally applicable to a configuration which provides liquid crystal display using only the constant display mode without using the normal display mode and the constant display mode in combination.
  • FIG. 2 is a schematic cross-sectional structure diagram illustrating a relationship between the active matrix substrate 10 and the counter electrode 30 , and illustrates a structure of a display element unit 21 (see FIG. 3 ) which is a component of the pixel circuit 2 .
  • the active matrix substrate 10 is an optically transmissive transparent substrate, and is made of, for example, glass or plastic.
  • the pixel circuits 2 including each signal line are formed on the active matrix substrate 10 .
  • FIG. 2 illustrates pixel electrodes 20 which represent components of the pixel circuit 2 .
  • the pixel electrode 20 is made of an optically transmissive transparent conductive material such as ITO (indium tin oxide).
  • An optically transmissive counter substrate 31 is arranged to oppose to the active matrix substrate 10 , and a liquid crystal layer 33 is held in a gap between these substrates.
  • Polarizing plates (not illustrated) are attached to outer surfaces of both surfaces.
  • the liquid crystal layer 33 is sealed by a sealing member 32 in a peripheral portion of both substrates.
  • the counter electrode 30 which is made of an optically transmissive transparent conductive material such as ITO is formed to oppose to the pixel electrodes 20 .
  • This counter electrode 30 is formed as a single film to spread substantially over the counter substrate 31 .
  • one pixel electrode 20 , the counter electrode 30 and the liquid crystal layer 33 sandwiched therebetween form a unit liquid crystal display element LC (see FIG. 3 ).
  • a backlight device (not illustrated) is arranged on a back surface side of the active matrix substrate 10 , and can emit light in a direction from the active matrix substrate 10 to the counter substrate 31 .
  • a plurality of signal lines are formed on the active matrix substrate 10 in vertical and horizontal directions.
  • a plurality of pixel circuits 2 are formed in a matrix pattern at portions at which m source lines (SL 1 , SL 2 , . . . and SLm) extending in the vertical direction (column direction) and n gate lines (GL 1 , GL 2 , . . . and GLn) extending in the horizontal direction (row direction) to form the pixel circuit array.
  • m and n are natural numbers equal to or more than 2, respectively.
  • n auxiliary gate lines (AGL 1 , AGL 2 , . . . and AGLn) extending in the horizontal direction (row direction) are provided in addition to n gate lines.
  • each source line (SL 1 , SL 2 , . . . and SLm) is collectively referred to as the “source line SL”
  • each gate line (GL 1 , GL 2 , . . . and GLn)
  • each auxiliary gate line (AGL 1 , AGL 2 , . . . and AGLn) is collectively referred to as the “auxiliary gate line AGL”.
  • the source line SL corresponds to the “data signal line”
  • the gate line GL corresponds to the “first scan signal line”
  • the auxiliary gate line AGL corresponds to the “second scan signal line”.
  • the source driver 13 corresponds to a “data signal line drive circuit”
  • the gate driver 14 corresponds to a “scan signal line drive circuit”
  • part of the display control circuit 11 corresponds to a “control line drive circuit” and a “voltage supply line drive circuit”.
  • the signal lines for driving the pixel circuits 2 include a first control line SWL, a second control line BST, an auxiliary capacity line CSL (corresponding to the “third control line”) and a voltage supply line VSL in addition to the source line SL and the gate line GL.
  • the auxiliary capacity line CSL is driven by, for example, the display control circuit 11 .
  • the first control line SWL, the second control line BST, the auxiliary capacity line CSL, and the voltage supply line VSL are provided for each row so as to extend in the row direction, and wirings of respective rows are mutually connected and unified in a peripheral portion of the pixel circuit array
  • a configuration may be employed where the wirings of respective rows are individually driven, and a common voltage can be applied thereto according to an operation mode.
  • the “self-refresh operation” described below is collectively executed with respect to the pixel circuits 2 in the pixel circuit array for each row, the first control line SWL, the second control line BST, and the voltage supply line VSL are independently provided in each row so as to extend in the row direction.
  • the “self-refresh operation” when the “self-refresh operation” is collectively executed with respect to all pixel circuits 2 in the pixel circuit array or is collectively executed for each column, part or all of the first control line SWL, the second control line BST, and the voltage supply line VSL may be provided in each column so as to extend in the column direction. Furthermore, when the “self-refresh operation” is collectively executed with respect to all pixel circuits 2 in the pixel circuit array or is collectively executed in units of a plurality of rows, the auxiliary gate line AGL may be provided such that the wirings of respective rows are mutually connected and unified in all rows or in units of a plurality of rows in the peripheral portion of the pixel circuit array similar to the first control line SWL and the second control line BST.
  • the display control circuit 11 is a circuit which controls each writing operation in the normal display mode and the constant display mode described below, and the self-refresh operation in the constant display mode.
  • the display control circuit 11 receives a data signal Dv showing an image to be displayed and a timing signal Ct from an external signal source, and generates a digital image signal DA and a data side timing control signal Stc given to the source driver 13 , a scan side timing control signal Gtc given to the gate driver 14 , a counter voltage control signal Sec given to the counter electrode drive circuit 12 and each signal voltage applied to the first control line SWL, the second control line BST, the auxiliary capacity line CSL, and the voltage supply line VSL, respectively based on the signals Dv and Ct as signals for displaying an image on the display element unit 21 of the pixel circuit array.
  • part or the entirety of the display control circuit 11 is preferably formed in the source driver 13 or the gate driver 14 .
  • the source driver 13 is a circuit which applies source signals of a predetermined timing and a predetermined voltage value to each source line SL upon the writing operation and the self-refresh operation according to control by the display control circuit 11 .
  • the source driver 13 generates the voltage which is appropriate for a voltage level of a counter voltage Vcom and corresponds to a pixel value of one display line shown by a digital signal DA based on the digital image signal DA and the data side timing control signal Stc upon the writing operation for each horizontal period (also referred to as “1H period”) as source signals Sc 1 , Sc 2 , . . . and Scm.
  • the voltages are analog voltages of multiple tones (a plurality of mutually discrete voltage values) according to the normal display mode and the constant display mode.
  • these source signals are applied to the source lines SL 1 , SL 2 , . . . and SLm, respectively. Furthermore, the source driver 13 applies the same voltage to all source lines SL connected to the target pixel circuits 2 upon the self-refresh operation according to control by the display control circuit 11 (details will be described below).
  • the gate driver 14 is a circuit which applies the gate signal and the auxiliary gate signal of a predetermined timing and a predetermined voltage amplitude to each gate line GL and each auxiliary gate line AGL upon the writing operation and the self-refresh operation according to control by the display control circuit 11 .
  • the gate driver 14 sequentially selects the gate lines GL 1 , GL 2 , . . . and GLn and the auxiliary gate lines AGL 1 , AGL 2 , . . . and AGLn substantially for each horizontal period in each frame period of the digital image signal DA in order to write the source signals Sc 1 , Sc 2 , . . . and Scm in each pixel circuit 2 based on the scan side timing control signal Gtc.
  • the gate driver 14 applies the same voltage to all gate lines GL connected to the target pixel circuits 2 according to control by the display control circuit 11 , and performs the voltage control on all auxiliary gate lines AGL connected to the target pixel circuits 2 at the same timing (details will be described below).
  • the gate driver 14 may be formed on the active matrix substrate 10 similar to the pixel circuit 2 .
  • the auxiliary gate lines AGL may be provided such that the wirings of respective rows are mutually connected and unified in all rows or in units of a plurality of rows in the peripheral portion of the pixel circuit array, and may be configured to be driven by the display control circuit 11 instead of the gate driver 14 .
  • the counter electrode drive circuit 12 applies the counter voltage Vcom to the counter electrode 30 through the counter electrode wiring CML.
  • the counter electrode drive circuit 12 switches the counter electrode Vcom between a predetermined high level (5 V) and a predetermined low level (0 V) and outputs the counter electrode Vcom in the normal display mode and the constant display mode.
  • Driving the counter electrode 30 by switching the counter voltage Vcom between a high level and a low level in this way is referred to as “counter AC driving”.
  • counter AC driving in the normal display mode is directed to switching the counter voltage Vcom between a high level and a low level for each horizontal period and for each one frame.
  • the voltage polarity between the counter electrode 30 and the pixel electrode 20 changes between two adjacent horizontal periods, and, in one same horizontal period, the voltage polarity between the counter electrode 30 and the pixel electrode 20 changes between two adjacent frame periods.
  • the same voltage level is maintained in one frame period in the constant display mode, the voltage polarity between the counter electrode 30 and the pixel electrode 20 changes between two adjacent writing operations.
  • FIG. 3 illustrates a basic circuit configuration of the pixel circuit 2 according to the present invention.
  • the pixel circuit 2 is configured to have a display element unit 21 which includes a unit liquid crystal display element LC, an auxiliary capacitative element C 2 (corresponding to the second capacitative element), a first switch circuit 22 , a second switch circuit 23 and a control circuit 24 .
  • the basic circuit configuration illustrated in FIG. 3 is a circuit configuration of an broader concept including a specific circuit configuration example illustrated in FIG. 4 (the simplest circuit configuration example including the auxiliary capacitative element C 2 ).
  • the unit liquid crystal display element LC is as described with reference to FIG. 2 , and therefore will not be described.
  • the auxiliary capacitative element C 2 has one end connected to the internal node N 1 and the other end connected to an auxiliary capacity line CSL.
  • the auxiliary capacitative element C 2 is supplementarily added to enable the internal node N 1 to stably hold the pixel data voltage.
  • the pixel data voltage is a pixel voltage V 20 applied to the pixel electrode 20 , and will be referred to as the “pixel voltage V 20 ” below accordingly.
  • the first switch circuit 22 has the other end connected to the source line SL and at least a series circuit of a transistor T 1 (corresponding to the first transistor element) and a transistor element T 2 (corresponding to the second transistor element), and a control terminal of the transistor T 1 is connected with the gate line GL and a control terminal of the transistor T 2 is connected with the auxiliary gate line AGL. At least when the transistor T 1 is in the off state, the first switch circuit 22 enters the off state (non-conducted state), and conduction between the source line SL and the internal node N 1 is blocked.
  • a connection point N 2 for connecting the transistor T 1 and the transistor T 2 in series is referred to as an “intermediate node N 2 ”.
  • intermediate node N 2 In a circuit configuration example illustrated in FIG.
  • the first switch circuit 22 consists of only a series circuit of the transistor T 1 and the transistor T 2 , and a first terminal of the transistor T 1 is connected with the source line SL and a second terminal of the transistor T 1 is connected with a first terminal of the transistor T 2 to form an intermediate node N 2 and a second terminal of the transistor T 2 is connected with the internal node N 1 .
  • the second switch circuit 23 has a transistor T 3 (corresponding to a third transistor element), one end connected with the voltage supply line VSL, and the other end connected with the intermediate node N 2 .
  • a control terminal of the transistor T 3 is connected with an output node N 3 of the control circuit 24 , and the on state (conducted state) of the transistor T 3 is controlled according to a voltage state of the output node N 3 .
  • the second switch circuit 23 consists of only the transistor T 3 , and a first terminal of the transistor T 3 is connected with the voltage supply line VSL and a second terminal is connected with the intermediate node N 2 .
  • the control circuit 24 consists of a series circuit of a transistor T 4 (corresponding to a fourth transistor element) and a first capacitative element C 1 , and a first terminal of the transistor T 4 is connected with the internal node N 1 , a second terminal of the transistor T 4 is connected with one end of the first capacitative element C 1 , a control terminal of the transistor T 4 is connected with the first control line SWL, and the other end of the first capacitative element C 1 is connected with the second control line BST.
  • a connection point of the second terminal of the transistor T 4 and one end of the first capacitative element C 1 forms an output node N 3 .
  • the output node N 3 has the same potential as the internal node N 1 when the transistor T 4 is in the on state, a voltage level of the pixel voltage V 20 held in the internal node N 1 is sampled to the output node N 3 , and the voltage level of the sampled pixel voltage V 20 is held when the transistor T 4 enters the off state.
  • a predetermined boost voltage to the second control line BST connected with the other end of the first capacitative element C 1 , it is possible to change and adjust the voltage level held in the output node N 3 by way of capacitive coupling through the first capacitative element C 1 and perform fine control of the on state of the transistor T 3 of the second switch circuit 23 according to the adjusted voltage level.
  • the above four types of the transistors T 1 to T 4 are thin film transistors such as polysilicon TFTs or amorphous silicon TFTs each formed on the active matrix substrate 10 , and one of the first and second terminals corresponds to a drain electrode, the other thereof corresponds to a source electrode and a control terminal corresponds to a gate electrode. Further, although each of the transistors T 1 to T 4 may be formed with a single transistor, when suppression of a leak current upon the off state is highly demanded, a configuration of connecting a plurality of transistors in series and sharing the control terminal may be employed. In addition, the following description of the operation of the pixel circuit 2 assumes that all of the transistors T 1 to T 4 are N channel type polysilicon TFTs, and the threshold voltage is about 2 V.
  • the pixel circuit 2 may be configured such that the voltage supply line VSL also serves as the auxiliary capacity line CSL and is referred to as the voltage supply line CSL/VSL, and the other end of the auxiliary capacitative element C 2 and one end of the second switch circuit 23 are connected to the same voltage supply line CSL/VSL, compared to the circuit configuration illustrated in FIG. 3 or 4 .
  • the voltage supply line VSL also serves as the auxiliary capacity line CSL and is referred to as the voltage supply line CSL/VSL.
  • the circuit configuration illustrated in FIGS. 3 and 4 and the circuit configuration illustrated in FIGS. 5 and 6 are distinguished as a first type and a second type, respectively.
  • the pixel circuit 2 having the circuit configuration illustrated in FIG. 4 or 6 can be modified such that another transistor element is connected to the series circuit of the transistor T 1 and the transistor T 2 of the first switch circuit 22 in series or such that another transistor element is connected to the transistor element T 3 of the second switch circuit 23 in series, upon the writing operation and the self-refresh operation, as long as conduction/non-conduction of the added transistor element is controlled according to conduction/non-conduction of the transistor element positioned on the same side based on the intermediate node N 2 of the first switch circuit 22 and the second switch circuit 23 , operations of the first and second switch circuits 22 and 23 upon the writing operation and the self-refresh operation are substantially the same between the circuit configuration illustrated in FIG.
  • pixel data of one frame is divided with respect to each display line in a horizontal direction (row direction), a pixel data voltage (in case of four tones, one of four tone voltages being discrete in a voltage range from a low level (0 V) to a high level (5 V)) corresponding to each pixel data of one display line is applied to the source line SL in each column, a selected row voltage 8 V is applied to the gate line GL and the auxiliary gate line AGL of the selected display line (selected row), the first switch circuits 22 of all pixel circuits 2 in the selected row are set to the conducted state, and the voltage of the source line SL in each column is transferred to the internal node N 1 of each pixel circuit 2 in the selected row.
  • a pixel data voltage in case of four tones, one of four tone voltages being discrete in a voltage range from a low level (0 V) to a high level (5 V)
  • a selected row voltage 8 V is applied to the gate line GL and the auxiliary gate line AGL of the selected display
  • An unselected row voltage ⁇ 5 V is applied to the gate line GL other than the selected display line (unselected row) to set the first switch circuits 22 of all pixel circuits 2 in the selected row to the non-conducted state.
  • the auxiliary gate lines AGL are provided for each row and therefore the unselected row voltage ⁇ 5 V is applied to the auxiliary gate line AGL in the unselected row similar to the gate line GL, it is possible to set the first switch circuit 22 to the non-conducted state only by controlling the gate line GL and it is not necessary at all times to control the auxiliary gate line AGL with respect to each row upon the writing operation.
  • the display control circuit 11 illustrated in FIG. 1 controls a timing of applying the voltage to each signal line upon the writing operation described below, and the display control circuit 11 , the counter electrode drive circuit 12 , the source driver 13 and the gate driver 14 individually apply voltages.
  • the tone voltage is determined based on transmittance characteristics of a liquid crystal layer 33 with respect to a liquid crystal voltage Vlc applied between the pixel electrode 20 and the counter electrode 30 of the unit liquid crystal display element LC.
  • the liquid crystal voltage Vic is given as a difference voltage (V 20 -Vcom) between the counter voltage Vcom of the counter electrode 30 and the pixel voltage V 20 held in the pixel electrode 20 .
  • FIG. 7 illustrates a timing diagram of the writing operation in the constant display mode when a first type pixel circuit is used.
  • FIG. 7 illustrates each voltage waveform of two gate lines GL 1 and GL 2 , two auxiliary gate lines AGL 1 and AGL 2 , two source lines SL 1 and SL 2 , a first control line SWL, a second control line BST, a voltage supply line VSL, and an auxiliary capacity line CSL, and the voltage waveform of the counter voltage Vcom in one frame period.
  • FIG. 7 illustrates each voltage waveform of the pixel voltages V 20 of the internal nodes N 1 of the two pixel circuits 2 .
  • One of the two pixel circuits 2 is a pixel circuit 2 ( a ) selected by the gate line GL 1 and the source line SL 1
  • the other one is a pixel circuit 2 ( b ) selected by the gate line GL 1 and the source line SL 2
  • the pixel circuits 2 are distinguished by adding (a) and (b) behind the pixel voltages V 20 in FIG. 7 .
  • One frame period is divided into horizontal periods the number of which corresponds to the number of gate lines GL, and the gate lines GL 1 to GLn to be selected are sequentially allocated to the respective horizontal periods.
  • FIG. 7 illustrates voltage changes in two gate lines GL 1 and GL 2 and auxiliary gate lines AGL 1 and AGL 2 in the first two horizontal periods.
  • the selected row voltage 8V is applied to the gate line GL 1 and the auxiliary gate line AGL 1 and the unselected row voltage ⁇ 5 V is applied to the gate line GL 2 and the auxiliary gate line AGL 2 in the first horizontal period
  • the selected row voltage 8 V is applied to the gate line GL 2 and the auxiliary gate line AGL 2 and the unselected row voltage ⁇ 5 V is applied to the gate line GL 1 and the auxiliary gate line AGL 1 in the second horizontal period
  • the unselected row voltage ⁇ 5 V is applied to the gate lines GL 1 and GL 2 and the auxiliary gate lines AGL 1 and AGL 2 in subsequent horizontal periods, respectively.
  • a multilayer voltage (0 V to 5 V and is displayed by a cross hatching except in the first horizontal period) corresponding to each of the pixel data of a display line corresponding to each horizontal period is applied to the source line SL in each column (two source lines SL 1 and SL 2 are illustrated in FIG. 7 as representatives).
  • voltages of the two source lines SL 1 and SL 2 in the first horizontal period are separately set to 5 V and 0 V to describe the change of the pixel voltage V 20 .
  • each applied voltage of the first control line SWL, the second control line BST, the voltage supply line VSL, and the auxiliary capacity line CSL is constant through one frame period with the writing operation which is not executed in parallel to the self-refresh operation, and therefore each of the above signal lines has no substantial difference between a case where wirings in respective rows are mutually connected and unified and a case where wirings in respective rows are independently provided.
  • FIG. 7 illustrates a voltage waveform of the former case.
  • the first switch circuit 22 consists of a series circuit of the transistor T 1 and the transistor T 2 , and conduction/non-conduction of the first switch circuit 22 is controlled by performing on/off control of the transistor T 1 and the transistor T 2 . More specifically, the selected row voltage 8 V is applied to the gate line GL and the auxiliary gate line AGL in the selected row as described above, and the unselected row voltage ⁇ 5 V is applied to the gate line GL and the auxiliary gate line AGL in the unselected row. In addition, the reason for using ⁇ 5 V which is a negative voltage as the unselected row voltage ⁇ 5 V is as follows.
  • the pixel voltage V 20 is likely to change to the negative voltage following the voltage change of the counter voltage Vcom, and therefore it is necessary to prevent the first switch circuit 22 in the non-conducted state from entering the conducted state unnecessarily in this state.
  • the second switch circuit 23 needs to be set to the non-conducted state to prevent interference from the voltage supply line VSL in the writing operation.
  • the second switch circuit 23 consists of only the transistor T 3 , and the transistor T 3 is substantially set to the off state.
  • the second switch circuit 23 functions as a forward diode from the intermediate node N 2 to the source line SL, and the first control voltage (5 V in the second embodiment) equal to or more than the maximum voltage of the pixel data voltage (tone voltage) held in an internal node N 1 is applied to a voltage supply line VSL through one frame period to place the diode in an inverse bias state, and set the second switch circuit 23 to a non-conducted state.
  • first switch voltage which is higher than the first control voltage (5 V) by a threshold voltage (about 2 V) or more is applied to the first control line SWL to set a transistor T 4 to the on state at all times irrespectively of the voltage state of the internal node N 1 during one frame period.
  • the high voltage 8 V is applied to the first control line SWL, and a pixel data voltage (tone voltage) transferred to the internal node N 1 by the writing operation of each pixel circuit 2 is sampled to the output node N 3 as a preparation operation for collectively executing the self-refresh operation on the pixel circuits 2 of one frame, after the writing operation for one frame period is finished.
  • the output node N 3 and the internal node N 1 are electrically connected in a state where the transistor T 4 is in the on state at all times, the first capacitative element 1 connected to the internal node N 1 through the transistor T 4 can be used to hold the pixel voltage V 20 , which contributes to the stabilization of the pixel voltage V 20 .
  • the second control line BST is fixed to a predetermined fixed voltage (for example, 0 V: first boost voltage), and the auxiliary capacity line CSL is also fixed to a predetermined fixed voltage (for example, 0 V).
  • a predetermined fixed voltage for example, 0 V: first boost voltage
  • the auxiliary capacity line CSL is also fixed to a predetermined fixed voltage (for example, 0 V).
  • a predetermined fixed voltage (0 V in FIG. 7 ) is applied to the auxiliary capacity line CSL.
  • the first control voltage (5 V) is applied to the voltage supply line CSL/VSL functioning as the voltage supply line VSL and the auxiliary capacity line CSL.
  • the second type pixel circuit can execute counter AC driving by applying the first control voltage (5 V) to the voltage supply line CSL/VSL instead of giving the same voltage change as the counter voltage Vcom in the counter AC driving operation for each frame period.
  • the transistor T 3 in series another transistor element which is turned off upon the writing operation and is turned on upon the self-refresh operation in the second switch circuit 23 employing the circuit configuration illustrated in FIG. 6 , it is possible to impart the same voltage change as the counter voltage Vcom to the voltage supply line CSL/VSL upon this counter AC driving.
  • the self-refresh operation is an operation in a constant display mode, and is an operation of, for a plurality of pixel circuits 2 , controlling the on state of a transistor T 3 forming a second switch circuit 23 using a voltage Vn 3 held in an output node N 3 of each pixel circuit 2 , supplying the current from the voltage supply line VSL through the transistor T 3 , an intermediate node N 2 and a transistor T 2 , and collectively compensating for voltage fluctuation produced in the pixel voltage V 20 held in the internal node N 1 irrespectively of a tone value of a pixel data voltage held in each pixel circuit 2 .
  • the self-refresh operation is an operation of, in the off state of a transistor T 1 of a first switch circuit 22 , setting the transistor T 2 to the on state, activating a control circuit 24 according to a predetermined sequence, controlling bias states of a first terminal and a control terminal of the transistor T 3 , maintaining the voltage of the intermediate node N 2 to the same or substantially the same voltage as the internal node N 1 immediately after the writing operation, and feeding back the voltage of the intermediate node N 2 to the internal node N 1 in which voltage fluctuation occurs.
  • the self-refresh operation is collectively performed at the same time targeting all the pixel circuits 2 of one frame after the writing operation is finished.
  • the same voltage is applied to all gate lines GL, auxiliary gate lines AGL, source lines SL, first control line SWL, second control line BST, voltage supply line VSL, auxiliary capacity line CSL, and counter electrode 30 connected to the pixel circuits 2 , which are self-refresh operation targets, at the same timing.
  • a display control circuit 11 illustrated in FIG. 1 controls a timing of applying the voltage to each signal line, and the display control circuit 11 , a counter electrode drive circuit 12 , a source driver 13 and a gate driver 14 individually apply voltages.
  • the self-refresh operation is an operation of the pixel circuit 2 unique to the present invention, and can substantially reduce power consumption compared to the same operation of suppressing a leak current by voltage driving using a buffer amplifier of a unity gain with respect to a conventional intermediate node.
  • the phrase “at the same time” in the above phrase “collectively . . . at the same time” means “the same time” including a time width of a series of self-refresh operations.
  • FIG. 8 illustrates a timing diagram of the self-refresh operation targeting all the pixel circuits 2 of one frame when the first type pixel circuit is used.
  • the entire self-refresh operation includes three basic phases (phases A to C)
  • each operation in the phases A and B is an operation of preparing for the self-refresh operation
  • the operation in the phase C is a main operation.
  • the operation in the phase C is referred to as a “self-refresh main operation”, and is distinguished from the entire self-refresh operation in the phases A to C.
  • FIG. 8 illustrates each voltage waveform of all gate lines GL, auxiliary gate lines AGL, source lines SL, first control line SWL, second control line BST, voltage supply line VSL, and auxiliary capacity line CSL connected to the pixel circuits 2 which are self-refresh operation targets, and the voltage waveform of a counter electrode Vcom. Further, FIG. 8 illustrates each voltage waveform of a voltage V 20 of the internal node N 1 , a voltage Vn 2 of the intermediate node N 2 , and a voltage Vn 3 of the output node N 3 assuming that the pixel voltage V 20 of the internal node N 1 is a high voltage tone.
  • V 20 ( 0 ) represents the pixel voltage V 20 immediately after the writing operation or before voltage fluctuation occurs.
  • Each voltage of the gate lines GL, the source lines SL, the voltage supply line VSL and the auxiliary capacity line CSL, and the counter voltage Vcom are maintained at a certain voltage through three basic phases (phases A to C).
  • a voltage of ⁇ 5 V is applied to the gate line GL to set the transistor T 1 of the first switch circuit 22 of the operation target pixel circuit 2 to the off state.
  • a first reset voltage ( ⁇ 1 V in the present embodiment) equal to or less than a minimum voltage (0 V in the present embodiment) of the pixel data voltage (tone voltage) held in the internal node N 1 (the reason for applying the first reset voltage will be described below) is applied to the source line SL.
  • a first control voltage (5 V in the present embodiment) equal to or more than the maximum voltage (5 V in the present embodiment) of the pixel data voltage (tone voltage) held in the internal node N 1 is applied to the voltage supply line VSL.
  • the same voltage continuously from the writing operation is applied to the voltage supply line VSL.
  • the auxiliary capacity line CSL is fixed to a predetermined fixed voltage (for example, 0 V).
  • the counter voltage Vcom is fixed to 0 V or 5 V similar to a voltage upon the writing operation (the counter voltage Vcom is fixed to 0 V in FIG. 8 ).
  • a predetermined fixed voltage (0 V in FIG. 8 ) is applied to the auxiliary capacity line CSL
  • the first control voltage (5 V) is applied to the voltage supply line CSL/VSL functioning as the voltage supply line VSL and the auxiliary capacity line CSL.
  • a first switch voltage (8V) which sets the transistor T 4 to the on state irrespectively of the voltage state of the internal node N 1 is applied from the first control line SWL to the control terminal of the transistor T 4 in a certain period (t 0 to t 1 ) from time t 0 immediately after the writing operation is finished, the output node N 3 and the internal node N 1 are electrically connected, and the pixel voltage V 20 ( 0 ) of the internal node N 1 is sampled to the output node N 3 .
  • the voltage of the first control line SWL changes from the first switch voltage (8 V) to the second switch voltage ( ⁇ 5 V) at time t 1
  • the transistor T 4 is set to the off state
  • the output node N 3 and the internal node N 1 are electrically separated
  • the pixel voltage V 20 ( 0 ) of the internal node N 1 is held in the output node N 3 .
  • This holding state is continued to time t 2 at which the phase C starts.
  • the pixel voltage V 20 ( 0 ) of the internal node N 1 is sampled to the output node N 3 upon the writing operation as described above, so that it is possible to skip the sampling period of the phase A (t 0 to t 1 ).
  • the auxiliary gate line AGL in this row is changed from the selected row voltage 8 V to the unselected row voltage ⁇ 5 V at time t 1 .
  • the transistor T 4 enters the off state, so that the holding period of the phase B (t 1 to t 2 ) can be set in a short time in accordance with response characteristics of the transistor T 4 .
  • the second control line BST is fixed to the first boost voltage (for example, 0 V) set upon the writing operation during the phase A period.
  • V 20 ( 0 ) is a pixel voltage held in the internal node N 1 and is equal to the voltage of the output node N 3 upon sampling
  • ⁇ Vswl is a voltage difference (13 V) between the first switch voltage (8V) and the second switch voltage ( ⁇ 5V)
  • Cbst is an electrical capacitance of the first capacitative element C 1
  • Cn 3 is an electrical capacitance obtained by subtracting the electrical capacitance Cbst of the first capacitative element C 1 from the electrical capacitance parasitizing the output node N 3
  • (Cbst+Cn 3 ) is the total electrical capacitance parasitizing the output node N 3 .
  • phase C (t 2 to t 3 ) subsequent to the phase B (t 1 to t 2 )
  • a boosting operation of changing the auxiliary gate line AGL from the unselected row voltage ⁇ 5 V to the selected voltage 8V, and further changing the second control line BST from the first boost voltage to the second boost voltage (for example, about 3 V) is performed.
  • the boosting operation boosts the voltage Vn 3 of the output node N 3 to a voltage Vn 3 (t 2 ) shown in following equation (3) by way of capacitive coupling of the first capacitative element C 1 .
  • Vn 3( t 2) Vn 3( t 1)+ ⁇ Vbst ⁇ Cbst /( Cbst+Cn 3) (Equation 3)
  • Vn 3( t 2) V 20(0)+ Vt 3 (Equation 4)
  • the first term on the right side of equation 3 is given from equation 2, and the sum of the second term on the right side of equation 3 and the second term on the right side of equation 2 (minus value) only needs to be the threshold voltage Vt 3 of the transistor T 3 .
  • the second term on the right side of equation 3 when the second term on the right side of equation 2 is small to such an extent that the second term can be ignored, the second term on the right side of equation 3 only needs to be the threshold voltage Vt 3 of the transistor T 3 .
  • a voltage obtained by adding the threshold voltage Vt 3 of the transistor T 3 to the pixel voltage V 20 ( 0 ) is applied to the control terminal of the transistor T 3 , and a voltage obtained by subtracting the threshold voltage Vt 3 from the voltage Vn 3 (t 2 ) applied to the control terminal of the transistor T 3 , that is, the pixel voltage V 20 ( 0 ) held in the internal node N 1 before voltage fluctuation, is supplied to the intermediate node N 2 .
  • the voltage Vn 2 of the intermediate node N 2 is the same pixel voltage V 20 ( 0 ) as the internal node N 1 immediately after the writing operation, the voltage is likely to fluctuate from the original pixel voltage V 20 ( 0 ) due to the leak current through the transistor T 1 caused by fluctuation of the voltage applied to the source line SL. Further, voltage fluctuation of the intermediate node N 2 causes voltage fluctuation of the pixel voltage V 20 of the internal node N 1 .
  • the voltage returns to the original pixel voltage V 20 ( 0 ) through the transistor T 3 during the phase C period and the returned pixel voltage V 20 ( 0 ) is fed back to the internal node N 1 through the transistor T 2 in the on state, so that fluctuation of the pixel voltage V 20 produced in the internal node N 1 returns to a state immediately after the writing operation.
  • the leak current of the transistor T 1 is supplied from the transistor T 3 side, so that the voltage Vn 2 (t 2 ) of the intermediate node N 2 during the phase C period is maintained to the pixel voltage V 20 ( 0 ) or a neighborhood value.
  • the voltage V 20 of the internal node N 1 suppresses significant voltage fluctuation which decreases display quality, and is stably maintained to the originally written pixel voltage V 20 ( 0 ) or its neighborhood value.
  • FIG. 8 schematically illustrates that the voltage Vn 2 of a high voltage tone of the intermediate node N 2 returns from a state where the voltage is slightly decreased to the originally written voltage V 20 ( 0 ) according to the boosting operation.
  • the voltage Vn 2 of the intermediate node N 2 returns to the originally written voltage V 20 ( 0 ), so that the voltage V 20 of the internal node N 1 also returns to the originally written voltage V 20 ( 0 ) through the transistor T 2 .
  • a refresh canceling operation for finishing the self-refresh main operation is executed. Consequently, the phase D represents a state after the self-refresh operation is finished.
  • the refresh canceling operation is the same holding operation as in the holding period of the phase B (t 1 to t 2 ), and is referred to as the “holding operation” below for the sake of convenience.
  • the voltage of the auxiliary gate line AGL is changed from the selected row voltage 8 V to the unselected row voltage ⁇ 5 V
  • the voltage of the second control line BST is changed from the second boost voltage to the first boost voltage and is returned to the state before the boosting operation.
  • the voltage Vn 3 of the output node N 3 is stepped down by a voltage boosted by the boosting operation in the phase C by way of capacitive coupling of the first capacitative element C 1 .
  • the phase C period is shorter to such an extent that the voltage Vn 3 (t 2 ) of the output node N 3 does not decrease due to the leak current of the transistor T 4 , the voltage Vn 3 of the output node N 3 changes to the pixel electrode V 20 ( 0 ) immediately after sampling.
  • both of the transistor T 2 and the transistor T 4 connected to the internal node N 1 enter the off state, and the internal node N 1 enters a holding operation state of holding the original pixel voltage V 20 ( 0 ) for which voltage fluctuation is compensated for. Meanwhile, the transistor T 4 is in the off state, and therefore the output node N 3 also enters the holding operation state of holding the original pixel voltage V 20 ( 0 ).
  • the voltage Vn 2 of the intermediate node N 2 is likely to fluctuate due to, for example, the leak current through the transistor T 1 of the first switch circuit 22 as described above, and the pixel voltage V 20 of the internal node N 1 fluctuates in some cases due to voltage fluctuation of the intermediate node N 2 .
  • the voltage of the auxiliary gate line AGL is changed from the unselected row voltage ⁇ 5 V to the selected row voltage 8 V at time t 4 after a certain period of time passes from time t 3 to compensate for voltage fluctuation of the intermediate node N 2 and the internal node N 1 in the holding operation period in the phase D (t 3 to t 4 ), the boosting operation of changing the voltage of the second control line BST from the first boost voltage to the second boost voltage is performed and the self-refresh main operation in the phase C (t 4 to t 5 ) is executed again.
  • the self-refresh main operation in the phase C is as described above, and overlapping description will be skipped.
  • the self-refresh main operation in the phase C and the holding operation in the phase D are repeatedly executed in order.
  • the continuing time of the holding operation in the phase D is set according to the degree of voltage fluctuation of the pixel voltage V 20 during the holding operation period. Specifically, if the voltage fluctuation is not handled, the voltage fluctuation appears as fluctuation in display brightness of pixels (the transmittance of liquid crystal) and leads to deterioration in display quality. Thus, the continuing time of the holding operation in the phase D is set to the extent that the voltage fluctuation may not cause such a result.
  • ⁇ 5 V is applied to the gate line GL to set the transistor T 1 of the first switch circuit 22 of the operation target pixel circuit 2 to the off state. Further, during the holding operation period in the phase B and the phase D, ⁇ 5 V is applied to the auxiliary gate line AGL to set the transistor T 2 of the first switch circuit 22 of the operation target pixel circuit 2 to the off state.
  • the first reset voltage ( ⁇ 1 V in the third embodiment) equal to or less than the minimum voltage of the pixel data voltage (tone voltage) held in the internal node N 1 is applied to the source line SL, this reason will be described.
  • the pixel voltage V 20 lower than the voltage of the source line SL is held in the internal node N 1 of the pixel circuit 2 connected to this source line SL in some cases.
  • the voltage of the intermediate node N 2 is equal to the pixel voltage V 20 immediately after the writing operation
  • the leak current of the transistor T 1 flows from the source line SL side to the intermediate node N 2
  • a supply of currents from both of the transistor T 1 and the transistor T 3 causes fluctuation of the voltage in the intermediate node N 2 which voltage is boosted from the same pixel voltage V 20 as the internal node N 1 immediately after the writing operation.
  • the first reset voltage applied to the source line SL is the same, if the pixel data voltage (tone voltage) held in the internal node N 1 is higher, the voltage of the intermediate node N 2 is higher, and therefore the leak current of the transistor T 1 increases. That is, when the voltage Vn 3 (t 2 ) of the output node N 3 during the phase C period is a sum of the pixel voltage V 20 and the threshold voltage Vt 3 of the transistor T 3 , a difference is produced in the leak current of the transistor T 1 due to the tone voltage, and therefore a slight difference is produced in the voltage Vn 2 maintained in the intermediate node N 2 .
  • the tone voltage is determined based on transmittance characteristics of a liquid crystal layer 33 with respect to a liquid crystal voltage Vlc applied to between the pixel electrode 20 and the counter electrode 30 of a unit liquid crystal display element LC
  • the transmittance characteristics are not necessarily linear, and therefore this voltage fluctuation appears as significant fluctuation of the transmittance of liquid crystal in the intermediate tone voltage.
  • a self-refresh operation according to the fourth embodiment also includes three basic phases (phases A to C) similar to the above third embodiment, and the content of the self-refresh operation is completely the same as that in the third embodiment. As illustrated in FIG.
  • FIG. 9 is a timing diagram of the self-refresh operation which is created similar to FIG. 8 and which targets all the pixel circuits 2 of one frame when a first type pixel circuit is used.
  • the voltage Vn 3 (t 2 ) of the output node N 3 decreases in the phase C
  • the voltage Vn 2 of the intermediate node N 2 also decreases following a decrease in the voltage Vn 3 (t 2 ) due to the leak current of a transistor T 1 , and therefore the pixel voltage V 20 held in the internal node N 1 decreases.
  • a boosting state in the phase C is temporarily stopped and the voltage Vn 3 of the output node N 3 is refreshed.
  • the refresh operation of the voltage Vn 3 is realized by executing the phase D (t 3 to t 6 ) after the phase C is finished, and subsequently, executing the self-refresh main operation of the phase C again.
  • the same sampling and holding operations as in the phase A and the phase B are executed.
  • the first control line SWL is changed from the second switch voltage ( ⁇ 5 V) to the first switch voltage (8 V)
  • the holding state is canceled and the transistor T 4 is set to the on state.
  • the voltage Vn 3 (t 2 ) of the output node N 3 slightly decreases due to the leak current of the transistor T 4 during the phase B period, the voltage Vn 3 of the output node N 3 decreases below the pixel voltage V 20 immediately after sampling, the pixel voltage V 20 of the output node N 1 is newly sampled to the output node N 3 at time t 4 when the transistor T 4 enters the on state. Meanwhile, the total electrical capacitance of the internal node 1 is much larger than the total electrical capacitance of the output node N 3 , so that it is possible to ignore a decrease in the pixel voltage V 20 due to the sampling.
  • the voltage of the first control line SWL is changed from a first switch voltage (8 V) to a second switch voltage ( ⁇ 5 V), the transistor T 4 is set to the off state, the output node N 3 and the internal node N 1 are electrically separated, and the pixel voltage V 20 of the internal node N 1 is held in the output node N 3 .
  • the voltage Vn 3 of the output node N 3 is stepped down to the pixel voltage V 20 and change from a second boost voltage of the second control line BST to a first boost voltage takes place prior to change from the second switch voltage ( ⁇ 5 V) of the first control line SWL to the first switch voltage (8 V), so that the period of t 3 to t 4 can be set in a short time. Further, it is only sufficient to compensate for a decrease in the voltage of the output node N 3 , so that a sampling period at time t 4 to t 5 can be set in a short time.
  • the transistor T 4 enters the off state, so that the holding period of time t 5 to t 6 can be set in a short time according to response characteristics of the transistor T 4 . Consequently, when respective periods are set in short times in a period of t 3 to t 4 and a holding period of time t 5 to t 6 , it is not necessary to purposely change the voltage of an auxiliary gate line from a selected row voltage 8 V to an unselected row voltage ⁇ 5 V.
  • the voltage of the auxiliary gate line AGL is maintained at the selected row voltage 8V through the phase C (t 2 to t 3 ) and the phase D (t 3 to t 6 ).
  • the voltage of the auxiliary gate line AGL may be changed from the selected row voltage 8 V to the unselected row voltage ⁇ 5 V as in the phase D according to the third embodiment, and the transistor T 2 may be set to the off state.
  • the self-refresh main operation differs from the self-refresh main operation in the phase C (t 2 to t 3 ) in that, when the holding period of time t 5 to t 6 is short, the voltage of the auxiliary gate line AGL is maintained at the selected row voltage 8 V, and therefore an operation of changing the voltage from the unselected voltage ⁇ 5 V to the selected voltage 8 V is not accompanied.
  • the self-refresh main operation is the same as the self-refresh main operation in the phase C (t 2 to t 3 ) when the voltage of the auxiliary gate line AGL is changed from the selected row voltage 8V to the unselected row voltage ⁇ 5 V in the holding period of time t 5 to t 6 . Subsequently, until the next writing operation is started, the self-refresh main operation in the phase C and the operation in the phase D are repeatedly executed in order.
  • Embodiments have been described in the second to fourth embodiments where a writing operation and a self-refresh operation are performed targeting all the pixel circuits 2 of one frame, and the self-refresh operation for one frame is collectively performed at the same time after the writing operation for one frame is finished.
  • the writing operation is executed in time division by dividing pixel data of one frame with respect to each display line in the horizontal direction (row direction) as described in the second embodiment, and applying a pixel data voltage corresponding to each pixel data of one display line to the source line SL in each column for each horizontal period.
  • a substantial timing to finish the writing operation varies among the display lines in respective rows, and therefore variation is produced in a time width of a stand-by period between an end of the writing operation and start of the self-refresh operation.
  • the pixel data voltage is applied to the source line SL for the subsequent writing operation, and therefore a state where the voltage different from the written pixel data voltage is applied to a first terminal of a transistor T 1 is likely to continue through the stand-by period in pixel circuits in a row in which the writing operation is finished.
  • the self-refresh operation is started independently for each display line in each row immediately after the writing operation in each row is finished.
  • a voltage supply line VSL does not necessarily need to be independently controlled with respect to each row.
  • FIGS. 10 and 11 illustrate timing diagrams of the writing operation and the self-refresh operation with respect to each row in the constant display mode when a first type pixel circuit is used.
  • FIG. 10 illustrates that a refresh canceling operation (holding operation) described in the third embodiment is executed in a phase D after the self-refresh main operation in a phase C
  • FIG. 11 illustrates that the refresh canceling operation (holding operation) described in the fourth embodiment is executed in the phase D after the self-refresh main operation in the phase C.
  • FIGS. 10 illustrates that a refresh canceling operation (holding operation) described in the third embodiment is executed in a phase D after the self-refresh main operation in a phase C
  • FIG. 11 illustrates that the refresh canceling operation (holding operation) described in the fourth embodiment is executed in the phase D after the self-refresh main operation in the phase C.
  • 10 and 11 illustrate each voltage waveform of two gate lines GL 1 and GL 2 , two auxiliary gate lines AGL 1 and AGL 2 , two source lines SL 1 and SL 2 , two first control lines SWL 1 and SWL 2 , two second control lines BST 1 and BST 2 , the voltage supply line VSL and the auxiliary capacity line CSL, and the voltage waveform of the counter voltage Vcom in one frame period.
  • the gate line GL 1 , the auxiliary gate line AGL 1 , the first control line SWL 1 , and the second control line BST 1 are connected to the pixel circuits 2 in the same row for which the writing operation is performed in the first horizontal period.
  • the gate line GL 2 , the auxiliary gate line AGL 2 , the first control line SWL 2 , and the second control line BST 2 are connected to the pixel circuits 2 in the same row for which the writing operation is performed in the second horizontal period.
  • the auxiliary gate line AGL 1 , the first control line SWL 1 , and the second control line BST 1 are used to perform the self-refresh operation for pixel circuits in the first row serving as writing operation targets in the first horizontal period, subsequently to the second horizontal period
  • the auxiliary gate line AGL 2 , the first control line SWL 2 , and the second control line BST 2 are used to perform the self-refresh operation for pixel circuits in the second rows serving as writing operation targets in the second horizontal period, subsequently to the third horizontal period.
  • the writing operation differs from the writing operation described in the second embodiment only in voltage applying conditions of the first control line SWL and the second control line BST with respect to pixel circuits in unselected rows for which the writing operation is finished, and the writing operation for selected rows is completely the same as the writing operation described in the second embodiment. Further, the voltage applying conditions for unselected rows before the writing operation is also the same as the writing operation described in the second embodiment.
  • the self-refresh operation during the writing operation for one frame differs from the self-refresh operation after the writing operation in that a pixel data voltage to be written in pixel circuits serving as writing operation targets instead of a first reset voltage is applied to the source line SL.
  • the self-refresh operations are the same in that the three basic phases (phases A to C) described in the third embodiment are executed by applying the voltage to the first control line SWL and the second control line BST.
  • the first rest voltage is applied to each source line SL after the writing operation for one frame is finished.
  • a predetermined fixed voltage (0 V in FIGS. 10 and 11 ) is applied to the auxiliary capacity line CSL
  • the first control voltage (5 V) is applied to a voltage supply line CSL/VSL functioning as the voltage supply line VSL and the auxiliary capacity line CSL.
  • timing control of the auxiliary gate line AGL, the first control line SWL, and the second control line BST may be changed such that the self-refresh operation is collectively performed at the same time for the pixel circuits 2 of one frame similar to the self-refresh operation according to the third and fourth embodiments after the writing operation for one frame is finished. Further, an operation of repeating the phase C and the phase D subsequent to the first phase D and the second phase C in the phase C and the phase D may be performed after the writing operation for one frame is finished.
  • the self-refresh operation executed after the writing operation for one frame continues for pixel circuits in rows for which the writing operation is not performed during the writing operation period of one frame illustrated in FIGS. 10 and 11 .
  • voltage application control is collectively performed for the first control line SWL and the second control line BST in all unselected rows for which the writing operation is not performed.
  • pixel data of one frame is divided with respect to each display line in a horizontal direction (row direction), an analog voltage of multiple tones corresponding to each pixel data of one display line is applied to the source line SL in each column for each horizontal period, a selected row voltage 8 V is applied to a gate line GL and an auxiliary gate line AGL of the selected display line (selected row), first switch circuits 22 of all pixel circuits 2 in the selected row are set to the conducted state, and the voltage of the source line SL in each column is transferred to an internal node N 1 of each pixel circuit 2 in the selected row.
  • An unselected row voltage ⁇ 5 V is applied to the gate line GL other than the selected display line (unselected row) to set the first switch circuits 22 of all pixel circuits 2 in the selected row to the non-conducted state.
  • the display control circuit 11 illustrated in FIG. 1 controls a timing of applying the voltage to each signal line upon the writing operation described below, and the display control circuit 11 , the counter electrode drive circuit 12 , the source driver 13 , and the gate driver 14 individually apply voltages.
  • FIG. 12 illustrates a timing diagram of the writing operation in the normal display mode when a first type pixel circuit is used.
  • FIG. 12 illustrates each voltage waveform of two gate lines GL 1 and GL 2 , two auxiliary gate lines AGL 1 and AGL 2 , two source lines SL 1 and SL 2 , a first control line SWL, a second control line BST, a voltage supply line VSL and an auxiliary capacity line CSL, and the voltage waveform of the counter voltage Vcom in one frame period.
  • One frame period is divided into horizontal periods the number of which corresponds to the number of gate lines GL, and the gate lines GL 1 to GLn to be selected are sequentially allocated to the respective horizontal periods.
  • FIG. 12 illustrates voltage changes in two gate lines GL 1 and GL 2 and auxiliary gate lines AGL 1 and AGL 2 in the first two horizontal periods.
  • the selected row voltage 8V is applied to the gate line GL 1 and the auxiliary gate line AGL 1 and the unselected row voltage ⁇ 5 V is applied to the gate line GL 2 and the auxiliary gate line AGL 2 in the first horizontal period
  • the selected row voltage 8 V is applied to the gate line GL 2 and the auxiliary gate line AGL 2 and the unselected row voltage ⁇ 5 V is applied to the gate line GL 1 and the auxiliary gate line AGL 1 in the second horizontal period
  • the unselected row voltage ⁇ 5 V is applied to the gate lines GL 1 and GL 2 and the auxiliary gate lines AGL 1 and AGL 2 in subsequent horizontal periods, respectively.
  • An analog voltage of multiple tones are displayed by a cross hatching in FIG.
  • an analog voltage to be applied to the source line SL is set such that a liquid crystal voltage Vlc given from a difference voltage (V 20 -Vcom) between the counter voltage Vcom and the pixel voltage V 20 has different voltage polarities, but takes the same absolute value corresponding to each pixel data between when the counter voltage Vcom is 5V and when the counter voltage Vcom is 0V.
  • a first switch circuit 22 consists of a series circuit of a transistor T 1 and a transistor T 2 , and conduction/non-conduction of the first switch circuit 22 is controlled by performing on/off control of the transistor T 1 and the transistor T 2 similar to the writing operation in a constant display mode. Further, similar to the writing operation in the constant display mode, it is necessary to set a second switch circuit 23 to a non-conducted state to prevent interference from the voltage supply line VSL in the writing operation, and therefore a first control voltage (5 V in the present embodiment) equal to or more than the maximum voltage of a pixel data voltage (tone voltage) held in an internal node N 1 through one frame period is applied to the voltage supply line VSL.
  • first switch voltage which is higher than the first control voltage (5 V) by a threshold voltage (about 2 V) or more is applied to the first control line SWL to set a transistor T 4 to the on state at all times irrespectively of the voltage state of the internal node N 1 during one frame period.
  • the output node N 3 and the internal node N 1 are electrically connected with each other, and the output node N 3 and the intermediate node N 2 have the same potential.
  • the second control line BST is fixed to a predetermined fixed voltage (for example, 0 V: first boost voltage).
  • the counter voltage Vcom is counter-AC-driven for each horizontal period, and the auxiliary capacity line CSL is driven to have the same potential as the counter voltage Vcom.
  • a pixel electrode 20 capacitive-couples to a counter electrode 30 through a liquid crystal layer and also capacitive-couples to the auxiliary capacity line CSL through the auxiliary capacitative element C 2 , and therefore, when the voltage on the auxiliary capacity line CSL side of the auxiliary capacitative element C 2 is fixed, the change of the counter voltage Vcom is distributed between the auxiliary capacity line CSL and the auxiliary capacitative element C 2 and appears in the pixel electrode 20 , and the liquid crystal voltage Vlc of the pixel circuits 2 in unselected rows fluctuates.
  • a method of inverting the polarity of each display line for each horizontal period includes a method of applying a predetermined fixed voltage to the counter voltage 30 as the counter voltage Vcom in addition to above “counter AC driving”. In this case, the voltage applied to the pixel voltage 20 is switched for each horizontal period between a positive voltage and a negative voltage based on the counter voltage Vcom.
  • auxiliary capacity lines CSL are individually pulse-driven with respect to each row without being driven at the same voltage as the counter voltage Vcom.
  • a method of inverting the polarity of each display line for each horizontal line in the writing operation in the normal display mode is employed in the sixth embodiment to overcome the following inconvenience which occurs when the polarity is inverted for each frame.
  • the method of overcoming this inconvenience includes a method of inverting the polarity and performing driving for each column and a method of inverting the polarity and performing driving for each pixel in row and column directions at the same time.
  • the normal display mode is a mode for displaying such a high quality still image or movie, and therefore the above minute change is likely to be visually recognized.
  • the polarity is inverted for each display line in the same frame in the present embodiment.
  • the liquid crystal voltages Vlc of different polarities between display lines in the same frame are applied, so that it is possible to prevent an influence on display image data based on the polarity of the liquid crystal voltage Vlc.
  • the voltage supply line VSL and the auxiliary capacity line CSL are independently controlled for counter AC driving and the polarity is inverted for each display line. Therefore, the writing operation in the normal display mode cannot be applied when a second type pixel circuit illustrated in FIG. 6 is used.
  • the transistor T 3 by connecting to the transistor T 3 in series another transistor element which is turned off upon the writing operation and is turned on upon the self-refresh operation in the second switch circuit 23 employing the circuit configuration illustrated in FIG. 6 , it is possible to give the same voltage change as the counter voltage Vcom to the voltage supply line CSL/VSL.
  • a first switch voltage (8V) is applied to a first control line SWL, the potential is made to the same between an output node N 3 and an internal node N 1 and a second switch circuit 23 is set to the non-conducted state by applying a first control voltage (5 V) to a voltage supply line VSL. Therefore, when the second switch circuit 23 is consists of not only a transistor T 3 but also a series circuit of the transistor T 3 and another control transistor, it is possible to set the second switch circuit 23 to the non-conducted state upon the writing operation by directly performing on/off control of the control transistor. Consequently, it is not always necessary to perform control of applying the first switch voltage (8 V) to the first control line SWL and applying the first control voltage (5 V) to the voltage supply line VSL.
  • one frame may be divided into a plurality of row groups each including a predetermined number of rows, and the self-refresh operation may be executed with respect to each row group.
  • one frame is divided into a group of four rows and every time the writing operation is finished for each group of four rows, the self-refresh operation may be collectively performed at the same time for pixel circuits in the group of the four rows. Consequently, it is possible to reduce the number of signal lines related to independent timing control, and simplify control.
  • all pixel circuits 2 formed on the active matrix substrate 10 employ a configuration having the second switch circuit 23 and a control circuit 24 .
  • the transmissive pixel unit displays an image in the normal display mode
  • the reflective pixel unit displays an image in the constant display mode. According to this configuration, it is possible to reduce the number of elements formed on an entire active matrix substrate 10 .
  • each pixel circuit 2 employs a configuration having the capacitative element C 2 in the above embodiments, each pixel circuit 2 may employ a configuration without the auxiliary capacitative element C 2 . In this case, the auxiliary capacity line CSL is not required, and the first type pixel circuit 2 and the second type pixel circuit 2 employ the same configuration.
  • the display element unit 21 may employ a configuration having an analog amplifier 40 (voltage amplifier) between the internal node N 1 and the pixel electrode 20 as illustrated in FIG. 13 .
  • FIG. 13 illustrates, for example, configuration where an auxiliary capacity line CSL and a power source line Vcc are inputted as power source lines for the analog amplifier 40 .
  • the voltage given to the internal node N 1 is amplified by an amplification factor ⁇ set by the analog amplifier 40 , and the amplified voltage is supplied to the pixel electrode 20 . Consequently, this configuration can reflect a minute voltage change of the internal node N 1 in a display image.
  • transistors T 1 to T 4 in the pixel circuit 2 are assumed to be N channel type polysilicon TFT in the above embodiments, it may be possible to employ a configuration using P channel type TFTs or employ a configuration using amorphous silicon TFTs.
  • a display device employing the configuration using the P channel type TFTs can also operate the pixel circuits 2 similar to each of the above embodiments by processing of, for example, inverting positive and negative values of a power voltage and a voltage value shown as the above operation conditions, providing the same effect.

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