US8749420B2 - A/D converter, A/D conversion method, and program - Google Patents
A/D converter, A/D conversion method, and program Download PDFInfo
- Publication number
- US8749420B2 US8749420B2 US13/398,994 US201213398994A US8749420B2 US 8749420 B2 US8749420 B2 US 8749420B2 US 201213398994 A US201213398994 A US 201213398994A US 8749420 B2 US8749420 B2 US 8749420B2
- Authority
- US
- United States
- Prior art keywords
- resolution
- bits
- clock signal
- stopped
- decode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 238000006243 chemical reaction Methods 0.000 title claims description 46
- 238000000034 method Methods 0.000 title claims description 12
- 230000004044 response Effects 0.000 claims description 22
- 230000008859 change Effects 0.000 claims description 10
- 238000013139 quantization Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 description 80
- 238000010586 diagram Methods 0.000 description 44
- 230000002829 reductive effect Effects 0.000 description 24
- 230000006866 deterioration Effects 0.000 description 19
- 230000006870 function Effects 0.000 description 18
- 230000009467 reduction Effects 0.000 description 9
- 230000000875 corresponding effect Effects 0.000 description 7
- 238000004891 communication Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 238000013441 quality evaluation Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/004—Reconfigurable analogue/digital or digital/analogue converters
- H03M1/007—Reconfigurable analogue/digital or digital/analogue converters among different resolutions
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/56—Input signal compared with linear ramp
Definitions
- the present disclosure relates to an A/D converter, an A/D conversion method, and a program, and specifically relates to an A/D converter, an A/D conversion method, and a program that can reduce power consumption.
- FIG. 1 shows a typical circuit example having a comparator and a counter.
- FIG. 2 is a timing chart of the circuit in FIG. 1 .
- sweeping of the reference voltage Vramp is started in the comparator 1 and the count operation of the counter 2 is started at the same time.
- the output signal VCO of the comparator 1 is inverted from the high level to the low level.
- the count operation of the counter 2 is stopped.
- the count value VCNT has a one-on-one relationship with the voltage width swept by the reference voltage Vramp, and the count value VCNT is a result of analog-digital (AD) conversion of the input voltage.
- AD analog-digital
- the ripple counters are used as the counters, and subtraction is realized by inversion of the respective bits of the ripple counters. Further, the addition operation is realized by holding the count value of the first data and continuously operating the ripple counter for the next data.
- the CDS (Correlated Double Sampling) operation which is often performed in an image sensor, is independently performed with respect to each column, and thus, the AD conversion results of the pixel outputs do not depend on the clock signals between the columns and the skew of the reference potential. As a result, the count operation can be performed using the faster clock signals. Further, addition and subtraction of the AD conversion results with respect to each column can be performed, and thus, there is an advantage that the addition operation of the pixel outputs within the same column may be performed on the AD conversion circuits.
- An A/D converter switches resolution of m bits to resolution of n bits smaller than the m bits at a predetermined time.
- the resolution may be switched to the resolution of n bits by partially stopping clock signals having plural phase differences to be supplied at the resolution of m bits at the predetermined time.
- At least one clock signal of the clock signals to be stopped may be stopped under a condition that a logical value is “1”.
- Lower bits according to the clock signal may be decoded in response to predetermined output within a ripple counter that counts upper bits.
- the resolution may be switched to the resolution of n bits by partially stopping gray code counters to be supplied at the resolution of m bits at the predetermined time.
- At least one gray code of the gray codes to be stopped may be stopped under a condition that a logical value is “1”.
- the predetermined time may be a time into a white region.
- the predetermined time may be a time into a region in which a change of 1 LSB is buried in noise.
- the A/D converter may include a comparison unit that compares a reference voltage having a ramp waveform with a voltage value linearly changing with time to an input voltage, an upper bit counter that starts operation or stops operation with inversion of an output of the comparison unit as a trigger, and performing count with respect to each period of the clock signal, and a time quantization unit that outputs lower bits with the higher resolution than the period of the clock signal by latching phase information at a time when the output of a comparator is inverted using plural clock signals at different phases and decoding the value.
- the A/D converter may include a comparison unit that compares a reference voltage having a ramp waveform with a voltage value linearly changing with time to an input voltage, an upper bit counter that starts operation or stops operation with inversion of an output of the comparator as a trigger, and performing count with respect to each period of the clock signals, and a lower bit counter that outputs lower bits by latching gray codes generated by the gray code counters from the clock signals and decoding the values.
- a plurality of the A/D converters may be provided in an image sensor and the same control signals may be supplied thereto.
- An A/D conversion method includes switching resolution of m bits to resolution of n bits smaller than the m bits at a predetermined time.
- a program according to still another embodiment of the present disclosure is a computer-readable program for allowing a computer that controls an A/D converter for converting an analog signal into a digital signal to switch resolution of m bits to resolution of n bits smaller than the m bits at a predetermined time.
- the resolution of m bits is switched to the resolution of n bits smaller than m bits at the predetermined time.
- appropriate necessary resolution may be controlled. Further, by controlling the resolution, power consumption can be reduced.
- FIG. 1 is a diagram for explanation of a circuit having a comparator and a counter.
- FIG. 2 is a diagram for explanation of an operation of the circuit having the comparator and the counter.
- FIG. 3 shows a circuit having a latch, a decode, and a ripple counter.
- FIG. 4 shows details of the circuit shown in FIG. 3 .
- FIG. 5 is a diagram for explanation of an operation of the circuit shown in FIG. 4 .
- FIG. 6 is a diagram for explanation of the decode.
- FIG. 7 is a diagram for explanation of decode values.
- FIG. 8 is a diagram for explanation of a region in which stopping of clocks is executed.
- FIG. 9 is a diagram for explanation of the region in which stopping of clocks is executed.
- FIG. 10 is a diagram for explanation of an operation of the circuit shown in FIG. 4 .
- FIG. 11 is a diagram for explanation of decode.
- FIG. 12 is a diagram for explanation of decode values.
- FIG. 13 is a diagram for explanation of an operation of the circuit shown in FIG. 4 .
- FIG. 14 is a diagram for explanation of decode.
- FIG. 15 is a diagram for explanation of a decode value.
- FIG. 16 is a diagram for explanation of switching among operation modes.
- FIGS. 17A to 17C are diagrams for explanation of operations in the respective operation modes.
- FIG. 18 is a block diagram showing a configuration example of a column parallel ADC-mounted solid-state image sensing device.
- FIG. 19 is a diagram for explanation of an operation of the circuit shown in FIG. 4 .
- FIG. 20 is a diagram for explanation of linearity.
- FIG. 21 is a diagram for explanation of linearity.
- FIG. 22 is a diagram for explanation of an operation of the circuit shown in FIG. 4 .
- FIG. 23 is a diagram for explanation of linearity.
- FIG. 24 is a diagram for explanation of loss of monotonic increasing characteristics.
- FIG. 25 is a diagram for explanation of switching among operation modes.
- FIG. 26 is a diagram for explanation of an operation of the circuit shown in FIG. 4 .
- FIG. 27 is a diagram for explanation of linearity.
- FIG. 28 is a diagram for explanation of errors.
- FIG. 29 is a diagram for explanation of an operation of the circuit shown in FIG. 4 .
- FIG. 30 is a diagram for explanation of linearity.
- FIG. 31 is a diagram for explanation of errors.
- FIG. 32 is a diagram for explanation of an improvement of monotonic increasing characteristics.
- FIG. 33 is a diagram for explanation of an operation of the circuit shown in FIG. 3 .
- FIG. 34 is a diagram for explanation of switching among operation modes.
- FIG. 35 shows details of the circuit that performs the operation shown in FIG. 33 .
- FIGS. 36A to 36C are diagrams for explanation of operations of the circuit shown in FIG. 35 .
- FIG. 37 shows other details of the circuit shown in FIG. 3 .
- FIG. 38 shows details of the circuit shown in FIG. 37 .
- FIG. 39 is a diagram for explanation of an operation of the circuit shown in FIG. 37 .
- FIG. 40 is a diagram for explanation of switching among operation modes.
- FIG. 41 is a diagram for explanation of decode.
- FIG. 42 is a diagram for explanation of linearity.
- FIG. 43 is a diagram for explanation of linearity.
- FIG. 44 is a diagram for explanation of switching among operation modes.
- FIG. 45 is a diagram for explanation of errors.
- FIG. 46 is a diagram for explanation of linearity.
- FIG. 47 is a diagram for explanation of a recording medium.
- FIG. 3 shows a configuration of one embodiment of an A/D converter (Analog Digital Converter).
- the A/D converter 20 has a reference voltage supply unit 21 , a comparator 22 , a latch-decode circuit 23 , and a ripple counter 24 .
- the latch-decode circuit 23 includes a latch circuit and a decode circuit.
- the A/D converter 20 shown in FIG. 3 is an integrating A/D converter 20 that obtains information of the lower bits by an upper bit counter and a TDC (Time to Digital Converter) that latches and decodes clock signals at different phases.
- the A/D converter 20 having resolution of 14 bits including a ripple counter of the upper 11 bits and the TDC of the lower 3 bits is shown.
- the comparator 22 compares a reference voltage Vramp having a ramp waveform with a voltage value linearly changing with time supplied from the reference voltage supply unit 21 to an input voltage VSL, and outputs an output signal VCO at the level in response to the result to the latch-decode circuit 23 and the ripple counter 24 .
- the upper bits of the ripple counter 24 stop counting and the latch-decode circuit 23 latches phase information of the clock signals CLK and outputs latch data EB (extension code EB).
- a clock signal CLKA, a clock signal CLKB, a clock signal CLKC, a clock signal CLKD at different phases by 45 degrees are supplied to the latch-decode circuit 23 , and the phase information is latched by the respective clock signals.
- clock signals are supplied from a supply unit (not shown), and the clock signals supplied from the supply unit are supplied to the latch-decode circuit 23 under control of a control unit (not shown). As will be described later, supply of the clock signals is stopped when a predetermined region (for example, a white region) is determined, and the determination is performed by the control unit.
- a predetermined region for example, a white region
- the latch-decode circuit 23 converts latch information into pulse (train) and the pulse is output as a count clock signal of the ripple counter 24 .
- the ripple counter 24 converts the phase information of the clock signals into binary codes as the least significant bit of the ripple counter in response to the count clock signal of the latch-decode circuit 23 .
- FIG. 4 shows the detailed configuration of the latch-decode circuit 23 of the A/D converter 20 shown in FIG. 3 .
- the latch-decode circuit 23 shown in FIG. 4 is a circuit of converting the extension codes into binary values.
- the latch-decode circuit 23 shown in FIG. 4 includes a latch circuit 41 and a decode circuit 51 , and the latch circuit 41 includes flip-flops 42 to 45 .
- the decode circuit 51 has a selector 52 , a first decode circuit 53 , a first ripple counter part 54 , a mask circuit 55 , a second decode circuit 56 , a second ripple counter part 57 .
- the comparator 22 compares the reference voltage Vramp having the ramp waveform with the voltage value linearly changing with time to the input voltage VSL, and outputs the output signals VCO at the levels in response to the results to the respective flip-flops 42 to 45 of the latch circuit 41 .
- the latch circuit 41 has the flip-flops 42 , 43 , 44 as a first latch and the flip-flop 46 as a second latch.
- the latch circuit 41 latches the phase information at the time when the output signal VCO of the comparator 22 is inverted using the plural clock signals at different phases.
- the four clock signals including the clock signal CLKB, the clock signal CLKC, the clock signal CLKD at phases sequentially shifted by 45 degrees with reference to the clock signal CLKA, and the clock signal CLKA itself are used as the plural clock signals at different phases.
- the phase shift of 45 degrees corresponds to 1/8 of a clock signal period Tck.
- the respective flip-flops 42 to 45 latch the phase information of the clock signal CLKA, the clock signal CLKB, the clock signal CLKC, and the clock signal CLKD in synchronization with the output signals VCO of the comparator 22 .
- the flip-flop 42 latches the clock signal CLKD in synchronization with the output signal VCO of the comparator 22 .
- the extension code EB[ 0 ] is obtained from Q-output of the flip-flop 42 , and the flip-flop 42 outputs the obtained extension code EB[ 0 ] to the selector 52 .
- the flip-flop 43 latches the phase information of the clock signal CLKC in synchronization with the output signal VCO of the comparator 22 .
- the extension code EB[ 1 ] is obtained from Q-output of the flip-flop 43 , and the flip-flop 43 outputs the obtained extension code EB[ 1 ] to the selector 52 .
- the flip-flop 44 latches the phase information of the clock signal CLKB in synchronization with the output signal VCO of the comparator 22 .
- the extension code EB[ 2 ] is obtained from Q-output of the flip-flop 44 , and the flip-flop 44 outputs the obtained extension code EB[ 2 ] to the selector 52 .
- the flip-flop 45 latches the phase information of the clock signal CLKA in synchronization with the output signal VCO of the comparator 22 .
- the extension code EB[ 3 ] is obtained from Q-output of the flip-flop 45 , and the flip-flop 45 outputs the obtained extension code EB[ 3 ] to the first decode circuit 53 and the mask circuit 55 .
- the selector 52 sequentially selects the extension code EB[ 0 ], the extension code EB[ 1 ], the extension code EB[ 2 ] output from the flip-flops 42 to 44 in response to selector signals EBSEL[2:0], and outputs them as signals EBO to the first decode circuit 53 .
- the first decode circuit 53 converts the extension codes EB[ 0 ] to EB[ 2 ] as latch information of the latch circuit 41 into pulse (train) in response to a pulse signal EBCK and the extension code EB[ 3 ], and outputs the pulse signal EBCKO as a count clock signal of the first ripple counter part 54 .
- the first decode circuit 53 has an AND-OR circuit 61 including two AND circuits and one OR circuit.
- the first input terminal of the first three-input AND circuit of the AND-OR circuit 61 is connected to the supply line of the pulse signal EBCK.
- the second negative input terminal of the first three-input AND circuit is connected to the output line of the extension code EB[ 3 ], and the third negative input terminal is connected to the supply line of the signal EBO of the selector 52 .
- the first input terminal of the second three-input AND circuit of the AND-OR circuit 61 is connected to the supply line of the pulse signal EBCK.
- the second input terminal of the second three-input AND circuit is connected to the output line of the extension code EB[ 3 ], and the third input terminal is connected to the supply line of the signal EBO of the selector 52 .
- the outputs from the first three-input AND circuit and the second three-input AND circuit are respectively supplied to the OR circuit. Further, the output from the OR circuit is supplied to the first ripple counter part 54 .
- the first ripple counter part 54 converts the phase information of the clock signals into binary codes as lower bits in response to the count clock signal of the first decode circuit 53 .
- the first ripple counter part 54 has cascade-connected flip-flop 62 and flip-flop 63 as memory devices.
- the terminal CIN of the flip-flop 62 is connected to the supply line of the pulse signal EBCKO of the first decode circuit 53 , the input D is connected to the inverted output/Q (“/” indicates inversion), and the output Q is connected to the terminal CIN of the flip-flop 63 .
- the D-input of the flip-flop 63 is connected to the inverted output/Q and the output Q is connected to the second decode circuit 56 .
- the mask circuit 55 performs mask processing of determining whether the extension code EB[ 3 ] by the latch circuit 41 is input or not to the second decode circuit 56 in response to a mask signal XEBMSK and processing it.
- the mask circuit 55 includes a negative two-input AND circuit. The first negative input terminal of the AND circuit of the mask circuit 55 is connected to the supply line of the extension code EB[ 3 ] of the latch circuit 41 , and the second negative input terminal is connected to the supply line of the mask signal XEBMSK at the low active level.
- the second decode circuit 56 converts the extension code EB[ 3 ] of the latch circuit 41 into pulse (train) in response to a pulse signal EB 4 CK, and outputs the signal Q[ 2 ] as the count clock signal of the second ripple counter part 57 .
- the second decode circuit 56 has an AND-OR circuit 64 including two AND circuits and one OR circuit.
- the first input terminal of the first two-input AND circuit of the AND-OR circuit 64 is connected to the supply line of the pulse signal EB 4 CK, and the second input terminal is connected to the output terminal of the mask circuit 55 .
- the first negative input terminal of the second two-input AND circuit of the AND-OR circuit 64 is connected to the output terminal of the mask circuit and the second input terminal is connected to the output line of the output Q[ 1 ] of the first ripple counter part 54 .
- the output of the first two-input AND circuit and the output of the second AND circuit are supplied to the OR circuit, and the output signal Q[ 2 ] from the OR circuit is supplied to the second ripple counter part 57 .
- the second ripple counter part 57 converts the phase information of the clock signals into binary codes as higher bits of the ripple counter in response to the count clock signal of the second decode circuit 56 .
- the second ripple counter part 57 has a flip-flop 57 and a ripple counter 24 ( FIG. 3 ).
- the input D of the flip-flop 57 is connected to the inverted output/Q (“/” indicates inversion), the terminal CIN is connected to the supply line of the output signal Q[ 2 ] of the second decode circuit 56 , and the output Q is connected to the input terminal of the ripple counter 24 ( FIG. 3 ).
- the flip-flop 57 functions as a memory device (latch) after binary conversion.
- FIG. 5 shows a timing chart for explanation of an operation of the A/D converter 20 in FIG. 4
- FIG. 6 shows an algorithm for conversion of extension codes into binary values
- FIG. 7 shows an example of decoding results of the extension codes EB[3:0] into binary values.
- FIG. 5 shows the case of the four clock signals at phases shifted by 1/8 Tck (Tck is a clock signal period).
- Tck is a clock signal period.
- the period of the clock signal is equally divided into eight by the combinations of 0/1 of the four clock signals CLKA to CLKD.
- the clock signals CLK[3:0] 1000b
- the clock signals CLK[3:0] 1100b, . . . .
- information of 3b in binary codes may be obtained.
- the clock signals CLK[3:0] are latched and the latch data is the extension codes EB[3:0].
- the first period from 0 to 1/8 Tck of the clock signal is converted into “0”
- the period from 1/8 Tck to 2/8 Tck is converted into “1”
- the periods are converted into count values of 2, 3, 4, . . . , the pulses in the numbers having the correspondence relationships as shown in FIG. 7 are generated.
- the algorithm with reference to FIG. 7 , if the extension codes EB[ 3 ], EB[ 2 ], EB[ 1 ], EB[ 0 ] are “1, 0, 0, 0”, the binary code is “000” and the decode value is “0”.
- the extension codes EB[ 3 ], EB[ 2 ], EB[ 1 ], EB[ 0 ] are “1, 1, 0, 0”
- the binary code is “001” and the decode value is “1”.
- extension codes EB[ 3 ], EB[ 2 ], EB[ 1 ], EB[ 0 ] are “1, 1, 1, 0”
- the binary code is “010” and the decode value is “2”.
- the extension codes EB[ 3 ], EB[ 2 ], EB[ 1 ], EB[ 0 ] are “1, 1, 1, 1”
- the binary code is “011” and the decode value is “3”.
- the extension codes EB[ 3 ], EB[ 2 ], EB[ 1 ], EB[ 0 ] are “0, 1, 1, 1”
- the binary code is “100” and the decode value is “4”.
- extension codes EB[ 3 ], EB[ 2 ], EB[ 1 ], EB[ 0 ] are “0, 0, 1, 1”
- the binary code is “101” and the decode value is “5”.
- the extension codes EB[ 3 ], EB[ 2 ],EB[ 1 ], EB[ 0 ] are “0, 0, 0, 1”
- the binary code is “110” and the decode value is “6”.
- the extension codes EB[ 3 ], EB[ 2 ], EB[ 1 ], EB[ 0 ] are “0, 0, 0, 0”
- the binary code is “111” and the decode value is “7”. In this manner, the extension codes are converted into the decode values.
- A/D converter circuit 20 Since the A/D converter circuit 20 operates in the above described manner, A/D conversion with improved resolution using extension codes can be performed. For example, according to a digital camera including the A/D converter circuit 20 , improvements in image quality because of higher resolution may be expected. That is, as the resolution is higher, the quality of data in the device including the A/D converter circuit 20 , for example, image quality or sound quality can be improved.
- the A/D converter circuit in the embodiment is applied to devices that handle images and videos such as a digital camera will be exemplified, and processing for reducing power consumption without deterioration of image quality will be explained.
- the four clock signals are input to the latch-decode circuit 23 .
- the power consumption may be reduced.
- the resolution becomes lower. Accordingly, conditions having little (negligible) influence even when the clock signals are stopped and the resolution becomes lower will be explained.
- FIG. 8 is a graph showing relations between illuminance of light entering an image sensor and the number of electrons generated within the pixels of the image sensor.
- the circuit noise as a fixed component is dominating and the signal component proportional to the amount of light is smaller.
- the light shot noise proportional to the square of the illuminance is dominating.
- N ( Q ) 2 ( E ⁇ square root over (Q) ⁇ ) 2 +Nc 2 (3)
- N ( Q ) ⁇ square root over ( E 2 Q+Nc 2 ) ⁇ (4)
- the graph in FIG. 9 is a graph showing relations with the number of photoelectrons Q [ ⁇ e] on the horizontal axis and the total amount of noise N [V rms ] on the vertical axis.
- the Q FD [ ⁇ e] is saturated capacity of the pixel.
- the dynamic range of the image sensor is D RANGE [V] and the resolution of the A/D converter is n [bit].
- the weight of 1 LSB (least significant bit), i.e., the voltage width changing by the 1 LSB is expressed by the following equation (5). Voltage Width D RANGE /2 n (5)
- FIG. 9 shows a curve of the total amount of noise N and a curve of a half of the total amount of noise (1/2)N.
- the voltage width D RANGE /2 n of 1 LSB is smaller than the half of the total amount of noise N/2, the change of 1 LSB is buried in the noise, and the resolution of n [bit] of the A/D converter may not necessarily be required in the region (for example, the white region). In the region in which the resolution is buried in the noise, it is not necessary to maintain the resolution for maintenance of image quality and the resolution may be n bits or less.
- the A/D converter circuit 20 raises the resolution by inputting the four clock signals to the latch-decode circuit 23 and processing them to create the lower three bits, and the power consumption of the A/D converter circuit 20 may be reduced by stopping the clock signals in a range that does not affect the image quality.
- the lower power consumption of the entire A/D converter 20 is realized by focusing attention on a region where the highest resolution of the A/D converter 20 is not necessary in the part with high illuminance, for example, in the white region, and reducing the resolution of the A/D converter 20 in the region.
- the condition that the resolution is buried in the noise is not limited to the above described condition because it is determined through an image quality evaluation or the like. That is, in the above described example, the condition that the voltage width D RANGE /2 n of 1 LSB is smaller than the half of the total amount of noise N/2 is set, however, not only the half of the total amount of noise but also other values such as a third or fifth of the total amount may be used.
- the decode value when the clock signal input to the latch-decode circuit 23 is stopped in the A/D converter circuit 20 will be explained.
- the decode values when the clock signals are not stopped i.e., in the operation mode of operation as a 3-bit TDC in which three binary codes are obtained has been explained.
- decode values when two clock signals are stopped in an operation mode of operation as a 2-bit TDC in which two binary codes are obtained and decode values when three clock signals are stopped in an operation mode of operation as a 1-bit TDC in which one binary code is obtained will respectively be explained.
- FIG. 10 is a timing chart for explanation of an operation of the A/D converter 20 in FIG. 4 , and the timing chart in which two clock signals of the four clock signals input to the latch-decode circuit 23 are stopped and the circuit functions as a 2-bit TDC.
- FIG. 11 shows an algorithm of converting extension codes into binary values.
- FIG. 12 shows an example of decoding results of the extension codes EB[3:0] into binary values.
- the four signals at phases shifted by 1/8 Tck (Tck is a clock signal period) are input to the latch-decode circuit 23 , and the timing chart is when the two clock signals of them operate.
- FIG. 10 shows the timing chart when the clock signal CLKA and the clock signal CLKC operate and the clock signal CLKB and the clock signal CLKD are stopped. Further, in FIG. 10 , the dotted lines show that the clock signals are stopped.
- the first period from 0 to 2/8 Tck of the clock signal period is converted into the count value of “0”
- the period from 3/8 Tck to 4/8 Tck of the clock signal period is converted into the count value of “2”
- the period from 5/8 Tck to 6/8 Tck of the clock signal period is converted into the count value of “4”
- the period from 7/8 Tck to 8/8 Tck of the clock signal period is converted into the count value of “6”
- pulses in the numbers having the correspondence relations as shown in FIG. 12 are generated.
- extension codes EB[ 3 ], EB[ 1 ] are “1, 0”, the binary code is “000” and the decode value is “0”. If the extension codes EB[ 3 ], EB[ 1 ] are “1, 1”, the binary code is “010” and the decode value is “2”. If the extension codes EB[ 3 ], EB[ 1 ] are “0, 1”, the binary code is “100” and the decode value is “4”. If the extension codes EB[ 3 ], EB[ 1 ] are “0, 0”, the binary code is “110” and the decode value is “6”.
- the number of clock signals necessary for acquisition of the phase information is smaller by two. This means that, by reducing the resolution of 1 bit, the operation of the two clock signals is no longer necessary. It is clear that, if the two clock signals are not operated, the power to be consumed may be reduced by the amount.
- FIG. 13 is a timing chart for explanation of an operation of the A/D converter 20 in FIG. 4 , and the timing chart in which three clock signals of the four clock signals input to the latch-decode circuit 23 are stopped and the circuit functions as a 1-bit TDC.
- FIG. 14 shows an algorithm of converting extension codes into binary values.
- FIG. 15 shows an example of decoding results of the extension codes EB[3:0] into binary values.
- the four signals at phases shifted by 1/8 Tck (Tck is a clock signal period) are input to the latch-decode circuit 23 , and the timing chart is that when the one clock signal of them operates.
- FIG. 13 shows the timing chart when the clock signal CLKA operates and the clock signal CLKB, the clock signal CLKC, and the clock signal CLKD are stopped. Further, in FIG. 13 , the dotted lines show that the clock signals are stopped.
- the first period from 0 to 4/8 Tck of the clock signal period is converted into the count value of “0”
- the period from 5/8 Tck to 8/8 Tck of the clock signal period is converted into the count value of “4”
- pulses in the numbers having the correspondence relations as shown in FIG. 15 are generated. If the extension code EB[ 3 ] is “1”, the binary code is “000” and the decode value is “0”. If the extension code EB[ 3 ] is “1”, the binary code is “100” and the decode value is “4”.
- the number of clock signals necessary for acquisition of the phase information is smaller by one.
- the number of clock signals necessary for acquisition of the phase information is smaller by three. It is clear that, if the three clock signals are not operated, the power to be consumed may be reduced by the amount.
- the resolution becomes lower.
- the power consumption can be reduced without deterioration of the image quality due to reduction of the resolution.
- the time when the clock signal is stopped is, for example, when the voltage width D RANGE /2 n of 1 LSB is smaller than the half of the total amount of noise N/2 as described above. Even when the clock signal is stopped in the area and the resolution is reduced, decoding may be performed without any substantial influence on the image quality.
- latch-decode circuit 23 is used by switching in the order of the 3-bit TDC, 2-bit TDC, 1-bit TDC, in other words, the case where the latch-decode circuit 23 is switched from an operation mode of operating four clock signals to an operation mode of operating two clock signals, and further switched to an operation mode of operating one clock signal will be explained with reference to FIG. 16 .
- FIG. 16 shows an A/D conversion period and operation periods of four clock signals.
- counting is performed at the higher potential of the pixel output VSL (lower illuminance) and, in the second half of the A/D conversion period, counting is performed at the lower VSL potential (higher illuminance).
- the circuit is operated as the 3-bit TDC with higher resolution in the black region with lower illuminance, and, concurrently, the four clock signals CLKA, CLKB, CLKC, CLKD are operated. From the region where the resolution may be reduced, the two clock signals CLKB, CLKD are stopped, and the circuit is operated as the 2-bit TDC. Further, the one clock signal CLKC is stopped, and the circuit is operated as the 1-bit TDC.
- the current consumption may be reduced at least by the stopped clock signals in the case where the clock signals CLKB, CLKC, CLKD are stopped and the circuit functions with resolution of n bits compared to the case where the four clock signals are constantly operated and the circuit functions with resolution of m bits. Further, by stopping the clock signals in the white region, the substantial deterioration of image quality is not caused even when the clock signals are stopped and the resolution is reduced.
- FIGS. 17A to 17C show waveforms of the control signals.
- FIG. 17A shows a waveform when the latch-decode circuit 23 functions as a 3-bit TDC
- FIG. 17B shows a waveform when the circuit functions as a 2-bit TDC
- FIG. 17C shows a waveform when the circuit functions as a 1-bit TDC.
- the pulse of the control signal EBCK is a signal source for driving the counter.
- the control signal EBCKO is a pulse representing whether the pulse of the control signal EBCK is passed or not, and the pulse for control to pass the pulse when the count is necessary and not to pass the pulse when the count is unnecessary according to the combination of the values of extension codes.
- the passing pulse actually drives the counter as a count clock signal.
- a control signal XEBMSK is a control signal for performance of mask processing of determining whether the extension code EB[ 3 ] by the latch circuit 41 is input or not to the second decode circuit 56 .
- a control signal EB 4 CK is a control signal for conversion of the extension code EB[ 3 ] of the latch circuit 41 into pulse (train) in response to the pulse of the control signal EB 4 CK and output of the signal D[ 2 ] as a count clock signal of the second ripple counter part 57 .
- the flip-flops 62 , 63 storing the respective extension codes are accessed at the EBSEL[2:0], and the control signal EBCK generates clock signal pulses one by one at the same time.
- the number of logical values is sent to the ripple counter of the first or second bit (the flip-flop 62 , 63 having the output of Q[ 0 ], Q[ 1 ]) depending on whether the pulse of the control signal EBCKO is passed or not.
- FIG. 18 is a block diagram showing a configuration example of a column parallel ADC-mounted solid-state image sensing device (CMOS image sensor) when the A/D converters 20 shown in FIG. 4 are applied to an image sensor in column parallel arrangement.
- CMOS image sensor solid-state image sensing device
- a solid-state image sensing device 100 shown in FIG. 18 has a pixel unit 102 , a vertical scan circuit 103 , a horizontal transfer scan circuit 104 , and a column processing circuit group 105 including a group of ADCs. Further, the solid-state image sensing device 100 has a digital-analog converter (DAC) 106 and an amplifier circuit 107 .
- the DAC 106 corresponds to the reference voltage supply unit 21 in FIG. 3 .
- the pixel unit 102 includes unit pixels 121 each containing a photodiode (photoelectric conversion device) and an in-pixel amplifier arranged in a matrix.
- the column processing circuit group 105 includes plural column processing circuits 151 forming the ADCs arranged with respect to each column.
- Each column processing circuit (ADC) 151 corresponds to the A/D converter circuit 20 in FIGS. 3 and 4 .
- Each column processing circuit 151 has a comparator 151 - 1 that compares a reference signal RAMP (reference voltage V ramp ) as a ramp waveform obtained by changing a reference signal generated by the DAC 106 in a stepwise manner to an analog signal obtained from the pixel through a vertical signal line 108 with respect to each row line.
- the comparator 151 - 1 corresponds to the comparator 22 in FIG. 3 .
- each column processing circuit 151 has a counter latch 151 - 2 that counts a comparison time of the comparator 151 - 1 and holds its count result.
- the counter latch 151 - 2 corresponds to the latch-decode circuit 23 and the ripple counter 24 in FIG. 3 .
- the column processing circuits 151 each has an n-bit digital signal conversion function (14 bits in the example shown in FIG. 3 ) and is provided with respect to each of vertical signal lines (column lines) 108 - 1 to 108 - n , and thereby, form a column parallel ADC block.
- the output of each memory 151 - 2 is connected to a horizontal transfer line 109 having a width of k bits, for example.
- k amplifier circuits 107 corresponding to the horizontal transfer lines are provided.
- the column processing circuits 151 i.e., the A/D converter circuits 20 are arranged in parallel, and the control signals EBSEL, EBCK, EB 4 CK, XEBMSK, etc. are commonly distributed to the respective A/D converter circuits 20 . Accordingly, when the clock signals are stopped and the resolution is reduced in the predetermined region (for example, the white region), because the data to be A/D-converted are different with respect to each column, the codes of the different resolution with respect to each column are stored in the extension codes, however, the decode processing is performed by the specific control signals in common. Therefore, it is not necessarily ensured that the times such as the times when the clock signals are stopped are appropriate in all A/D converter circuits 20 and decoding is executed.
- FIG. 19 shows decoding results of the extension codes of the 2-bit TDC by decode processing of the 3-bit TDC.
- the clock signal CLKB because the clock signal CLKB is stopped, its output is zero.
- the clock signal CLKD because the clock signal CLKD is stopped, its output is zero.
- the values by the two clock signals are not used under the normal conditions in the case of the 2-bit TDC, however, if the processing is erroneously performed as the 3-bit TDC, the values by the two clock signals are also processed.
- the decode values are 0, 0, 2, 2, 4, 4, 6, 6, however, as shown in FIG. 19 , if the extension codes of the 2-bit TDC are decoded by decode processing of the 3-bit TDC, the decode values are 0, 0, 1, 1, 6, 6, 7, 7.
- the ideal decode values refer to values having ideal linearity in response to the resolution.
- the actual decode values refer to decode values when processing, which will be described later, is not performed. If the processing to be described is performed, the differences between the actual decode values and the ideal decode values are smaller.
- FIG. 20 is a graph of the results shown in FIG. 19 .
- FIG. 20 is a graph formed by respectively plotting the ideal decode values and the actual decode values as decoding results of the extension codes of the 2-bit TDC by the decode processing of the 3-bit TDC.
- circle points are the plots of the ideal decode values.
- square points are the plots of the actual decode values, and the decode values are obtained when the clock signal CLKB and the clock signal CLKD are respectively stopped at the low states.
- FIG. 20 shows linearity (fidelity of output signals with respect to input signals) of A/D conversion with the time on the horizontal axis and the decode value on the vertical axis. From FIG. 20 , it can be seen that the ideal decode values deviate from the actual decode values.
- FIG. 21 shows a graph formed by respectively plotting ideal decode values and actual decode values as decoding results of the extension codes of the 3-bit TDC by the decode processing of the 3-bit TDC. In this case, the ideal decode values coincide with the actual decode values because the extension codes of the 3-bit TDC are decoded by the decode processing of the 3-bit TDC. Like this, it is preferable that the ideal decode values coincide with the actual decode values as much as possible.
- the actual decode values as close to the ideal decode values as possible are output.
- the processing to be described is not performed, as shown in FIG. 20 , when the two clock signals are stopped, the ideal decode values deviate from the actual decode values.
- FIG. 22 shows decoding results of the extension codes of the 1-bit TDC by decode processing of the 3-bit TDC.
- the 1-bit TDC because the clock signal CLKB is stopped, its output is zero.
- the clock signals CLKC and CLKD have been already stopped, both of their outputs are zero.
- the values by the three clock signals are not used under the normal conditions in the case of the 1-bit TDC, however, if the processing is erroneously performed as the 3-bit TDC, the values by the three clock signals are also processed.
- FIG. 23 is a graph showing them.
- FIG. 23 is a graph formed by respectively plotting the ideal decode values and the actual decode values as decoding results of the extension codes of the 1-bit TDC by the decode processing of the 3-bit TDC.
- circle points are the plots of the ideal decode values. Further, square points are the plots of the actual decode values, and the decode values are obtained when the clock signal CLKB, the clock signal CLKC, and the clock signal CLKD are respectively stopped at the low states.
- FIG. 23 shows linearity of A/D conversion with the time on the horizontal axis and the decode value on the vertical axis. From FIG. 23 , it is seen that the ideal decode values deviate from the actual decode values. Also, in this case, it is preferable that, when the clock signals are stopped, the actual decode values as close to the ideal decode values as possible are output. However, if the processing to be described is not performed, as shown in FIG. 23 , when the three clock signals are stopped, the ideal decode values deviate from the actual decode values.
- FIG. 24 shows decode values when the clock signals are stopped, i.e., at the joint of the TDCs with different resolution.
- the additional value rises and falls in the part of the joint and the monotonic increasing characteristics are lost. That is, the decode value before switching of the operation mode from the 3-bit TDC to the 2-bit TDC is “3”, and the decode value after that is “1” and the later decode value is “6”.
- the decode values monotonically increase as 0, 1, 2, 3, 4, 5, 7, 8 as shown in FIG. 5 .
- the decode values monotonically increase as 0, 0, 2, 2, 4, 4, 6, 6 as shown in FIG. 10 .
- the decode values may not monotonically increase as 0, 1, 2, 3, 1, 6, 6, 7, 7, for example, as shown in FIG. 24 .
- the decode values may not monotonically increase.
- the monotonically increasing characteristics may be lost, and, when the monotonic increasing characteristics are lost, the precision of the decode values at the loss may be lower. Accordingly, the loss of the monotonic increasing characteristics may be prevented by performance of the processing to be explained as below.
- FIG. 19 shows the decoding results of the extension codes of the 2-bit TDC by decode processing of the 3-bit TDC.
- both the clock signal CLKB and the clock signal CLKD are stopped and fixed at the low (hereinafter, they will be described as Lo-fixed). Accordingly, the logical value is “0”.
- all of the clock signal CLKB, the clock signal CLKC, and the clock signal CLKD are stopped and Lo-fixed. Accordingly, the logical value is “0”.
- FIG. 16 shows the A/D conversion period and the operation periods of the four clock signals.
- the clock signal CLKB and the clock signal CLKD are stopped when the operation mode is switched from the 3-bit TDC mode to the 2-bit TDC mode and respectively Lo-stopped. Further, when the operation mode is switched from the 2-bit TDC mode to the 1-bit TDC mode, the clock signal CLCK is also stopped and the clock signal CLCK is also Lo-stopped.
- the clock signals to be stopped are not stopped at Low as described above, but stopped at High (hereinafter, referred to as “Hi-stopped”). In other words, when the mode is switched, the clock signals are stopped so that the logical values of the clock signals to be stopped may not be “0”, but may be “1”.
- the clock signal CLKB in the case where the clock signals are stopped in the white region, for example, the clock signal CLKB as one of the clock signals is stopped, the signal is not Lo-fixed, but Hi-fixed.
- the solid line indicates the actual operation.
- the mode is switched from the 3-bit TDC mode to the 2-bit TDC mode
- the clock signal CLKB is Hi-stopped and stopped with the High state kept.
- the mode is switched from the 2-bit TDC mode to the 1-bit TDC mode
- the clock signal CLKC is Lo-stopped and stopped with the Low state kept.
- the clock signal CLKD is Lo-stopped and stopped with the Low state kept.
- the clock signal CLKD when the mode is switched from the 3-bit TDC to the 2-bit TDC, the clock signal CLKD is also stopped, and the clock signal CLKD may be Hi-stopped like the clock signal CLKB. Further, the clock signal CLKB may be Lo-stopped and the clock signal CLKD may be Hi-stopped. Furthermore, when the mode is switched from the 2-bit TDC to the 1-bit TDC, the clock signal CLKC may also be Hi-stopped.
- clock signal is Hi-stopped and which clock signal is Lo-stopped can be determined by simulations in the design phase or the like. The simulation results are shown and explained in FIG. 28 , which will be described later.
- FIG. 26 shows decoding results of the extension codes latched in the 2-bit TDC mode by the decode processing of the 3-bit TDC.
- FIG. 26 corresponds to FIG. 19 .
- FIG. 19 shows the decoding results of the extension codes of the 2-bit TDC when the clock signal CLKB is Lo-stopped by the decode processing of the 3-bit TDC
- FIG. 26 is different in that it shows decoding results of the extension codes of the 2-bit TDC when the clock signal CLKB is Hi-stopped by the decode processing of the 3-bit TDC.
- the additional values are 0, 0, 2, 2, 4, 4, 6, 6, however, when the extension codes of the 2-bit TDC are decoded by the decode processing of the 3-bit TDC and the clock signal CLKB is Lo-stopped, the decode values are 0, 0, 1, 1, 6, 6, 7, 7. In this case, the differences between the ideal values and the actual decode values are 0, 0, ⁇ 1, ⁇ 1, 2, 2, 1, 1.
- FIG. 27 shows linearity of A/D conversion with the time on the horizontal axis and the decode value on the vertical axis.
- FIG. 27 corresponds to FIG. 20 .
- FIG. 20 shows the linearity of A/D conversion when the clock signal is Lo-stopped
- FIG. 27 shows the linearity of A/D conversion when the clock signal is Hi-stopped.
- the deviation from the ideal decode values from the actual decode values is smaller and the actual decode values are plotted as the values closer to the ideal decode values than in the case shown in FIG. 20 .
- the clock signal to be Hi-stopped is not limited to the clock signal CLKB, but also the other clock signal (clock signal CLKC) may be Hi-stopped.
- FIG. 28 shows the maximum errors by combinations when the clock signal CLKB or/and clock signal CLKC are Lo-stopped or/and Hi-stopped.
- FIG. 29 shows decoding results of the extension codes latched in the 1-bit TDC mode by the decode processing of the 3-bit TDC.
- FIG. 29 corresponds to FIG. 22 .
- FIG. 22 shows the decoding results of the extension codes of the 1-bit TDC when the clock signal CLKC is Lo-stopped by the decode processing of the 3-bit TDC
- FIG. 29 is different in that it shows decoding results of the extension codes of the 1-bit TDC when the clock signal CLKC is Hi-stopped by the decode processing of the 3-bit TDC.
- the additional values are 0, 0, 0, 0, 4, 4, 4, 4, however, when the extension codes of the 1-bit TDC are decoded by the decode processing of the 3-bit TDC and the clock signal CLKC is Lo-stopped, the decode values are 0, 0, 0, 0, 7, 7, 7, 7. In this case, the differences between the ideal values and the actual decode values are 0, 0, 0, 0, 3, 3, 3, 3.
- FIG. 30 shows linearity of A/D conversion with the time on the horizontal axis and the decode value on the vertical axis.
- FIG. 30 corresponds to FIG. 23 .
- FIG. 23 shows the linearity of A/D conversion when the clock signal is Lo-stopped
- FIG. 30 shows the linearity of A/D conversion when the clock signal is Hi-stopped.
- FIG. 22 and FIG. 30 it can be clearly seen that, in the case shown in FIG. 30 , the deviation from the ideal decode values from the actual decode values is smaller and the actual decode values are plotted as the values closer to the ideal decode values than in the case shown in FIG. 23 .
- FIG. 31 shows combinations of the logics of stopping three clock signals CLKB, CLKC, CLKD to be stopped in the 1-bit TDC and the maximum errors thereof.
- the predetermined region for example, the white region
- the reduction of the power consumption due to by stopping of the clock signals can be realized while the reduction of linearity is suppressed to the minimum.
- FIG. 32 shows decode values when the clock signals are stopped, i.e., at the joint of the TDCs with different resolution.
- FIG. 32 corresponds to FIG. 24 .
- FIG. 24 shows the decode values when the clock signal is Lo-stopped at the joint of the TDCs with different resolution, and FIG. 32 is different in that it shows decode values when the clock signal is Hi-stopped at the joint of the TDCs with different resolution.
- the example shown in FIG. 32 is an example in which the clock signal CLKB is High-stopped when the mode is switched from the 3-bit TDC to the 2-bit TDC.
- the decode values in this case are 0, 1, 2, 3, 4, 5, 6, 7, 6.
- the value before switching is “7” and the value after switching is “6”.
- the values are “6”, “7”, and then, if it monotonically increases, becomes “8”, however, becomes “6” and the monotonic increasing characteristics are lost and there is a small value of change as small as “1”.
- the power consumption can be reduced at least by the amount of stopped clock signals. Stopping the clock signals makes the resolution lower, however, because the resolution is lower in the region less affected by the lower resolution (for example, the white region), the final decode values are not affected and the image quality may be maintained.
- the power consumption can be reduced without deterioration of the image quality.
- the resolution switching the resolution
- the clock signals are stopped
- the states of the stopped clock signals the Low or High states
- the change of the upper bits of the counters are observed, the illuminance and the resolution of the columns are recognized, and, from the plural decode controls distributed to the entire columns, decode control is selectively performed in response to the resolution of the respective columns.
- the clock signals are stopped in a predetermined region and the following processing is executed when they are stopped. Further, the processing explained as below is processing applied to the column parallel ADC-mounted solid-state image sensing device (CMOS image sensor) shown in FIG. 18 , using plural A/D converters, and performed when the control signals are used in common.
- CMOS image sensor solid-state image sensing device
- the A/D converter circuit 20 shown in FIG. 3 belongs to an integrating A/D converter circuit and up-counts the A/D conversion period, and accordingly, when the period in which the clock signals are stopped is set to a point at which the counter value changes, the configuration of referring to the counter value in reverse may be formed. Specifically, by forming the configuration of referring to the upper bits, in which A/D conversion period the VCO changes and the extension code is latched may be identified in each column.
- the Q[ 12 ] and the Q[ 13 ] are referred to.
- the predetermined clock signals are stopped as the 2-bit TDC
- the predetermined clock signals are stopped as the 1-bit TDC.
- processing is performed to assert a control signal TDC 2 SEL when the Q[ 12 ] first becomes “1” in the logic circuit, and assert a control signal TDC 1 SEL when the Q[ 13 ] first becomes “1” in the logic circuit.
- the latch-decode circuit 23 when the control signal TDC 2 SEL and the control signal TDC 1 SEL are not asserted (“0”), the latch-decode circuit 23 ( FIG. 3 ) functions as the 3-bit TDC.
- the latch-decode circuit 23 When the control signal TDC 2 SEL is asserted (“1”) and the control signal TDC 1 SEL is not asserted (“0”), the latch-decode circuit 23 functions as the 2-bit TDC.
- both the control signal TDC 2 SEL and the control signal TDC 1 SEL are asserted (“1”), the latch-decode circuit 23 functions as the 1-bit TDC.
- the condition that the control signal TDC 2 SEL is not asserted (“0”) and the control signal TDC 1 SEL is asserted (“1”) is not caused, and not defined as an operation mode. If the condition is caused, error handling is executed.
- the A/D converter circuit 20 performing the processing has a configuration as shown in FIG. 35 .
- the same signs are assigned to the same parts as those of the A/D converter circuit 20 shown in FIG. 4 , and their explanation will be omitted.
- An A/D converter circuit 200 shown in FIG. 35 has a configuration formed by adding a TDC resolution switching circuit 201 to the A/D converter circuit 20 shown in FIG. 4 .
- FIG. 35 shows an upper bit ripple counter 202 as a ripple counter of the upper bits forming the ripple counter 24 .
- the ripple counter 24 includes flip-flops in the number of the bit number to be counted, and, of them, a flip-flop 221 and a flip-flop 222 as counters of the upper bits are shown.
- the flip-flop 221 counts the Q[x] of the upper bits and the flip-flop 222 counts the Q[y] of the upper bits.
- the x and y are “12” and “13” in the case of the A/D converter circuit 200 of performing processing that has been explained with reference to FIG. 33 .
- the x and y are not limited to “12” and “13, but may be connected to the predetermined flip-flops within the ripple counter 24 and refer to the outputs.
- the x and y are not limited to “12” and “13, but may be connected to the predetermined flip-flops within the ripple counter 24 and refer to the outputs.
- the x and y are not limited to “12” and “13, but may be connected to the predetermined flip-flops within the ripple counter 24 and refer to the outputs.
- the discontinuous outputs may be employed.
- a configuration of not only referring to two outputs but also referring to other outputs may be employed.
- the TDC resolution switching circuit 201 has an AND-OR circuit 211 including two AND circuits and one OR circuit, an AND circuit 212 , and Muller C-elements 213 , 214 .
- the Muller C-element is known as a waiting element, and is a circuit of, when two inputs are the same, outputting the value and, when the two inputs are different, retaining and outputting the previous output value.
- the first input terminal of the first two-input AND circuit of the AND-OR circuit 211 is connected to the supply line of a pulse signal EBCK 2 .
- a control signal TDC 2 SEL from the AND circuit 214 is supplied to the second negative input terminal of the first two-input AND circuit.
- the first input terminal of the second two-input AND circuit of the AND-OR circuit 211 is connected to the supply line of a pulse signal EBCK 1 .
- the control signal TDC 2 SEL from the Muller C-element 214 is supplied to the second input terminal of the second two-input AND circuit.
- the outputs from the first two-input AND circuit and the second two-input AND circuit are supplied to the OR circuit.
- the output from the OR circuit is supplied to the first input terminal of the AND circuit 212 .
- a control signal TDC 1 SEL from the Muller C-element 213 is supplied to the second negative input terminal of the AND circuit 212 .
- the output from the AND circuit 212 is supplied to the first input terminal of the first three-input AND circuit and the first input terminal of the second three-input AND circuit of the AND-OR circuit 61 as pulse signals EBCK.
- FIGS. 36A to 36C show waveforms of control signals.
- FIG. 36A shows a waveform when the latch-decode circuit 23 ( FIG. 3 ) functions as a 3-bit TDC
- FIG. 36B shows a waveform when the circuit functions as a 2-bit TDC
- FIG. 36C shows a waveform when the circuit functions as a 1-bit TDC.
- the control waveforms shown in FIGS. 36A to 36C are waveforms of the control signals supplied to the latch-decode circuit 23 , and the contents of the latch-decode circuit 23 are part of the A/D converter circuit 200 shown in FIG. 35 .
- the control waveforms shown in FIGS. 36A to 36C are waveforms of the control signals supplied to the A/D converter circuit 200 , and, for comparison, reference to the waveforms of the control signals supplied to the A/D converter circuit 20 ( FIG. 4 ) shown in FIGS. 17A to 17C are made again.
- FIG. 17A and FIG. 36A are compared.
- FIG. 36A has the control signal EBCK 2 and the control signal EBCK 1 added to FIG. 17A .
- the control signal EBCK, the control signal EBCKO, the control signal XEBMSK, and the control signal EB 4 CK are signals for performance of the same control in the A/D converter circuit 20 and the A/D converter circuit 200 .
- the control signal EBCK is a signal externally supplied and commonly supplied to the respective columns, and, in the A/D converter circuit 200 ( FIG. 35 ), the control signal EBCK is different in that it is a signal generated from the control signal EBCK 1 and the control signal EBCK 2 .
- the control signal EBCK is the signal externally supplied, and, in the A/D converter circuit 200 ( FIG. 35 ), the control signal EBCK is the self-generated signal.
- the individual columns can execute decode processing with optimal resolution in the columns based on the control signals EBCK different in the respective columns.
- the control signal EBCK is commonly supplied to the respective columns.
- two pulses for 2-bit TDC are distributed in the control signal EBCK 1 and three pulses for 3-bit TDC are distributed in the control signal EBCK 2 in the entire columns, and, by selecting and masking the control signal EBCK 1 and control signal EBCK 2 in response to the values of the control signal TDC 2 SEL and the control signal TDC 1 SEL, decoding in response to the resolution can be performed.
- EBSEL [2:0] are arranged to be accessed to the EB[ 2 ] once, the EB[ 1 ] twice, and the EB[ 0 ] once at times shifted for both the 3-bit TDC and the 2-bit TDC.
- the operation mode is the 3-bit TDC.
- the control signal EBCK 2 is selected for the decode pulse and three pulses are output to the control signal EBCK.
- the counting is performed depending on whether or not the pulse passes through the control signal EBCKO according to the value of the EB[ 3 ] and the values of the accessed EB[2:0] is the same as that in the case that has been explained with reference to FIGS. 17A to 17C .
- the operation mode is the 2-bit TDC.
- the control signal EBCK 1 is selected for the decode pulse and two pulses are output to the control signal EBCK.
- the counting is performed depending on whether or not the pulse passes through the control signal EBCKO according to the value of the EB[ 3 ] and the value of the twice-accessed EB[ 1 ] is the same as that in the case that has been explained with reference to FIGS. 17A to 17C .
- the operation mode is the 1-bit TDC.
- the control signal EBCK 2 and the control signal EBCK 1 are masked and no pulse is generated in the control signal EBCK. Accordingly, if there is access by the EBSEL[2:0], no pulse is generated in the EBCKO.
- the decode processing is executed based on the control signal TDC 2 SEL and control signal TDC 1 SEL, and thus, in the A/D converter circuit 200 shown in FIG. 35 , by stopping the clock signals in the predetermined region (for example, the white region), the power consumption may be reduced at least by the amount of the stopped clock signals. Stopping the clock signals makes the resolution lower, however, because the resolution is lower in the region less affected by the lower resolution (for example, the white region), the final decode values are not affected and the image quality may be maintained.
- the power consumption can be reduced without deterioration of the image quality.
- the resolution is reduced, i.e., the clock signals are stopped, by performing decode processing with reference to the upper bits in the ripple counter based on the signals generated by assertion of the predetermined control signals (in the above described example, the control signal TDC 2 SEL and control signal TDC 1 SEL), the deterioration of linearity and the loss of monotonic increasing characteristics can be prevented. That is, even when the resolution is reduced, the image quality at the same level as that before reduction of the resolution can be maintained.
- the upper bit counters that start operation or stop operation by inversion of the outputs of the comparators as triggers and performing count with respect to each period of the clock signals
- time-to-digital converters TDCs
- latch the phase information at the times when the outputs of the comparators are inverted using the plural clock signals at different phases decode the values, and thereby, output the lower bits with the higher resolution than the periods of the clock signals, by reducing the resolution of the TDCs in the white (light) region in response to the illuminance, the clock signals having unnecessary phase information are stopped and the power consumption can be reduced.
- the integrating A/D converter may be applied to a CMOS image sensor having integrating A/D converters in column parallel, and, with respect to the groups of TDCs with different resolution in columns depending on differences of illuminance, the possibility of deterioration of the DNL (differential non linearity) and the deterioration of linearity caused by performance of uniform decode control in response to the specific resolution in the entire columns can be relaxed by control of the logical values to be fixed when the clock signals are stopped.
- the decode control can be selectively performed in response to the resolution of the respective columns from the plural decode controls distributed in the entire columns, and deterioration of the DNL (differential non linearity) and the deterioration of linearity may be prevented.
- FIG. 37 shows a configuration of one embodiment of an A/D converter (analog digital converter).
- An A/D converter 300 has a reference voltage supply unit 321 , a comparator 322 , a latch-decode circuit 323 , a ripple counter 324 , and a gray code counter 325 .
- the latch-decode circuit 323 includes a latch circuit and a decode circuit.
- the A/D converter 300 is an integrating A/D converter that acquires the lower bits by an upper bit counter and a GC counter (gray code counter) characterized in that the change between adjacent values is constantly 1 bit.
- FIG. 37 shows an A/D converter with resolution of 14 bits including a ripple counter of the upper 9 bits and a GC counter of the lower 5 bits as an example.
- the comparator 322 compares a reference voltage Vramp having a ramp waveform with a voltage value linearly changing with time supplied from the reference voltage supply unit 321 to an input voltage VSL, and outputs an output signal VCO at the level in response to the result to the latch-decode circuit 323 .
- the latch-decode circuit 323 latches gray codes and outputs latch data GC.
- the gray codes GC[4:0] for 5 bits are supplied from the gray code counter 325 to the latch-decode circuit 323 .
- a reference clock signal CLK is supplied to the gray code counter 325 .
- the latch-decode circuit 323 converts latch information into pulse (train) and outputs the pulse as a count clock signal of the ripple counter 324 .
- the ripple counter 324 converts the phase information of the clock signals into binary codes as the least significant bit of the ripple counter in response to the count clock signal of the latch-decode circuit 323 .
- the column processing circuit group 105 has a configuration as shown in FIG. 38 .
- the column processing circuit group 105 includes ADCs of the lower N bits and the upper M bits.
- the column processing circuit group 105 includes ADCs of 14 bits in total of the lower 5 bits and the upper 9 bits.
- the column processing circuit group 105 has plural ADC blocks 105 - 1 to 105 -P including plural columns. In other words, the column processing circuit group 105 is segmented into plural ADC blocks, each ADC block including plural columns.
- One ADC has the configuration of the A/D converter 300 shown in FIG. 37 .
- each of gray code counters 325 - 1 to 325 -P is provided in each of the ADC blocks 105 - 1 to 105 -P.
- the gray code counters 325 - 1 to 325 -P function as code conversion counters.
- a column processing part 351 that performs comparison processing, lower bit latch, and upper bit count operation with respect to each column is provided.
- the column processing part 351 has the comparator 322 that compares a reference signal RAMP (Vslop) as a ramp waveform with changed gradient generated by the DAC 321 (reference voltage supply unit 321 ) to an analog signal VSL obtained from pixels via a vertical signal line with respect to each row line.
- the column processing part 351 has a lower bit latch part 352 of the lower N bits that latches the count value according to the output of the comparator 322 and the count results of the gray code counters 325 - 1 to 325 -P.
- the column processing part 351 has an upper bit counter part 353 for upper M bits that performs count operation according to the latch output of the most significant lower bit latch circuit of the lower bit latch part 352 .
- the lower bit latch part 352 corresponds to the latch-decode circuit 323 and the upper bit counter part 353 corresponds to the ripple counter 324 .
- the reference signal RAMP is generated as a ramp waveform with the voltage value linearly changing with time, for example.
- the comparator 322 of each column processing part 351 compares the reference signal RAMP to the analog signal VSL read from the addressed pixel of a pixel part (not shown) to the vertical signal line.
- the comparator 322 outputs the output signal VCO at the high level until the reference signal RAMP coincides with the analog signal VSL, and inverts the level of the output signal VCO from the high level to the low level at coincidence.
- Each gray code counter 325 With the inversion of the output level of the output signal VCO of the comparator 322 as a trigger, the latch operation of the gray codes GC[ 0 ] to [ 4 ] in the lower bit latch part 352 is performed.
- Each gray code counter 325 generates a gray code GC of N bits as a digital code according to the reference clock signal CLK at the frequency fn (MHz), for example, generated in a PLL circuit 371 contained in the timing control circuit and propagated in the clock signal supply line.
- the plural N-bit gray codes GC are formed as codes in which level transits between logical “0” and logical “1” only for one bit.
- the gray code counter 325 generates the least significant gray code GC[ 0 ] at the frequency (1/2)fn, generates the gray code GC[ 1 ] at the frequency (1/4)fn, and generates the gray code GC[ 2 ] at the frequency (1/8)fn MHz. Further, the gray code counter 325 generates the gray code GC[ 3 ] and the most significant gray code GC[ 4 ] at the frequency (1/16)fn.
- the respective gray code counters 325 supply the generated gray codes to the lower bit latch parts 352 for the plural columns included in the same ADC blocks 105 - 1 to 105 -P.
- the gray code counter 325 generates the binary codes BC[ 0 ] to BC[ 4 ] at the falling edge of the input reference clock signal CLK, and generates input clock signals and binary codes BC[ 0 ] to BC[ 4 ]. Further, the counter re-synchronizes the respective bits by the clock signal CK at the same frequency as that of the reference clock signal CLK and its inverted signal XCK, and outputs the gray codes GC[ 0 ] to GC[ 4 ].
- the respective gray code counters 325 supply the generated gray codes to the lower bit latch parts 352 for the plural columns included in the same ADC blocks 105 - 1 to 105 -P.
- FIG. 39 shows waveforms of the reference clock signal CLK and the gray codes GC[4:0].
- the reference voltage RAMP having the ramp waveform with the voltage value linearly changing with time supplied from the reference voltage supply unit 321 and the input voltage VSL are compared in the comparator 322 , and the comparison result is output as the VCO and supplied to the latch-decode circuit 323 .
- the upper counter starts or stops operation at the time when the VCO changes.
- the lower bit latch part 352 respectively loads and latches the gray code GC[ 0 ], the gray code GC[ 1 ], the gray code GC[ 2 ], the gray code GC[ 3 ], and the gray code GC[ 4 ] by the gray code counter 325 .
- FIG. 40 shows an A/D conversion period and operation periods of the gray codes GC[4:0]. In the first half of the A/D conversion period, counting is performed at the higher potential of the pixel output VSL (lower illuminance) and, in the second half of the A/D conversion period, counting is performed at the lower VSL potential (higher illuminance).
- the circuit In the A/D conversion period, the circuit is operated in a 5-bit GC operation mode with higher resolution in the black region with lower illuminance, and the gray codes GC[4:0] are output in the gray code counter 325 . Further, from the region where the image quality is not substantially lower even when the resolution is reduced, the output of the least significant gray code GC[ 0 ] is stopped, and the circuit is shifted to a 4-bit GC operation mode and operated as a 4-bit GC. Furthermore, then, the output of the next gray code GC[ 1 ] is stopped, and the circuit is shifted to a 3-bit GC operation mode and operated as a 3-bit GC. Subsequently, the circuit may subsequently be shifted to a 2-bit GC operation mode and a 1-bit GC operation mode, or the shift of the operation mode may be stopped in the 3-bit GC operation mode.
- the power consumption can be reduced.
- the outputs of the gray codes may be stopped. It is clear that, by stopping the outputs of the gray codes, the current consumption may be reduced by the amount of stopped GC[1:0] in the predetermine region (for example, the white region) compared to the case where the gray codes GC[4:0] are continuously output from the gray code counter 325 .
- FIG. 41 shows a method of converting the gray codes GC[4:0] of 5 bits into binary values BC[4:0].
- the lower binary code BC[m ⁇ 1] is calculated by an exclusive OR of the upper binary code BC[m] and the gray code GC[m ⁇ 1] corresponding to the lower binary code.
- the most significant gray code GC[ 4 ] is converted into the binary code BC[ 4 ] as it is.
- the lower bits are converted into the binary codes BC by an exclusive OR (EXOR) of the gray code GC latched at the stage of itself and the binary code BC at the previous stage, and thus, the binary code BC[ 3 ] is obtained by EXOR of the gray code GC[ 3 ] latched at the stage of itself and the binary code BC[ 4 ] at the previous stage.
- EXOR exclusive OR
- the binary code BC[ 2 ] is obtained by EXOR of the gray code GC[ 2 ] latched at the stage of itself and the binary code BC[ 3 ] at the previous stage
- the binary code BC[ 1 ] is obtained by EXOR of the gray code GC[ 1 ] latched at the stage of itself and the binary code BC[ 2 ] at the previous stage
- the binary code BC[ 0 ] is obtained by EXOR of the gray code GC[ 0 ] latched at the stage of itself and the binary code BC[ 1 ] at the previous stage.
- the binary code is obtained using the gray codes with the same significance as that of the lower binary code.
- FIG. 42 linearity of A/D conversion is shown by the results of the conversion into binary values according to the above described algorithm with the time on the horizontal axis and the decode value on the vertical axis.
- the actual decode values are values when the gray code GC[ 0 ] is Lo-fixed and stopped as shown in FIG. 40 .
- circle points are the plots of the ideal decode values
- square points are the plots of the actual decode values when the circuit operates in the 4-bit GC operation mode.
- FIG. 45 shows a table in which combinations of the logical values of the two gray codes GC[ 1 ], GC[ 0 ] to be stopped in the 3-bit GC operation region and the maximum errors thereof.
- FIG. 46 shows linearity of A/D conversion with the time on the horizontal axis and the decode value on the vertical axis.
- FIG. 46 shows results of the 3-bit GC operation region.
- FIG. 46 corresponds to FIG. 43
- circle points are the plots of the ideal decode values
- the rate of increase of the decode value from time 4 to time 5 and the rate of increase of the decode value from time 8 to time 9 are different. In this case, they are monotonically increase, however, the difference between the rates of increase is larger.
- the rate of increase of the decode value from time 4 to time 5 and the rate of increase of the decode value from time 8 to time 9 are nearly equal. In this case, they are monotonically increase and the difference between the rates of increase is smaller. From the results, it is known that the monotonic increasing characteristics are also improved.
- the current consumption can be reduced by stopping the outputs of the gray codes to be unnecessary by reducing the resolution from the gray code counters in the white (light) region in response to the illuminance.
- the integrating A/D converters may be applied to a CMOS image sensor in column parallel arrangement, with respect to the groups of gray-binary combined counters with different resolution in columns depending on differences of illuminance, the possibility of deterioration of the DNL (differential non linearity) and the deterioration of linearity caused by performance of uniform decode control in the entire columns can be relaxed by control of the logical values when the gray codes output from the gray code counters are stopped.
- the integrating A/D converter has been explained as an example, however, not limited to the integrating type, the present disclosure may be applied to a sequential comparison type, a pipeline type, a ⁇ type, or the like.
- the above described series of processing may be executed by hardware or software.
- the programs forming the software are installed in a computer.
- the computer includes a computer incorporated in dedicated hardware, a general-purpose computer, for example, that can execute various functions by installation of various programs, or the like.
- FIG. 47 is a block diagram showing a configuration example of hardware of a computer that executes the above described series of processing using programs.
- a CPU Central Processing Unit
- ROM Read Only Memory
- RAM Random Access Memory
- An input/output interface 1005 is further connected to the bus 1004 .
- An input unit 1006 , an output unit 1007 , a memory unit 1008 , a communication unit 1009 , and a drive 1010 are connected to the input/output interface 1005 .
- the input unit 1006 includes a keyboard, a mouse, a microphone, etc.
- the output unit 1007 includes a display, a speaker, etc.
- the memory unit 1008 includes a hard disc, a nonvolatile memory, or the like.
- the communication unit 1009 includes a network interface or the like.
- the drive 1010 drives a magnetic disc, an optical disc, a magneto-optical disc, or a removable medium 1011 such as a semiconductor memory.
- the above described series of processing is performed by the CPU 1001 loading the program stored in the memory unit 1008 , for example, via the input/output interface 1005 and the bus 1004 in the RAM 1003 and executing it.
- the program executed by the computer (CPU 1001 ) may be recorded and provided in the removable medium 1011 as a package medium or the like, for example. Further, the program may be provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.
- the program may be installed in the memory unit 1008 via the input/output interface 1005 by mounting of the removable medium on the drive 1010 . Further, the program may be received by the communication unit 1009 via a wired or wireless transmission medium and installed in the memory unit 1008 . In addition, the program may be installed in the ROM 1002 and the memory unit 1008 in advance.
- the program executed by the computer may be a program for performing time-series processing along the order that has been explained in this specification, or a program for performing processing in parallel or at times necessary when a call is made.
- the system refers to the entire equipment including plural devices.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Analogue/Digital Conversion (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
Light Shot Noise=√{square root over (Q)}[e −] (1)
Light Shot Noise=E√{square root over (Q)}[Vrms] (2)
N(Q)2=(E√{square root over (Q)})2 +Nc 2 (3)
N(Q)=√{square root over (E 2 Q+Nc 2)} (4)
Voltage Width D RANGE/2n (5)
BC[m−1]=BC[m]⊕GC[m−1] (6)
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011-052084 | 2011-03-09 | ||
JP2011052084A JP2012191359A (en) | 2011-03-09 | 2011-03-09 | A/d conversion device, a/d conversion method and program |
Publications (2)
Publication Number | Publication Date |
---|---|
US20120229319A1 US20120229319A1 (en) | 2012-09-13 |
US8749420B2 true US8749420B2 (en) | 2014-06-10 |
Family
ID=46795039
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/398,994 Active 2032-05-06 US8749420B2 (en) | 2011-03-09 | 2012-02-17 | A/D converter, A/D conversion method, and program |
Country Status (5)
Country | Link |
---|---|
US (1) | US8749420B2 (en) |
JP (1) | JP2012191359A (en) |
KR (1) | KR20120103453A (en) |
CN (1) | CN102684698A (en) |
TW (1) | TW201242262A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130120622A1 (en) * | 2010-05-14 | 2013-05-16 | Panasonic Corporation | Solid-state imaging device, imaging system, and method for driving solid-state imaging device |
US20150181145A1 (en) * | 2013-12-24 | 2015-06-25 | Samsung Electronics Co., Ltd. | Analog-to-digital converter configured to operate at high speed and image sensor including the same |
US10587832B2 (en) | 2017-10-31 | 2020-03-10 | Samsung Electronics Co., Ltd. | Analog to digital converting circuit and an operation method thereof |
US20220345147A1 (en) * | 2021-04-27 | 2022-10-27 | Novatek Microelectronics Corp. | Column analog-to-digital converter and local counting method thereof |
US11921537B2 (en) | 2021-08-30 | 2024-03-05 | Stmicroelectronics International N.V. | Method and circuit for calibration of high-speed data interface |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9628147B2 (en) * | 2011-02-01 | 2017-04-18 | Fu Da Tong Technology Co., Ltd. | Method of automatically adjusting determination voltage and voltage adjusting device thereof |
JP6112871B2 (en) * | 2013-01-18 | 2017-04-12 | キヤノン株式会社 | Imaging device and imaging apparatus |
US9712178B2 (en) * | 2013-05-03 | 2017-07-18 | Texas Instruments Incorporated | Dynamic resolution adjustment for digital converters |
JP2015026934A (en) * | 2013-07-25 | 2015-02-05 | 株式会社東芝 | Solid state image pickup device |
KR102104564B1 (en) | 2013-11-21 | 2020-04-24 | 삼성전자주식회사 | Digital correlated double sampling circuit and image sensor including the same |
JP6394056B2 (en) * | 2013-11-27 | 2018-09-26 | ソニー株式会社 | A / D conversion device, gray code generation device, imaging device, and electronic device |
JP2015115655A (en) * | 2013-12-09 | 2015-06-22 | 株式会社東芝 | Analog digital converter, and image sensor |
US9000968B1 (en) * | 2013-12-16 | 2015-04-07 | Freescale Semiconductor, Inc | Analog-to-digital converter with clock halting circuit |
JP6314477B2 (en) | 2013-12-26 | 2018-04-25 | ソニー株式会社 | Electronic devices |
JP6274898B2 (en) * | 2014-02-17 | 2018-02-07 | キヤノン株式会社 | Solid-state imaging device and camera |
KR102261595B1 (en) | 2014-09-19 | 2021-06-04 | 삼성전자주식회사 | An image sensor, and an image processing system including the same |
JP6666043B2 (en) * | 2015-09-10 | 2020-03-13 | キヤノン株式会社 | Imaging device and imaging system |
JP2017219586A (en) * | 2016-06-03 | 2017-12-14 | 株式会社ジャパンディスプレイ | Signal supply circuit and display |
US9722623B1 (en) * | 2016-12-19 | 2017-08-01 | Stmicroelectronics International N.V. | Analog-to-digital converter with dynamic element matching |
JP6910255B2 (en) * | 2017-09-14 | 2021-07-28 | シャープ株式会社 | AD converter and solid-state image sensor |
JP6941890B2 (en) * | 2017-10-11 | 2021-09-29 | 株式会社テックイデア | Time domain A / D converter group and sensor device using this |
JP7134782B2 (en) * | 2018-08-20 | 2022-09-12 | キヤノン株式会社 | AD conversion device, imaging device, imaging system, and moving body |
US11575853B2 (en) * | 2020-09-29 | 2023-02-07 | Shenzhen GOODIX Technology Co., Ltd. | Image sensor having high resolution analog to digital converter |
KR102556056B1 (en) | 2021-07-14 | 2023-07-13 | 연세대학교 산학협력단 | Input adaptive event driven voltage controlled oscillator based non-uniform sampling analog-to-digital converter |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5231398A (en) * | 1992-04-24 | 1993-07-27 | Panasonic Technologies, Inc. | Method and apparatus for self-tracking multiple analog to digital conversion |
US5610604A (en) * | 1994-12-07 | 1997-03-11 | Panasonic Technologies, Inc. | Analog to digital converter providing varying digital resolution |
JP2005278135A (en) | 2004-02-23 | 2005-10-06 | Sony Corp | Solid state imaging device, and driving method of solid state imaging device |
JP2006033453A (en) | 2004-07-16 | 2006-02-02 | Sony Corp | Data processing method, semiconductor device for detecting physical quantity distribution, and electronic equipment |
US7443333B2 (en) * | 2007-02-13 | 2008-10-28 | Freescale Semiconductor, Inc. | Single stage cyclic analog to digital converter with variable resolution |
US7561091B1 (en) * | 2008-01-03 | 2009-07-14 | The Boeing Company | Analog to digital converter with dynamically reconfigurable conversion resolution |
US20100128817A1 (en) * | 2006-08-18 | 2010-05-27 | Desmond Philips | Wireless receiver and method of saving power |
US8009075B2 (en) * | 2008-08-29 | 2011-08-30 | Broadcom Corporation | Analog to digital converter (ADC) with extended dynamic input range |
US8462037B2 (en) * | 2009-11-13 | 2013-06-11 | The Board Of Trustees Of The University Of Illinois | Method and system having adjustable analog-to-digital conversion levels |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0653832A (en) * | 1992-08-03 | 1994-02-25 | Hitachi Ltd | Multistage type a/d converter |
JP2000252825A (en) * | 1999-03-04 | 2000-09-14 | Matsushita Electric Ind Co Ltd | A/d converter |
JP4423111B2 (en) * | 2004-06-01 | 2010-03-03 | キヤノン株式会社 | Imaging device and imaging system |
JP2008092091A (en) * | 2006-09-29 | 2008-04-17 | Tokyo Institute Of Technology | Integral a-d converter, imaging apparatus having a-d converter, and electronic apparatus |
JP5131024B2 (en) * | 2008-05-16 | 2013-01-30 | 大日本印刷株式会社 | A / D converter, A / D conversion method, and solid-state imaging device including A / D converter or A / D conversion method |
JP2010154372A (en) * | 2008-12-25 | 2010-07-08 | Panasonic Corp | Solid-state imaging device, digital camera, and ad conversion method |
JP2010251957A (en) * | 2009-04-14 | 2010-11-04 | Sony Corp | A/d converter, solid-state image sensing device, and camera system |
JP5407523B2 (en) * | 2009-04-24 | 2014-02-05 | ソニー株式会社 | Integrating AD converter, solid-state imaging device, and camera system |
JP5417993B2 (en) * | 2009-06-01 | 2014-02-19 | 日本テキサス・インスツルメンツ株式会社 | Analog-digital conversion circuit |
JP2010288237A (en) * | 2009-06-15 | 2010-12-24 | Sony Corp | Analog-digital converter, analog-digital conversion method, signal processing system, and signal processing method |
JP5243352B2 (en) * | 2009-06-17 | 2013-07-24 | シャープ株式会社 | AD converter, solid-state imaging device, and electronic information device |
-
2011
- 2011-03-09 JP JP2011052084A patent/JP2012191359A/en not_active Ceased
-
2012
- 2012-02-17 US US13/398,994 patent/US8749420B2/en active Active
- 2012-02-17 TW TW101105346A patent/TW201242262A/en unknown
- 2012-02-29 KR KR1020120020734A patent/KR20120103453A/en not_active Application Discontinuation
- 2012-03-02 CN CN2012100525551A patent/CN102684698A/en active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5231398A (en) * | 1992-04-24 | 1993-07-27 | Panasonic Technologies, Inc. | Method and apparatus for self-tracking multiple analog to digital conversion |
US5610604A (en) * | 1994-12-07 | 1997-03-11 | Panasonic Technologies, Inc. | Analog to digital converter providing varying digital resolution |
JP2005278135A (en) | 2004-02-23 | 2005-10-06 | Sony Corp | Solid state imaging device, and driving method of solid state imaging device |
JP2006033453A (en) | 2004-07-16 | 2006-02-02 | Sony Corp | Data processing method, semiconductor device for detecting physical quantity distribution, and electronic equipment |
US20100128817A1 (en) * | 2006-08-18 | 2010-05-27 | Desmond Philips | Wireless receiver and method of saving power |
US7443333B2 (en) * | 2007-02-13 | 2008-10-28 | Freescale Semiconductor, Inc. | Single stage cyclic analog to digital converter with variable resolution |
US7561091B1 (en) * | 2008-01-03 | 2009-07-14 | The Boeing Company | Analog to digital converter with dynamically reconfigurable conversion resolution |
US8009075B2 (en) * | 2008-08-29 | 2011-08-30 | Broadcom Corporation | Analog to digital converter (ADC) with extended dynamic input range |
US8462037B2 (en) * | 2009-11-13 | 2013-06-11 | The Board Of Trustees Of The University Of Illinois | Method and system having adjustable analog-to-digital conversion levels |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130120622A1 (en) * | 2010-05-14 | 2013-05-16 | Panasonic Corporation | Solid-state imaging device, imaging system, and method for driving solid-state imaging device |
US9019142B2 (en) * | 2010-05-14 | 2015-04-28 | Panasonic Intellectual Property Management Co., Ltd. | Solid-state imaging device, imaging system, and method for driving solid-state imaging device |
US20150181145A1 (en) * | 2013-12-24 | 2015-06-25 | Samsung Electronics Co., Ltd. | Analog-to-digital converter configured to operate at high speed and image sensor including the same |
US9681082B2 (en) * | 2013-12-24 | 2017-06-13 | Samsung Electronics Co., Ltd. | Analog-to-digital converter configured to operate at high speed and image sensor including the same |
US10587832B2 (en) | 2017-10-31 | 2020-03-10 | Samsung Electronics Co., Ltd. | Analog to digital converting circuit and an operation method thereof |
US10827145B2 (en) | 2017-10-31 | 2020-11-03 | Samsung Electronics Co., Ltd. | Analog to digital converting circuit and an operation method thereof |
US20220345147A1 (en) * | 2021-04-27 | 2022-10-27 | Novatek Microelectronics Corp. | Column analog-to-digital converter and local counting method thereof |
US11777515B2 (en) * | 2021-04-27 | 2023-10-03 | Novatek Microelectronics Corp. | Column analog-to-digital converter and local counting method thereof |
US11921537B2 (en) | 2021-08-30 | 2024-03-05 | Stmicroelectronics International N.V. | Method and circuit for calibration of high-speed data interface |
Also Published As
Publication number | Publication date |
---|---|
CN102684698A (en) | 2012-09-19 |
TW201242262A (en) | 2012-10-16 |
JP2012191359A (en) | 2012-10-04 |
US20120229319A1 (en) | 2012-09-13 |
KR20120103453A (en) | 2012-09-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8749420B2 (en) | A/D converter, A/D conversion method, and program | |
JP5181087B2 (en) | Single slope analog-to-digital converter | |
KR101996491B1 (en) | Double data rate counter, and analog-digital converting apparatus and cmos image sensor thereof using that | |
JP6188451B2 (en) | Analog-digital converter and solid-state imaging device | |
JP5799531B2 (en) | A / D converter, A / D conversion method, solid-state imaging device, and camera system | |
US8446483B2 (en) | Binary conversion circuit and method, AD converter, solid-state imaging device, and camera system | |
EP3371889B1 (en) | Analog-to-digital conversion and method of analog-to-digital conversion | |
WO2013175959A1 (en) | A/d converter, solid-state image pickup device and electronic device | |
US9871986B2 (en) | Counter, counting method, ad converter, solid-state imaging device, and electronic device | |
US20090195682A1 (en) | Counter array and image sensor including the same | |
JP6371407B2 (en) | Time detection circuit, AD conversion circuit, and solid-state imaging device | |
KR102082288B1 (en) | Double data rate counter, and analog-digital converting apparatus and cmos image sensor thereof using that | |
JP6753985B2 (en) | Analog-to-digital converter and solid-state image sensor | |
KR101111638B1 (en) | ADC using correlated double sampling and the conversion method thereof | |
JP6523733B2 (en) | Binary value conversion circuit and method thereof, AD converter and solid-state imaging device | |
CN110291783B (en) | Analog-to-digital converter, image sensor, and analog-to-digital conversion method | |
JP6726362B2 (en) | Analog-digital converter and solid-state image sensor | |
CN114326926B (en) | Double sampling counter | |
US10574927B1 (en) | Image sensor having analog-to-digital converter selectively enabling storage of count value, and analog-to-digital conversion method | |
KR20230099899A (en) | Count using milti clock and method performing thereof | |
CN210804503U (en) | Counter circuit and pixel data conversion circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SONY CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TAKAHASHI, TOMOHIRO;UI, HIROKI;REEL/FRAME:027723/0364 Effective date: 20120201 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551) Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |