KR20230099899A - Count using milti clock and method performing thereof - Google Patents

Abstract

A counter using multiple clocks according to an embodiment of the present invention comprises a ramp generator generating a ramp signal to be compared with an input signal, and comparing the ramp signal and the input signal when the ramp signal and input signal received by the ramp generator are input. It includes a comparator that outputs an output result and a counter that matches each of the first clock signal and the second clock signal of different cycles with a basic clock signal and digitally outputs the output result of the comparator. Accordingly, the present invention has an advantage in that power consumption can be prevented by reducing the number of digital outputs of the counter at the time when the first clock signal and the second clock signal of different cycles are matched with the additional clock signal.

Description

Counter using multiple clocks and its operation method {COUNT USING MILTI CLOCK AND METHOD PERFORMING THEREOF}

The present invention relates to a counter using multiple clocks and a method for operating the same, and more particularly, the number of digital outputs of the counter can be reduced at the time when each of the first clock signal and the second clock signal of the delayed phase and an additional clock signal are matched. The present invention relates to a counter using multiple clocks and an operating method thereof, which can prevent power consumption.

An image sensor is a device that captures an image using the property of a semiconductor that responds to light. Recently, with the development of CMOS technology, a CMOS image sensor using CMOS is widely used.

A CMOS image sensor requires an operation of converting an analog signal output from an active pixel sensor (APS) array into a digital signal. Therefore, for this conversion, the CMOS image sensor uses an analog to digital converter (ADC).

The CMOS image sensor is divided into a single ADC method and a column ADC method according to the analog-to-digital conversion method. The single ADC method uses one ADC operating at high speed to convert the analog pixel signals output from all columns into digital signals within a fixed time. Since it has to be operated, there is a disadvantage in that power consumption is large.

In contrast, the column ADC method is a method in which ADCs having a simple structure are arranged for each column, and power consumption is smaller than that of the single ADC method.

Meanwhile, the above-described column ADC may include a counter, for example, an up/down counter. The up/down counter compares a pixel signal output through the APS array with a ramp signal output from an external device, for example, a ramp signal generator, and counts a state transition time of the comparison signal output as a result of the comparison.

For example, if a counter outputting a 4-bit binary codeword performs an up count operation and the counter output at the current time point is 0111, the counter output at the next time point becomes 1000, at which time the maximum toggle of the counter The number of bits to be ringed is 4. That is, the maximum number of toggled bits of a counter outputting an N-bit binary codeword may be N. where N is a natural number.

The increase in the instantaneous current change of the counter causes a problem in that the operation margin of the counter is lowered when a current drop phenomenon occurs during high-speed operation of the counter. Defects in such a counter may appear as defects in an image sensor.

The present invention is a counter using multiple clocks that can reduce power consumption by reducing the number of digital outputs of the counter at the time when each of the first clock signal and the second clock signal of the delayed phase and the additional clock signal are matched, and Its purpose is to provide an operation method.

In addition, in the present invention, when the state of the clock along with the clock for reference is arranged within one cycle of the operating clock that operates the ripple counter, the operation to secure the resolution by using the patterned and appearing distinctive property is the stop signal of the counter. Therefore, it is an object of the present invention to provide a counter using multiple clocks and an operating method thereof that can reduce power consumption by operating less than a ripple counter having the same resolution.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned above can be understood by the following description and will be more clearly understood by the examples of the present invention. It will also be readily apparent that the objects and advantages of the present invention may be realized by means of the instrumentalities and combinations indicated in the claims.

A counter using multiple clocks to achieve this object is a ramp generator that generates a ramp signal to be compared with an input signal, and when the ramp signal and input signal received by the ramp generator are input, the ramp signal and the input signal are compared to output the result. and a counter that outputs an output result of the comparator in digital form by matching the first clock signal and the second clock signal of the delayed phase with the basic clock signal.

In one embodiment, the second clock signal may be generated after being delayed by a specific time based on the first clock signal.

In one embodiment, the first clock signal and the second click signal may have a phase difference of 90 degrees.

In one embodiment, the additional clock signal may include a period including a period of the first clock signal and a period of the second clock signal.

In one embodiment, the counter may divide the period of each of the first clock signal and the second clock signal according to the additional clock signal and then digitally output the output result of the comparator according to the divided clock signal. there is.

In addition, a method of operating a counter using multiple clocks to achieve this object includes generating a ramp signal to be compared with an input signal by a ramp generator, and when the ramp signal and the input signal received by the ramp generator are input to the comparator, the ramp signal is input. Comparing the signal and the input signal and outputting an output result, and matching the first clock signal and the second clock signal of different cycles with the additional clock signal by the counter to output the output result of the comparator as a digital output. .

In one embodiment, the second clock signal may be generated after being delayed by a specific time based on the first clock signal.

In one embodiment, the first clock signal and the second click signal may have a phase difference of 90 degrees.

In one embodiment, the additional clock signal may include a period including a period of the first clock signal and a period of the second clock signal.

In one embodiment, the step of matching the first clock signal and the second clock signal of different cycles with the additional clock signal by the counter and outputting the output result of the comparator as a digital output may include matching the first clock signal and the second clock signal of different cycles with an additional clock signal according to the additional clock signal. and outputting an output result of the comparator as a digital output according to the divided clock signal after dividing periods of each of the first clock signal and the second clock signal.

As described above, according to the present invention, the number of digital outputs of the counter can be reduced at the time when each of the first and second clock signals of the delayed phase and the additional clock signal are matched, so that power consumption can be prevented. there is.

In addition, according to the present invention, when the state of the clock along with the clock for reference purposes is arranged within one cycle of the operating clock that operates the ripple counter, the operation of securing the resolution by using the distinctive property that is patterned is the stop of the counter. Since it operates on a signal, it eventually operates less than a ripple counter having the same resolution, and thus has the advantage of reducing power consumption.

1 is a diagram for explaining a conventional ripple counter circuit.
2 is a diagram for explaining a conventional single slope ADC.
FIG. 3 is a timing graph for explaining the operation process of FIG. 2 .
4 is a circuit diagram illustrating a counter using multiple clocks according to an embodiment of the present invention.
5 is a diagram illustrating an operation when a general clock is input to a counter using multiple clocks according to an embodiment of the present invention.
6 is a diagram for explaining an operation process of a general dual edge triggered counter and a counter using multiple clocks according to an embodiment of the present invention.
7 and 8 show an operation diagram of a conventional QDR counter, and FIG. 9 shows an operation diagram of a counter using multiple clocks according to an embodiment of the present invention.
10 is a diagram for explaining and comparing operation processes of a conventional QDR counter and a counter using multiple clocks according to an embodiment of the present invention.
11 is a diagram for explaining and comparing the operation process of a counter using multiple clocks according to an embodiment of the present invention.
12 is a diagram for explaining an operation diagram of a counter using multiple clocks according to an embodiment of the present invention.

The above objects, features and advantages will be described later in detail with reference to the accompanying drawings, and accordingly, those skilled in the art to which the present invention belongs will be able to easily implement the technical spirit of the present invention. In describing the present invention, if it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar components.

1 is a diagram for explaining a conventional ripple counter circuit.

Referring to FIG. 1 , the ripple counter circuit includes a buffer unit and a ripple counter.

The buffer unit generates at least one lower bit signal LSB by latching at least one input clock signal CLKI at the end of the counting operation, and buffers and outputs the input clock signal CLKI until the end of the counting operation. .

Accordingly, the lower bit signal LSB is a signal that toggles like the input clock signal CLK until the counting operation ends. For example, the end point of the counting operation may be indicated using the logic level of the input signal.

The ripple counter generates upper bit signals MSB that sequentially toggle in response to a latch output signal LOUT corresponding to one of the lower bit signals LSB.

This ripple counter counts the values from 00000 to 11111 over 20 cycles of the input clock signal CLKI (ADC[0], ADC[1], AD[2], ADC[3], ADC[4])

2 is a diagram for explaining a conventional single slope ADC. FIG. 3 is a timing graph for explaining the operation process of FIG. 2 .

Referring to FIG. 2 , the single slope ADC is composed of a ramp generator 10 , a comparator 120 and a counter 130 . In this case, the counter may be the ripple counter of FIG. 1 .

The ramp generator 10 generates a ramp signal V RAMP to be compared with the input signal V _PIXEL , and provides the generated ramp signal V _RAMP to the comparator 20 .

When the ramp signal VRAMP and the input signal V _PIXEL received by the ramp generator 10 are input, the comparator 20 compares the ramp signal V _RAMP and the input signal V _PIXEL to output the output signal V _{CDS_OUT} ) is output.

In one embodiment, the comparator 20 compares the ramp signal V _RAMP and the input signal V _PIXEL and outputs a high signal 1 if the input signal V _PIXEL is greater than the ramp signal V _in . can

In another embodiment, comparator 20 compares a ramp signal (V _RAMP ) and an input signal (V _PIXEL ), and outputs a low signal (0) if the input signal (V _PIXEL ) is less than the ramp signal (V _in ). can be printed out.

The counter 30 calculates the number of clocks counted by the comparator 20 based on the input clock signal (Clock) until the input signal (V _PIXEL ) is smaller than the ramp signal (Vin) and the low signal (0) is output, N It is displayed as a digital output that fits the -bit and stores the value using a latch to output N-bit digital output (ADC_OUT).

4 is a circuit diagram illustrating a counter using multiple clocks according to an embodiment of the present invention.

Referring to FIG. 4 , a counter circuit using multiple clocks is composed of a ramp generator 110 , a comparator 120 and a counter 130 . In this case, the counter may be the ripple counter of FIG. 1 .

The ramp generator 110 generates a ramp signal V RAMP to be compared with the input signal V _PIXEL , and provides the generated ramp signal V _RAMP to the comparator 120 .

When the ramp signal VRAMP and the input signal V _PIXEL received by the ramp generator 110 are input, the comparator 120 compares the ramp signal V _RAMP and the input signal V _PIXEL to output the output signal VCDS_OUT. ) is output.

In one embodiment, the comparator 120 compares the ramp signal V _RAMP and the input signal V _PIXEL and outputs a high signal 1 if the input signal V _PIXEL is greater than the ramp signal V _in . can

In another embodiment, comparator 120 compares a ramp signal (V _RAMP ) and an input signal (V _PIXEL ), and outputs a low signal (0) if the input signal (V _PIXEL ) is less than the ramp signal (V _in ). can be printed out.

The counter 130 matches each of the first clock signal and the second clock signal of different cycles with the additional clock signal so that the input signal V _PIXEL is smaller than the ramp signal V _in by the comparator 120, resulting in a low signal ( The number of clocks counted until 0) is output is displayed as a digital output suitable for N-bits, and the value is stored using a latch to output N-bit digital output (ADC_OUT).

In this case, the second clock signal may be generated after being delayed by a specific time based on the first clock signal. That is, the first clock signal and the second click signal have a phase difference of 90 degrees.

As described above, the counter 130 outputs an N-bit digital output (ADC_OUT) in a period in which each of the first clock signal and the second clock signal of different cycles and the additional clock signal are matched.

At this time, the counter 130 may divide the first clock signal and the second clock signal according to the additional clock signal, and then output the output result of the comparator as a digital output according to the divided clock signal. In this case, the additional clock signal may be composed of a period including a period of the first clock signal and a period of the second clock signal.

Accordingly, by matching each of the first clock signal and the second clock signal of different cycles with the additional clock signal, the period between the cycles of the first clock signal and the second clock signal in which the counter 130 operates is 1/2, Divide by 1/4.

5 is a diagram showing an operation diagram when a general clock is input to a counter using multiple clocks according to an embodiment of the present invention, and FIG. 6 is a general dual edge triggered counter and multiple clocks according to an embodiment of the present invention. It is a diagram for explaining the operation process of the counter using .

Referring to FIGS. 5 and 6, an operation diagram in which the multi-clock counter of FIG. 4 expresses the number of clocks counted according to a general clock as a digital output corresponding to N-bits and stores the value using a latch is shown in FIG. Same as No value is stored based on the reference number 501, but four ripple counters are used as shown in the reference number 502.

Comparing the operation diagram of the counter using multiple clocks according to an embodiment of the present invention in FIG. 6 (a) and the operation diagram of the general dual edge triggered counter in FIG. 6 (b), in the case of FIG. 6 (a), four A ripple counter is used, but in the case of a typical dual edge triggered counter in Fig. 6(b), 5 ripple counters are used.

7 and 8 show an operation diagram of a conventional QDR counter, and FIG. 9 shows an operation diagram of a counter using multiple clocks according to an embodiment of the present invention. 10 is a diagram for explaining and comparing operation processes of a conventional QDR counter and a counter using multiple clocks according to an embodiment of the present invention.

Referring to FIGS. 7 to 10 , the QDR counter counts four times for each cycle period of the input clock signal CLKI as shown in FIGS.

Since the QDR counter according to an embodiment of the present invention has an operating speed four times that of a conventional ripple counter, it can provide a binary code with 2 bits increased for the same period clock signal and the same counting time. A refined counting value can be provided.

In contrast, an operation diagram in which a counter using multiple clocks displays the number of clocks counted according to a general clock as a digital output corresponding to N-bits and stores the value using a latch is shown in FIG. 9 . No value is stored based on the reference number 901, but three ripple counters are used as shown in the reference number 902.

Comparing the operation diagram of the QDR counter in FIG. 10 (a) and the operation diagram of the counter using multiple clocks according to an embodiment of the present invention in FIG. 10 (b), in the case of FIG. 10 (a), five ripple counters are used. , In the case of FIG. 10 (b), there is an advantage in that power consumption can be reduced because three ripple counters are used.

11 is a diagram for explaining and comparing the operation process of a counter using multiple clocks according to an embodiment of the present invention.

Referring to FIG. 11 , the counter 130 matches each of the first clock signal (a) and the second clock signal (a) of different cycles with the additional clock signal (c), and the input signal ( The number of clocks counted until a low signal (0) is output when V _PIXEL ) is smaller than the ramp signal (V _in ) is displayed as a digital output suitable for N-bits, and the value is stored using a latch to obtain N-bit digital output. Output (ADC_OUT) can be output.

In this case, the second clock signal (b) may be generated after being delayed by a specific time based on the first clock signal (a). That is, the first clock signal (a) and the second click signal (b) have a phase difference of 90 degrees.

And, the additional clock signal (c) is composed of a period including the period of the first clock signal (a) and the period of the second clock signal (b). Accordingly, the counter 130 outputs an N-bit digital output (ADC_OUT) in a period matching each of the first clock signal and the second clock signal of different cycles with the additional clock signal.

As shown in FIG. 11, the first clock signal (a) in which the counter 130 operates by matching the first clock signal (a) and the second clock signal (b) of different cycles with the additional clock signal (c). And, the period of each of the second clock signal (b) may be divided by 1/2 or 1/4.

12 is a diagram for explaining an operation diagram of a counter using multiple clocks according to an embodiment of the present invention.

Referring to FIG. 12, FIG. 12(a) is an operation diagram of a counter using multiple clocks according to an embodiment of the present invention operating according to a first clock signal and a second clock signal, and FIG. 12(b) is an operation diagram when a counter using multiple clocks according to an embodiment of the present invention operates according to a first clock signal, a second clock signal, and an additional clock signal.

As shown in FIG. 12 (a), when the counter using multiple clocks according to an embodiment of the present invention operates according to the first clock signal and the second clock signal, three ripple counters are used, but FIG. 12 (b) and Similarly, when the counter using multiple clocks according to an embodiment of the present invention operates according to the first clock signal, the second clock signal, and the additional clock signal, two ripple counters are used.

As a result, when the counter using multiple clocks according to an embodiment of the present invention operates according to the first clock signal, the second clock signal, and the additional clock signal, the interval between the periods of the first clock signal and the second clock signal is 1/ It is divisible by 2, 1/4, so two ripple counters are used.

Although described by the limited embodiments and drawings, the present invention is not limited to the above embodiments, and those skilled in the art can make various modifications and variations from these descriptions. Therefore, the spirit of the present invention should be grasped only by the claims described below, and all equivalent or equivalent modifications thereof will be said to belong to the scope of the spirit of the present invention.

Claims (10)

a ramp generator for generating a ramp signal to be compared with an input signal;
a comparator which compares the ramp signal and the input signal when the ramp signal received by the ramp generator and the input signal are input, and outputs an output result;
characterized in that it comprises a counter that matches each of the first clock signal and the second clock signal of different cycles with an additional clock signal to digitally output the output result of the comparator.
A counter that uses multiple clocks.
According to claim 1,
The second clock signal is
Characterized in that it is generated delayed by a specific time based on the first clock signal
A counter that uses multiple clocks.
According to claim 1,
The first clock signal and the second click signal
Characterized in that it has a phase difference of 90 degree intervals
A counter that uses multiple clocks.
According to claim 1,
The additional clock signal is
characterized in that it consists of a period including a period of the first clock signal and a period of the second clock signal
A counter that uses multiple clocks.
According to claim 1,
the counter is
After dividing periods of each of the first clock signal and the second clock signal according to the additional clock signal, an output result of the comparator is digitally output according to the divided clock signal.
A counter that uses multiple clocks.
generating, by the ramp generator, a ramp signal to be compared with the input signal;
comparing the ramp signal received by the ramp generator and the input signal to a comparator and outputting an output result by comparing the ramp signal and the input signal;
characterized in that it comprises a step of matching each of the first clock signal and the second clock signal of different cycles with an additional clock signal to digitally output the output result of the comparator.
A method of operating a counter using multiple clocks.
According to claim 6,
The second clock signal is
Characterized in that it is generated delayed by a specific time based on the first clock signal
A method of operating a counter using multiple clocks.
According to claim 6,
The first clock signal and the second click signal
Characterized in that it has a phase difference of 90 degree intervals
A method of operating a counter using multiple clocks.
According to claim 6,
The additional clock signal is
characterized in that it consists of a period including a period of the first clock signal and a period of the second clock signal
A method of operating a counter using multiple clocks.
According to claim 6,
The counter matching the first clock signal and the second clock signal of different cycles with the additional clock signal to digitally output the output result of the comparator
Dividing periods of each of the first clock signal and the second clock signal according to the additional clock signal, and then digitally outputting an output result of the comparator according to the divided clock signal.
A method of operating a counter using multiple clocks.

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