US8710892B2 - Clock distribution circuit - Google Patents

Clock distribution circuit Download PDF

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US8710892B2
US8710892B2 US13/597,366 US201213597366A US8710892B2 US 8710892 B2 US8710892 B2 US 8710892B2 US 201213597366 A US201213597366 A US 201213597366A US 8710892 B2 US8710892 B2 US 8710892B2
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clock
circuit
branch point
signal
generation circuit
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US20130093476A1 (en
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Kazuya Fujimori
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Canon Inc
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Canon Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

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  • the present invention relates to clock distribution circuits.
  • timing margins are a direct adverse factor of clock skew, and in locations such as interfaces between blocks having long distances from the clock branch, timing margins as countermeasures of discrepancies applied to route differences use an undesirably large portion of the timing in the cycle time.
  • phase adjustment mechanisms such as PLLs and DLLs
  • there is increased sharing of many of the clock routes and phase information of sequential circuits of the terminals is fed back.
  • the influence of discrepancies that occur between the clock drivers and the wiring within independent routes after the feedback path branch cannot be ignored. Accordingly, it is difficult with conventional techniques to eliminate completely problems of discrepancies, and reduced precision in phase adjustments is anticipated.
  • Japanese Patent Laid-Open No. 2007-336003 discloses, as shown in FIG. 1 , clock distribution circuits 11 a and 11 b that are provided with a clock generation circuit 13 having multiple DLLs or PLLs or the like, and are configured with clock distribution networks 12 a and 12 b (and 14 ; abbreviated as “CDN”) for each of the clock generation circuits 13 respectively.
  • Routes 17 a and 17 b are provided that perform feedback from branch points NA1 and NB1 of the sequential circuits (abbreviated as “SC”) 16 a and 16 b having a data transfer path 18 connecting between the sequential circuits belonging to the clock distribution networks 12 a and 12 b (clock domains) whose clock generation circuits 13 are different.
  • SC sequential circuits
  • Positions where the branch points that carry out feedback are provided are determined in a following manner. These are determined such that a delay of the path from the feedback branch point NA1 to the clock input terminal of the sequential circuit 16 a and a delay from the feedback branch point NA1 to the feedback clock terminal of the clock generation circuit 13 become zero. In terms of positions, branch points are selected so as to be as close as possible to a leaf so that the delay time difference becomes small.
  • the branch point NA1 is provided at the clock driver input terminal side closest to the sequential circuit.
  • a clock driver (abbreviated as “CD”) 15 a 2 is required within the feedback path 17 so as to match the delay time from the branch point NA1 to the sequential circuit 16 a and the delay time from the branch point NA1 to the clock generation circuit 13 .
  • the clock driver 15 a 2 within the feedback path is influenced by discrepancies.
  • a difference occurs between a delay time A1 from the branch point NA1 to the clock input of the sequential circuit 16 a and a delay time A2 from the branch point NA1 to the FBK terminal of the clock generation circuit 13 , such that correct phase information cannot be fed back and the accuracy of phase adjustments is reduced undesirably (see FIG. 2 ).
  • all the sequential circuits within the clock distribution network are influenced undesirably and there is a probability that the accuracy of phase adjustments will be reduced undesirably.
  • the present invention provides a clock distribution circuit in which the influence of feedback path discrepancies is suppressed to a minimum and in which highly accurate adjustments of clock phases can be carried out.
  • a clock distribution circuit of a semiconductor integrated circuit having a clock generation circuit configured to generate a clock signal, a clock distribution network in which the clock signal is distributed, and a sequential circuit configured to operate on the clock signal distributed through a branch point of the clock distribution network, comprising: a clock generation circuit configured to input as a feedback signal the clock signal that has branched from the branch point and to output the clock signal to the clock distribution network based on the inputted feedback signal and a reference clock signal, wherein the branch point is provided at a clock driver near the clock generation circuit, among preceding stage clock drivers of the sequential circuit of the clock distribution network.
  • FIG. 2 is a timing chart showing timings of wave patterns of a clock signal and a feedback signal according to a conventional example.
  • FIG. 3 is a schematic diagram showing a configuration of a clock distribution circuit according to an embodiment.
  • FIG. 4 is a timing chart showing timings of wave patterns of a clock signal and a feedback signal according to an embodiment.
  • FIG. 7 is a flowchart showing a method of providing a feedback path based on layout data according to embodiment 3.
  • the clock distribution circuit 21 is provided with a clock distribution network 22 , a clock generation circuit 23 such as a PLL or a DLL, a distribution circuit 24 , a clock driver 25 , and wiring.
  • a branch point N1 is provided at a clock driver near the clock generation circuit 23 as a feedback branch point. Description is given later concerning a method of determining the branch point N1.
  • the clock distribution circuit 21 distributes to the multiple sequential circuits 26 the clock signal outputted from a clock output terminal CLKOUT of the clock generation circuit 23 .
  • the clock distribution network 22 is provided with wiring to constitute the clock distribution network 22 , the multiple distribution circuits 24 arranged midway on the wiring, and the multiple clock drivers 25 .
  • Multiple branch points (N1, N2, and N3 in order of proximity to the clock generation circuit 23 ) are present on the clock distribution network 22 .
  • One is a method of providing a feedback path by selecting a branch point of the feedback path based on layout data after clock routing and after placement and routing.
  • the other is a method of providing a feedback path by selecting in advance a branch point at which a feedback path is provided and controlling the placement of feedback path branch points by implementing placement restrictions with a floor plan, which is an outline placement process prior to executing routing.
  • a method of providing a feedback path based on layout data with reference to the flowchart of FIG. 6 .
  • layout data after clock routing has been executed and detailed placement and routing have been executed is applied using an ordinary CTS (clock tree synthesis) technique or the like.
  • CTS clock tree synthesis
  • a sequential circuit that is present near the clock generation circuit is extracted based on the layout data (S 601 ).
  • sequential circuits 26 n 1 , 26 n 2 , and 26 n 3 are present near the clock generation circuit.
  • a delay time of the feedback path is calculated for the extracted sequential circuit (S 602 ).
  • the delay time is calculated when the feedback paths are provided to the sequential circuits 25 n 1 , 25 n 2 , and 25 n 3 .
  • Restrictions are applied so that the sequential circuit to be connected to the branch point selected in advance is placed near the clock generation circuit in the floor plan, which is an outline placement process prior to clock routing and detailed placement and routing. Following this, placement and routing and clock routing are executed based on the placement restrictions, and a timing verification is executed as to whether or not the relevant locations are within the design margin. In a case where relevant sequential circuit is not within the design margin, the placement position thereof is corrected.
  • the branch point is provided at the output terminal of the clock driver 25 n 1 for example. Since the feedback path 27 is obtained from the output terminal side of the clock driver 25 n 1 near the clock generation circuit 23 , it is configured fundamentally of wiring only, and compositional elements that cause delay discrepancies can be suppressed to a minimum. For this reason, the difference between a delay time A3 from the branch point N1 to the leaf sequential circuit 26 n 1 and a delay time A4 from the branch point N1 to the clock generation circuit 23 can be reduced (see FIG. 4 ). Furthermore, compared to conventional technologies, there is a high probability of configuring a short route of the feedback path, and therefore the influence received from peripheral circuits can be kept small.
  • the clock signal distributed through the same clock distribution path is distributed to the clock input of the sequential circuit 26 n 1 provided with the branch point N1 and a FBK terminal of the clock generation circuit 23 as a feedback signal so that the distribution delay from the branch point N1 is substantially equivalent.
  • the clock signal at the FBK terminal of the clock generation circuit has the same frequency as the clock signal of the clock input of the sequential circuit 26 n 1 , and phase adjustments can be carried out correctly so that the phases are substantially equivalent.
  • the branch point N1 of the feedback path was obtained from the output terminal of the preceding stage clock driver 25 n 1 of the sequential circuit near the clock generation circuit 23 .
  • the branch point may be provided so that wire congestion does not occur. For example, consider a case where a circuit having multitudinous connection relationships with SRAM or with another block, or a circuit that generates a control signal is present near the clock generation circuit.
  • phase adjustments can be performed so that wire congestion does not occur. Other than this, this is the same as embodiment 1.
  • the branch point is provided at an output terminal of a preceding stage clock driver of a sequential circuit having low relevance to at least one of function and performance, that is, having a data path in which there is leeway in the timing design, or a sequential circuit having data path in which there is a large timing margin.
  • a sequential circuit that is present near the clock generation circuit is extracted based on the layout data (S 701 ).
  • a delay time of the data path is calculated for the extracted sequential circuit (S 702 ).
  • a determination is performed as to whether or not the data path timing of the extracted sequential circuit is within the design margin, and the sequential circuit having the greatest leeway in the margin is selected (S 703 ).
  • a feedback path is obtained from the output terminal side of the preceding stage clock driver of the selected sequential circuit (S 704 ).
  • Placement and routing are executed based on these placement restrictions.
  • timing verification is executed as to whether or not the relevant locations are within the design margin. In a case where they are not within the design margin, the placement position of the relevant sequential circuit or clock generation circuit is corrected, and timing verification is executed again. This is iterated and a feedback path is provided so as to be within the design margin.
  • a new sequential circuit for a feedback signal (dummy sequential circuit) is provided to the clock distribution network, and is configured so that it is placed near the clock signal generation circuit.
  • a branch point is set at the input terminal of the dummy sequential circuit and feedback of position information is carried out.
  • the dummy sequential circuit and the branch point are connected by wiring only, in a case where delay adjustments are required between the dummy sequential circuit and the branch point, there is no problem in this being configured with multiple stages of clock drivers.
  • FIG. 5 is a schematic block diagram showing one example of a clock distribution circuit according to the present embodiment.
  • a clock distribution circuit 31 a is provided within a semiconductor integrated circuit and distributes a clock signal, as a first reference clock signal, which is generated as a reference signal of a frequency and phase of an external clock signal, to multiple sequential circuits 36 .
  • a sequential circuit 36 a and a sequential circuit 36 b are connected for data transfer.
  • a data transfer path 38 constitutes a data transfer path between different domains.
  • the clock distribution circuit 31 a is provided with a clock distribution network 32 a , a clock generation circuit 33 a such as a PLL, a distribution circuit 34 , a clock driver 35 , and wiring.
  • the branch point NA2 is provided at a clock driver near the clock generation circuit as a branch point for a first feedback signal.
  • the branch point for the first feedback signal is set at a position on the output terminal side of a clock driver 35 na 1 near the clock generation circuit 33 a of the final stage clock drivers of the clock distribution network.
  • the feedback path 37 a is configured so that shift in the timing due to manufacturing discrepancies in the actual circuit layout is within the design margin. Since the feedback path 37 a is obtained from the output terminal side of the clock driver 35 na 1 near the clock generation circuit 33 a , it can be configured fundamentally of wiring only, and compositional elements that cause delay discrepancies can be kept to a minimum.
  • the delay time from the branch point NA2 to the leaf sequential circuit 36 a and the delay time from the branch point NA2 to the clock generation circuit 33 a can be matched, and the accuracy of phase adjustments can be improved.
  • the feedback path 37 a is constituted of wiring only, but a feedback driver may also be inserted as long as this is within the design margin.
  • a configuration is also possible allowing placement to be performed so that the clock generation circuit 33 a comes closer to the feedback branch point NA2 so as to be within the design margin.
  • the clock generation circuit 33 b modulates the frequency and phase of a second feedback signal so that it is in synchronization with a second reference clock signal, and outputs this to the clock distribution network 32 b as a second clock signal.
  • the second reference clock signal is an external clock signal that is supplied from the outside to a reference clock terminal RCLK of the clock generation circuit 33 b through a clock driver 35 b and wiring.
  • the second reference clock signal is the same as the first reference clock signal.
  • the second feedback signal is a second clock signal that is supplied from a second feedback branch point NB2 to the feedback clock terminal FBK of the clock generation circuit 33 b through a wire of a feedback path 37 b.
  • the branch point is set at an output terminal side of a clock driver 35 nb 1 near the clock generation circuit in a same manner as the branch point of the clock 30 a.
  • the sequential circuit 36 a of the sequential circuits 36 connected to the block 30 a and the sequential circuit 36 b of the sequential circuits 36 connected to the block 30 b are connected by a data transfer path 38 . That is, there is a transfer of data between the sequential circuit 36 a and the sequential circuit 36 b , and therefore it is necessary to align the phases of the clock signals supplied to both of these. For this reason, a branch point is set at each of the output terminal sides of the clock drivers 35 na 1 and 35 nb 1 near the clock generation circuits 33 a and 33 b of the sequential circuits 36 a and 36 b having the data transfer path.
  • the first feedback branch point NA2 of the clock distribution network 32 a is provided between the output terminal of the clock driver 35 na 1 and the clock input terminal of the sequential circuit 36 a .
  • the second feedback branch point NB2 of the clock distribution network 32 b is provided between the output terminal of the clock driver 35 nb 1 and the clock input terminal of the sequential circuit 36 b .
  • the phase of the first feedback signal is substantially equivalent to the phase of the clock signal of the clock input of the sequential circuit 36 a .
  • the first feedback signal and the first reference clock signal are inputted to the clock generation circuit 33 a , and the clock generation circuit 33 a outputs the first clock so that the phase difference between phase comparators within the clock generation circuits becomes zero.
  • the phase of the second feedback signal is substantially equivalent to the phase of the clock signal of the clock input of the sequential circuit 36 b .
  • the second feedback signal and the second reference clock signal are inputted to the clock generation circuit 33 b , and the clock generation circuit 33 b outputs the second clock so that the phase difference between phase comparators within the clock generation circuits becomes zero.
  • the first clock of the FBK terminal of the clock generation circuit 33 a and the second clock of the FBK terminal of the clock generation circuit 33 b will have the same phase. Accordingly, the phase of the first clock of the sequential circuit 36 a and the phase of the second clock of the sequential circuit 36 b can be substantially matched.
  • the timing of data transfers between the sequential circuit 36 a and the sequential circuit 36 b can be matched, and the accuracy of phase adjustments between different domains can be improved without adversely influencing data transfers.
  • the distribution delay from the CLKOUT of the clock generation circuit 33 a to the clock input of the sequential circuit 36 a and the delay from the CLKOUT of the clock generation circuit 33 a to the FBK terminal of the clock generation circuit 33 a are influenced by discrepancies.
  • the configuration is such that from the CLKOUT of the clock generation circuit 33 a to the branch point NA2 is shared, the discrepancies of the shared portion can be accurately reflected in the phase adjustment of the clock generation circuit 33 a .
  • the branch point of the feedback path provides a feedback path from the output terminal side of the clock driver near the clock generation circuit, thereby keeping compositional elements that cause discrepancies to a minimum and enabling correct phase adjustments to be carried out.
  • phase adjustments can be carried out easily without causing wire congestion.
  • the branch point can be provided at a clock driver of a sequential circuit having low relevance to performance or function (a sequential circuit having a data path with timing design leeway). By doing this, phase adjustments can be carried out easily without adversely influencing the timing adjustments within the block.
  • a sequential circuit can be configured for providing a feedback path near the clock generation circuit and the branch point can be provided from the clock driver.
  • the branch point can be provided at a preceding stage clock driver of a sequential circuit having a data transfer path with a block managed by another clock distribution network (clock domain).
  • clock domain another clock distribution network
  • aspects of the present invention can also be realized by a computer of a system or apparatus (or devices such as a CPU or MPU) that reads out and executes a program recorded on a memory device to perform the functions of the above-described embodiments, and by a method, the steps of which are performed by a computer of a system or apparatus by, for example, reading out and executing a program recorded on a memory device to perform the functions of the above-described embodiments.
  • the program is provided to the computer for example via a network or from a recording medium of various types serving as the memory device (e.g., computer-readable medium).

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JP2011227436 2011-10-14
JP2011-227436 2011-10-14
JP2012172302A JP2013102417A (ja) 2011-10-14 2012-08-02 クロック分配回路
JP2012-172302 2012-08-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10585449B1 (en) * 2019-01-15 2020-03-10 Arm Limited Clock circuitry for functionally safe systems

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9793900B1 (en) 2016-06-29 2017-10-17 Microsoft Technology Licensing, Llc Distributed multi-phase clock generator having coupled delay-locked loops

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007336003A (ja) 2006-06-12 2007-12-27 Nec Electronics Corp クロック分配回路、半導体集積回路、クロック分配回路の形成方法及びそのプログラム
JP2008010607A (ja) 2006-06-29 2008-01-17 Nec Computertechno Ltd 半導体集積回路およびクロックスキュー低減方法
US20090002041A1 (en) * 2003-04-28 2009-01-01 Micron Technology, Inc. Method for improving stability and lock time for synchronous circuits

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JPH06282350A (ja) * 1993-01-27 1994-10-07 Hitachi Ltd Ｌｓｉ内クロック分配回路
US6429715B1 (en) * 2000-01-13 2002-08-06 Xilinx, Inc. Deskewing clock signals for off-chip devices
JP2002023886A (ja) * 2000-07-11 2002-01-25 Nec Corp 半導体集積回路
US6809606B2 (en) * 2002-05-02 2004-10-26 Intel Corporation Voltage ID based frequency control for clock generating circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090002041A1 (en) * 2003-04-28 2009-01-01 Micron Technology, Inc. Method for improving stability and lock time for synchronous circuits
JP2007336003A (ja) 2006-06-12 2007-12-27 Nec Electronics Corp クロック分配回路、半導体集積回路、クロック分配回路の形成方法及びそのプログラム
JP2008010607A (ja) 2006-06-29 2008-01-17 Nec Computertechno Ltd 半導体集積回路およびクロックスキュー低減方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10585449B1 (en) * 2019-01-15 2020-03-10 Arm Limited Clock circuitry for functionally safe systems

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US20130093476A1 (en) 2013-04-18

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