US8642478B2 - Plasma processing method and plasma processing apparatus - Google Patents

Plasma processing method and plasma processing apparatus Download PDF

Info

Publication number
US8642478B2
US8642478B2 US13/214,372 US201113214372A US8642478B2 US 8642478 B2 US8642478 B2 US 8642478B2 US 201113214372 A US201113214372 A US 201113214372A US 8642478 B2 US8642478 B2 US 8642478B2
Authority
US
United States
Prior art keywords
high frequency
energy
plasma
power
ions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US13/214,372
Other languages
English (en)
Other versions
US20120214313A1 (en
Inventor
Yoshinobu Ooya
Akira Tanabe
Yoshinori Yasuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to US13/214,372 priority Critical patent/US8642478B2/en
Assigned to TOKYO ELECTRON LIMITED reassignment TOKYO ELECTRON LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OOYA, YOSHINOBU, TANABE, AKIRA, Yasuta, Yoshinori
Publication of US20120214313A1 publication Critical patent/US20120214313A1/en
Priority to US14/138,166 priority patent/US9478387B2/en
Application granted granted Critical
Publication of US8642478B2 publication Critical patent/US8642478B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • H01J37/32091Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/02Details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • H01J37/32137Radio frequency generated discharge controlling of the discharge by modulation of energy
    • H01J37/32155Frequency modulation
    • H01J37/32165Plural frequencies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32Processing objects by plasma generation
    • H01J2237/33Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334Etching
    • H01J2237/3343Problems associated with etching
    • H01J2237/3348Problems associated with etching control of ion bombardment energy

Definitions

  • the present disclosure relates to a technology of performing a plasma process onto a target substrate, and to be specific, the present disclosure relates to a plasma processing method and a plasma processing apparatus capable of applying a high frequency power for attracting ions toward a substrate positioned in a plasma space.
  • etching process a deposition process, an oxidation process, or a sputtering process for manufacturing a semiconductor device or a FPD (Flat Panel Display)
  • plasma in order to make an effective reaction of a processing gas at a relatively low temperature.
  • RF high frequency power
  • microwave a microwave in order to discharge or ionize a processing gas within a vacuum processing chamber.
  • an upper electrode and a lower electrode are arranged in parallel with each other within a processing chamber. Further, a target substrate (a semiconductor wafer, a glass substrate or the like) is mounted on the lower electrode, and a high frequency power having a frequency (typically, about 13.56 MHz or higher) suitable for generating plasma is applied to the upper electrode or lower electrode.
  • a high frequency electric field generated between the electrodes facing each other by applying the high frequency power accelerates electrons, and plasma is generated by a collision and ionization between the electrons and a processing gas.
  • a gas phase reaction or a surface reaction of radicals or ions contained in the plasma a thin film is deposited on the substrate, or a material or a thin film on a surface of the substrate is etched.
  • radicals and ions incident onto a substrate may be an important factor in a plasma process.
  • the ions are important in that the ions have a physical action by an impact when the ions are incident onto the substrate.
  • a RF bias method In a RF bias method, a high frequency power having a relatively low frequency (typically, about 13.56 MHz or lower) is applied to a lower electrode for mounting thereon a substrate. Also, ions contained in plasma are accelerated by a negative bias voltage or a sheath voltage generated on the lower electrode, and are attracted to the substrate. In this way, the ions in the plasma are accelerated and the ions collide with a surface of the substrate, so that a surface reaction, an anisotropic etching process or a film modification (film reform) can be promoted.
  • a RF bias method a high frequency power having a relatively low frequency (typically, about 13.56 MHz or lower) is applied to a lower electrode for mounting thereon a substrate.
  • ions contained in plasma are accelerated by a negative bias voltage or a sheath voltage generated on the lower electrode, and are attracted to the substrate. In this way, the ions in the plasma are accelerated and the ions collide with a surface of the substrate
  • a high frequency power for attracting ions applied to a lower electrode is used. Further, this high frequency power, and a self-bias voltage or a sheath voltage on the lower electrode are used as control parameters.
  • FIG. 19A low power
  • FIG. 19B intermediate power
  • FIG. 19C high power
  • the minimum energy is fixed to about 0 eV
  • the maximum energy is varied into about 1000 eV ( FIG. 19A ), about 2000 eV ( FIG. 19B ), and about 3000 eV ( FIG. 19C ) in proportion to the RF power.
  • FIG. 20A low power
  • FIG. 20B intermediate power
  • FIG. 20C high power
  • the maximum energy is varied into about 650 eV, about 1300 eV, and about 1950 eV in proportion to the RF power
  • the minimum energy is also varied into about 350 eV, about 700 eV, and about 1050 eV in proportion to the RF power.
  • FIGS. 19A to 19C and 20 A to 20 C show ion energy distribution characteristics of argon (Ar + ) ions, other ions may have the same characteristics (patterns).
  • the present disclosure provides a plasma processing method and a plasma processing apparatus capable of optimizing a plasma process in response to various requirements of a micro processing by effectively controlling a RF bias function.
  • a plasma processing method including: mounting a target substrate on a first electrode positioned within an evacuable processing chamber; generating plasma by exciting a processing gas within the processing chamber; applying to the first electrode a first high frequency power and a second high frequency power each having a different frequency in order to attract ions from the plasma toward the substrate; and performing a plasma process on the substrate by the plasma.
  • a total power and a power ratio of the first and second high frequency powers are controlled to optimize at least one process characteristic which is dependent on energy of ions incident onto the substrate.
  • a plasma processing apparatus including an evacuable processing chamber for accommodating a target substrate and loading/unloading the substrate; a processing gas supply unit for supplying a processing gas into the processing chamber; a plasma generation unit for generating plasma of the processing gas within the processing chamber; a first electrode for mounting and holding the substrate thereon within the processing chamber; a first high frequency power supply unit for applying to the first electrode a first high frequency power having a first frequency in order to attract ions from the plasma toward the substrate on the first electrode; a second high frequency power supply unit for applying to the first electrode a second high frequency power having a second frequency higher than the first frequency in order to attract ions from the plasma toward the substrate on the first electrode; and a control unit for controlling a total power and a power ratio of the first and second high frequency powers to optimize at least one process characteristic dependent on energy of ions incident onto the substrate from the plasma.
  • the first and second high frequency powers having the first and second frequencies, respectively, appropriate for attracting ions are applied to the first electrode for mounting thereon the target substrate, and a total power of the first and second high frequency powers and a power ratio thereof are variably controlled. Therefore, in an energy distribution of ions incident onto the substrate from the plasma, it is possible to control the minimum energy and the maximum energy independently of each other. Further, it is also possible for an ion energy distribution characteristic to have a concave shape or a flat shape. Accordingly, the ion energy distribution characteristic can be optimized with respect to various process characteristics, and also the process characteristics can be optimized.
  • a RF bias function can be effectively controlled by the above-described function and operation, so that a plasma process can be optimized in response to various requirements of a micro processing.
  • FIG. 1 is a cross-sectional view showing a configuration of a plasma processing apparatus in accordance with an embodiment of the present disclosure
  • FIG. 2 shows a waveform of a sheath voltage and an ion response voltage in a dual frequency RF bias method in the embodiment
  • FIG. 3 shows a conversion function employed in the embodiment
  • FIG. 4 shows an ion energy distribution and an ion response voltage in a single frequency RF bias method
  • FIG. 5 shows an ion energy distribution and an ion response voltage in a dual frequency RF bias method
  • FIG. 6A shows a function of adjusting the minimum energy of an ion energy distribution within a certain range as desired while the maximum energy is fixed in the embodiment
  • FIG. 6B shows a function of adjusting the minimum energy of an ion energy distribution within a certain range as desired while the maximum energy is fixed;
  • FIG. 6C shows a function of adjusting the minimum energy of an ion energy distribution within a certain range as desired while the maximum energy is fixed;
  • FIG. 7A shows a function of adjusting the maximum energy of an ion energy distribution within a certain range as desired while the minimum energy is fixed in the embodiment
  • FIG. 7B shows a function of adjusting the maximum energy of an ion energy distribution within a certain range as desired while the minimum energy is fixed;
  • FIG. 7C shows a function of adjusting the maximum energy of an ion energy distribution within a certain range as desired while the minimum energy is fixed;
  • FIG. 8A shows a function of varying a width of an energy band within a certain range as desired while a central value of energy is fixed in the embodiment
  • FIG. 8B shows a function of varying a width of an energy band within a certain range as desired while a central value (an average value) of energy is fixed;
  • FIG. 8C shows a function of varying a width of an energy band within a certain range as desired while an average value of energy is fixed;
  • FIG. 8D shows a function of varying a width of an energy band within a certain range as desired while an average value of energy is fixed;
  • FIG. 8E shows a function of varying a width of an energy band within a certain range as desired while an average value of energy is fixed;
  • FIG. 9 is a diagram for explaining a combination of frequencies in a dual frequency RF bias method of the embodiment.
  • FIG. 10 is a longitudinal cross-sectional view schematically showing an etching process in a HARC process
  • FIG. 11A is a graph showing an etching rate and a thickness of a CF polymer film when a flow rate of a C 4 F 8 gas is changed in an etching process for a SiO 2 film;
  • FIG. 11B is a graph showing an etching rate and a thickness of a CF polymer film when a flow rate of a C 4 F 8 gas is changed in an etching process for a SiN film;
  • FIGS. 12A and 12B are longitudinal cross-sectional views each schematically showing a necking in a HARC process
  • FIGS. 13A and 13B show ion energy dependency of an etching yield of an oxide film and an organic film in a HARC process, and also show an ion energy distribution characteristic by a conventional single frequency RF bias method;
  • FIGS. 14A and 14B show ion energy dependency of an etching yield of an oxide film and an organic film in a HARC process, and also show an ion energy distribution characteristic by a dual frequency RF bias method of the embodiment;
  • FIG. 15 shows an incident angle when ions are incident onto each position of a mask (an organic film) in a HARC process
  • FIG. 16 shows cross-sectional shapes of a pattern and characteristic data obtained in a HARC process performed by a dual frequency RF bias method
  • FIG. 17 shows (an enlarged view of) cross-sectional shapes of a pattern and characteristic data obtained in a HARC process performed by a dual frequency RF bias method
  • FIG. 18 is a longitudinal cross-sectional view showing a configuration of a plasma processing apparatus in accordance with another embodiment
  • FIG. 19A shows an ion energy distribution obtained by setting a RF power to be low in a conventional signal frequency RF bias method using a relatively low frequency
  • FIG. 19B shows an ion energy distribution obtained by setting a RF power to be intermediate level in a conventional signal frequency RF bias method using a relatively low frequency
  • FIG. 19C shows an ion energy distribution obtained by setting a RF power to be high in a conventional signal frequency RF bias method using a relatively low frequency
  • FIG. 20A shows an ion energy distribution obtained by setting a RF power to be low in a conventional signal frequency RF bias method using a relatively high frequency
  • FIG. 20B shows an ion energy distribution obtained by setting a RF power to be intermediate level in a conventional signal frequency RF bias method using a relatively high frequency
  • FIG. 20C shows an ion energy distribution obtained by setting a RF power to be high in a conventional signal frequency RF bias method using a relatively high frequency.
  • FIG. 1 shows a configuration of a plasma processing apparatus in accordance with an embodiment of the present disclosure.
  • This plasma processing apparatus may be configured as a capacitively coupled plasma etching apparatus in which two radio frequency powers are applied to a lower electrode or a radio frequency power is applied to an upper electrode.
  • the plasma processing apparatus may include a cylindrical vacuum chamber (processing vessel) 10 made of, e.g., aluminum whose surface is alumite-treated (anodically oxidized).
  • the chamber 10 may be frame-grounded.
  • a cylindrical susceptor support 14 may be provided via an insulating plate 12 made of ceramic or the like, and on the susceptor support 14 , a susceptor 16 made of, for example, aluminum may be provided.
  • the susceptor 16 may serve as a lower electrode and a target substrate, for example, a semiconductor wafer W may be mounted thereon.
  • an electrostatic chuck 18 for holding the semiconductor wafer W by electrostatic attracting force may be provided.
  • This electrostatic chuck 18 may include an electrode 20 made of a conductive film embedded between a pair of insulating layers or insulating sheets, and the electrode 20 may be electrically connected to a DC power supply 22 via a switch 24 .
  • the semiconductor wafer W can be attracted to and held on the electrostatic chuck 18 by an electrostatic force caused by a DC voltage from the DC power supply 22 .
  • a focus ring 26 made of, for example, silicon may be positioned in order to enhance uniformity of an etching process in the surface.
  • a cylindrical inner wall member 28 made of, for example, quartz may be secured.
  • a coolant cavity or coolant path 30 of, e.g., a circular ring-shape may be formed.
  • a coolant such as cooling water cw of a certain temperature may be supplied into and circulated through the coolant path 30 from an external chiller unit (not illustrated) via lines 32 a and 32 b .
  • a processing temperature of the semiconductor wafer W on the susceptor 16 can be controlled depending on a temperature of the coolant cw.
  • a heat transfer gas such as a He gas may be supplied between an upper surface of the electrostatic chuck 18 and a rear surface of the semiconductor wafer W from a heat transfer gas supply mechanism (not illustrated) via a gas supply line 34 .
  • the susceptor 16 may be electrically connected to a first high frequency power supply 36 and a second high frequency power supply 38 for attracting ions via lower matching units 40 and 42 and lower power supply conductors 44 and 46 , respectively.
  • the lower power supply conductors 44 and 46 may be configured as a common conductor such as a power supply rod.
  • the first high frequency power supply 36 may be configured to variably output a first high frequency power RF L1 having a relatively low frequency of, for example, about 0.8 MHz suitable for attracting ions of plasma to the semiconductor wafer W on the susceptor 16 .
  • the second high frequency power supply 38 may be configured to variably output a second high frequency power RF L2 having a relatively high frequency of, for example, about 13 MHz suitable for attracting ions of plasma to the semiconductor wafer W on the susceptor 16 .
  • an upper electrode 48 may be provided so as to face the susceptor 16 in parallel with each other.
  • This upper electrode 48 may include an electrode plate 50 and an electrode support 52 , and may be secured at an upper space of the chamber 10 via a ring-shaped insulator 54 .
  • the electrode plate 50 may have a multiple number of gas discharge holes 50 a and may be made of a semiconductor material such as Si or SiC.
  • the electrode support 52 may be made of a conductive material such as aluminum whose surface is alumite-treated (anodically oxidized) for supporting the electrode plate 50 so as to be detachably attached thereto. Between this upper electrode 48 and the susceptor 16 , a plasma generation space or a processing space PS is formed.
  • the ring-shaped insulator 54 may be made of, for example, alumina (Al 2 O 3 ). Further, the ring-shaped insulator 54 may airtightly fill up a gap between a side surface of the upper electrode 48 and a sidewall of the chamber 10 , and physically support the upper electrode 48 without being grounded.
  • the electrode support 52 may include a gas buffer room 56 therein and a multiple number of gas vent holes 52 a configured to communicate the gas buffer room 56 with the gas discharge holes 50 a of the electrode plate 50 at its lower surface.
  • the gas buffer room 56 may be connected to a processing gas supply source 60 via a gas supply line 58 , and a mass flow controller (MFC) 62 and an opening/closing valve 64 may be provided at the gas supply line 58 . If a certain processing gas is introduced into the gas buffer room 56 from the processing gas supply source 60 , the processing gas may be electrically discharged to the processing space PS from the gas discharge holes 50 a of the electrode plate 50 toward the semiconductor wafer W on the susceptor 16 , as in a shower device. As described above, the upper electrode 48 may serve as a shower head for supplying the processing gas to the processing space PS.
  • the upper electrode 48 may be electrically connected to a third high frequency power supply 66 for plasma excitation via an upper matching unit 68 and an upper power supply conductor such as a power supply rod 70 .
  • the third high frequency power supply 66 may be configured to variably output a third high frequency power RF H having a frequency of, for example, about 60 MHz suitable for high frequency discharge of the processing gas by capacitive coupling, i.e. suitable for generating plasma.
  • a frequency of the third high frequency power RF H for generating plasma may be selected from a range of from about 27 MHz to about 300 MHz.
  • An annular space formed between the susceptor 16 and the sidewall of the chamber 10 and between the susceptor support 14 and the sidewall of the chamber 10 may serve as a gas exhaust space, and at the bottom of this gas exhaust space, a gas exhaust port 72 of the chamber 10 may be formed.
  • This gas exhaust port 72 may be connected to a gas exhaust device 76 via a gas exhaust line 74 .
  • the gas exhaust device 76 may include a vacuum pump such as a turbo molecular pump and may be configured to depressurize the inside of the chamber 10 , particularly, the processing space PS to a required vacuum level.
  • a gate valve 80 configured to open and close a loading/unloading port 78 for the semiconductor wafer W may be provided.
  • An output terminal of a variable DC power supply 82 provided outside the chamber 10 may be electrically connected to the upper electrode 48 via a switch 84 and a DC power supply line 85 .
  • the variable DC power supply 82 may be configured to output a DC voltage V DC ranging from, for example, about ⁇ 2000 V to about +1000 V.
  • a filter circuit 86 provided on the way of the DC power supply line 85 may apply the DC voltage V DC from the variable DC power supply 82 to the upper electrode 48 . Further, the filter circuit 86 may allow a high frequency power supplied to the DC power supply line 85 from the susceptor 16 via the processing space PS and the upper electrode 48 to flow through a ground line but not to flow toward the variable DC power supply 82 .
  • a DC ground part made of a conductive material such as Si or SiC may be provided.
  • This DC ground part may be constantly grounded via a ground line (not illustrated).
  • a control unit 88 may include a micro computer and may individually and overall control operations of respective parts of the plasma etching apparatus, for example, the switch 24 for the electrostatic chuck, the first, second and third high frequency power supplies 36 , 38 and 66 , the matching units 40 , 42 and 68 , the processing gas supply unit 60 , 62 and 64 , the gas exhaust device 76 , the variable DC power supply 82 and the switch 84 for DC bias, the chiller unit, and the heat transfer gas supply unit. Further, the control unit 88 may be connected to a touch panel (not shown) serving as a man-machine interface and storage unit (not shown) for storing therein various program or data such as preset values. Furthermore, in the present embodiment, the control unit 88 and a DC controller 83 serve as a DC bias control unit.
  • the gate valve 80 is opened, and the semiconductor wafer W as a target to be processed is loaded into the chamber 10 and mounted on the electrostatic chuck 18 .
  • a certain processing gas i.e. an etching gas (generally, a mixed gas)
  • a certain processing gas i.e. an etching gas (generally, a mixed gas)
  • the inside of the chamber 10 may be vacuum exhausted to a preset pressure level by the gas exhaust device 76 .
  • the third high frequency power RF H 60 MHz
  • the third high frequency power RF H 60 MHz
  • the third high frequency power RF H 60 MHz
  • the first high frequency power RF L1 (0.8 MHz) and second high frequency power RF L2 (13 MHz) for attracting ions may be respectively applied from the first and second high frequency power supplies 36 and 38 with a certain power level to the susceptor (lower electrode) 16 .
  • the switch 24 may be turned on, and a heat transfer gas (a He gas) may be confined in a contact interface between the electrostatic chuck 18 and the semiconductor wafer W by electrostatic attraction force.
  • the switch 84 may be turned on, and a certain DC voltage V DC may be applied from the variable DC power supply 82 to the upper electrode 48 .
  • the etching gas discharged from the shower head (upper electrode) 48 may be excited into plasma between both electrodes 16 and 48 by high frequency discharge, and a film on a main surface of the semiconductor wafer W may be etched by radicals or ions contained in the plasma.
  • the plasma etching apparatus of this embodiment may include hardware 36 to 46 in which two kinds of high frequency powers RF L1 (0.8 MHz) and RF L2 (13 MHz) suitable for attracting ions are applied to the susceptor 16 from the two high frequency power supplies 36 and 38 .
  • the control unit 88 may control a total power of both high frequency powers RF L1 and RF L2 and a power ratio thereof depending on specifications, conditions or recipes of an etching process.
  • the first high frequency power RF L1 (0.8 MHz) and the second high frequency power RF L2 (13 MHz) for attracting ions may be applied to the susceptor (lower electrode) 16 from the first high frequency power supply 36 and the second high frequency power supply 38 , respectively, during the process.
  • a negative sheath voltage V s (t) in which both high frequency powers RF L1 and RF L2 are applied may be generated in an ion sheath on a surface of the semiconductor wafer W or the susceptor 16 in contact with the plasma generation space PS.
  • Ions from the plasma may be accelerated by the sheath voltage V s (t) and incident onto the surface of the semiconductor wafer W.
  • acceleration or energy of the incident ions may depend on an instantaneous value (absolute value) of the sheath voltage V s (t) at that moment.
  • ions introduced into the ion sheath when the instantaneous value (absolute value) of the sheath voltage V s (t) is high may be incident onto the surface of the wafer W with high acceleration or high kinetic energy
  • ions introduced into the ion sheath when the instantaneous value (absolute value) of the sheath voltage V s (t) is low may be incident onto the surface of the wafer W with low acceleration or low kinetic energy.
  • the ions within the ion sheath may respond (accelerate) to the sheath voltage V s (t) with specific sensitivity equal to or less than about 100% (coefficient of 1).
  • This response sensitivity or a conversion function ⁇ (f) may vary depending on (in inverse proportion to) a frequency f of a high frequency power used for RF bias as depicted in FIG. 3 , and may be expressed by the following equation (1).
  • ⁇ ( f ) 1/ ⁇ ( cf ⁇ i ) p +1 ⁇ 1/p (1)
  • V i (t) a net sheath voltage, i.e. an ion response voltage V i (t), contributing to the acceleration of the ions within the ion sheath
  • V i ( t ) ⁇ ( f ) V s ( t ) (2)
  • FIGS. 2 and 3 respectively show the ion response voltage V i (t) and the conversion function ⁇ (f) of Ar + ions.
  • V i (t) the sheath voltage
  • V s (t) the sheath voltage
  • RF bias the frequency for RF bias
  • the ions within the ion sheath may respond (accelerate) to the first high frequency power RF L1 (0.8 MHz) having a relatively low frequency with sensitivity of about 100% ( ⁇ (f) ⁇ 1). Further, ions within the ion sheath may respond (accelerate) to the second high frequency power RF L2 (13 MHz) having a relatively high frequency with sensitivity of about 50% ( ⁇ (f) ⁇ 0.5).
  • an ion energy distribution (IED) can be calculated from the following equation (3) in the manner as depicted in FIGS. 4 and 5 .
  • FIG. 4 shows an IED and an ion response voltage V i (t) when a single high frequency power having a relatively low frequency is used for RF bias.
  • FIG. 5 shows an IED and an ion response voltage V i (t) when two high frequency powers each having a relatively low frequency or a relatively high frequency are used for RF bias.
  • an ion energy distribution has a shape that lots of ions are concentrated (peaks are shown) in the vicinity of the maximum energy and in the vicinity of the minimum energy, and it may be impossible to vary the minimum energy as desired even if a RF power varies in any way.
  • the minimum energy can be adjusted in a range of, for example, from about 0 eV to about 1000 eV as desired.
  • the maximum energy can be adjusted in a range of, for example, from about 650 eV to about 2650 eV as desired.
  • FIGS. 6A to 6C and FIGS. 7A to 7C show the IED characteristics of Ar + ions, but other ions may have the same characteristics with respect to the IED patterns. Further, each voltage value of the both high frequency powers RF L1 (0.8 MHz) and RF L2 (13 MHz) corresponds to an amplitude value of each bias voltage of the both high frequency powers and may be converted into RF powers.
  • the present embodiment it may be possible to obtain intermediate IED characteristics by adjusting the width E w of the energy band, as desired, between an IED characteristic ( FIG. 8A ) when only the first high frequency power RF L1 (0.8 MHz) for RF bias is used and an IED characteristic ( FIG. 8E ) when only the second high frequency power RF L2 (13 MHz) for RF bias is used.
  • This concave-shaped IED characteristic may be different from a U-shaped IED characteristic ( FIGS. 8A and 8 E) showing that ions are concentrated on a narrow line at the minimum energy and the maximum energy as in case where any one of the both high frequency powers RF L1 and RF L2 for RF bias is used.
  • the first high frequency power RF L1 and the second high frequency power RF L2 each having a different frequency may be used as a RF bias power. Further, a total power and/or a power ratio of these high frequency powers may be adjusted. Accordingly, an energy band width and a distribution shape of the ion energy distribution (IED) of the ions incident onto the surface of the semiconductor wafer W on the susceptor 16 can be controlled in various ways.
  • IED ion energy distribution
  • the first high frequency power RF L1 and the second high frequency power RF L2 are not limited to the above-described values (0.8 MHz and 13 MHz, respectively), and can be set from a certain range as desired.
  • a width (an energy band) E w of an ion energy distribution may become wider as a frequency becomes high and may become narrower as a frequency becomes low.
  • This relationship corresponds to a relationship between a frequency and a conversion function ⁇ (f) as depicted in FIG. 9 . Therefore, in order to increase a variable range of the energy band width E w , it depends on a kind of an ion (F + , Ar + , C 4 F 6 + or the like) mainly acting in an etching process.
  • the first high frequency power RF L1 needs to have a relatively low frequency (for example, about 100 kHz to about 6 MHz) and the second high frequency power RF L2 needs to have a relatively high frequency (for example, about 6 MHz to about 40 MHz).
  • the second high frequency power RF L2 needs to have a frequency of about 40 MHz or lower.
  • the plasma etching apparatus of the present embodiment can remarkably improve controllability of a RF bias function, and in particular, high performance in anisotropic etching can be achieved as compared with the conventional apparatus.
  • the HARC process may be an etching process for forming a narrow and deep contact hole (or a via hole) 92 in an insulating film or an oxide film (typically, a SiO 2 film). Further, the HARC has been used for contact etching (or via hole etching) for a BEOL (Back End of Line) in a manufacturing process of a large-scale integrated circuit.
  • an anisotropic shape of high precision and a high selectivity with respect to a mask 94 (and an underlying film 96 ) may be required in order to form the fine hole 92 of a high aspect ratio.
  • a method of performing a vertical etching process by vertically attracting ions such as CF x + or Ar + into the hole 92 of the SiO 2 film 90 by RF bias while a fluorocarbon-based gas is used as an etchant gas and a polymer film as a sidewall protective film is deposited on the mask 94 and a sidewall 98 of the hole 92 of the SiO 2 film 90 with CF x radicals.
  • F radicals having chemically high activity may reduce anisotropy and selectivity
  • a gas such as C 4 F 8 , C 5 F 8 or C 4 F 6 generating fewer F radicals and having a high C/F ratio has been widely used.
  • the requirements (4) and (5) related to the selectivity may be based on the following etching mechanism. That is, in a normal etching state, fluorocarbon radicals are constantly irradiated onto a surface of a SiO 2 film, and thus, a CF film having multi-molecular layers may be formed on the surface of the SiO 2 film. A thickness of this CF film may have a close relationship with an etching rate.
  • FIGS. 11A and 11B show that, in case of using a mixed gas of C 4 F 8 /Ar/O 2 as an etching gas, each etching rate of a SiO 2 film and a SiN film, and thicknesses of CF polymer films deposited on these films while a flow rate of a C 4 F 8 gas is varied and a flow rate of each of an Ar gas and an O 2 gas is fixed.
  • an etching rate (E/R) is increased up to about 11 sccm as a maximum value. Thereafter, the etching rate (E/R) is decreased in inverse proportion to an increase in a thickness of the CF film, and is scarcely changed at about 22 sccm or more.
  • the thickness of the CF film on the SiO 2 film is as thin as about 1 nm since oxygen released during the etching process for the SiO 2 film reacts with the CF film and produce a volatile material (i.e. remove the CF film).
  • a thickness of the CF film on the SiN film is as thick as about 5 nm, so that the etching can be suppressed.
  • the O 2 gas as an additive gas may adjust a removing rate of the CF film.
  • a SiN film may be used as the underlying film 96 and typically, an organic film may be used as the mask 94 .
  • an etching rate and a thickness of the CF film when a flow rate of the C 4 F 8 gas is varied under the same conditions as described above, the same characteristics as the SiN film can be seen in a case where the organic film is used as the mask 94 .
  • a difference in a thickness of the CF film (a difference in an etching rate) based on whether or not oxygen is released during an etching process or based on a difference in amount of released oxygen.
  • a flow rate ratio of O 2 /C 4 F 8 may be adjusted, and also [5] F atom radicals that deteriorates the selectivity may be reduced by addition of Ar (i.e. a total gas flow rate is increased). Accordingly, it may be possible to sufficiently increase the selectivity of the SiO 2 film with respect to the SiN film as the underlying film 96 or the organic film (which may include photoresist as an upper layer) as the mask 94 .
  • a plasma etching apparatus by using respective methods of adjusting [1] a high frequency power for generating plasma, [2] a flow rate of a fluorocarbon gas (for example, C 4 F 8 ), [3] a high frequency power for attracting ions, [4] a flow rate ratio of O 2 /C 4 F 8 (particularly, a flow rate of O 2 ), and [5] a flow rate of Ar, it may be possible to achieve a high etching rate and high selectivity in a HARC process. However, since very high selectivity is required in the HARC process, a very high deposition rate needs to be considered, so that radicals having a high adhesion rate needs be used.
  • coatability (coverage) of a deposition film 100 on the sidewall 98 may deteriorate and an entrance of the hole 92 may become narrow, and, thus, a necking 100 may be caused easily. If the necking 100 is caused, radicals or ions may not be sufficiently attracted to the bottom of the hole 92 . Therefore, a decrease in a CD (Critical Dimension) of the bottom of the hole or a decrease in a vertical etching rate of the hole bottom. Further, incident ions may be reflected from an upper portion of the necking 100 , and a bowing of the sidewall 98 may occur in a lower portion of the necking 100 .
  • radicals having a high adhesion rate C x F y radicals
  • such radicals may easily cause the necking 100 .
  • radicals having a low adhesion rate are used to avoid the necking 100 , the deposition film 100 on the mask 94 may become too thin as depicted in FIG. 12A and thus high selectivity cannot be achieved.
  • FIG. 13A shows etching yield characteristics of an oxide film (SiO 2 ) and an organic film with respect to energy of incident ions when radicals having a high adhesion rate are used in a HARC process.
  • a surface of the mask (organic film) may be protected by a deposition film at a low ion energy band and only the oxide film may be selectively etched.
  • the ion energy band becomes higher than a certain threshold value E t , physical etching by means of irradiation of ions exceeds the protection of the deposition film, and, thus the mask (organic film) becomes etched.
  • the etching yield of the oxide film is increased slowly.
  • an ion energy distribution need to have a shape where ions are concentrically distributed at an energy band near the threshold value E t , as shown in FIG. 13B .
  • an ion energy distribution is arranged entirely in a range lower than the threshold value E t .
  • ions concentrated in the vicinity of the minimum energy may hardly contribute to the etching for the oxide film.
  • high selectivity may be achieved by means of ions concentrated in the vicinity of the maximum energy, the above-described necking 100 cannot be avoided or prevented.
  • ions are distributed concentrically at the first energy band, so that high selectivity can be obtained. Further, ions are distributed concentrically at the second energy band, so that the necking 100 can be efficiently avoided or prevented.
  • the present inventors have conducted an experiment of the HARC process by the plasma etching apparatus of the present embodiment while varying a power ratio of the first high frequency power RF L1 (0.8 MHz) and the second high frequency power RF L2 (13 MHz) and comparing the relevant etching characteristics. Experiment results as shown in FIGS. 16 and 17 are obtained.
  • main etching conditions are as follows:
  • Diameter of wafer 300 mm
  • a total power of the first high frequency power RF L1 (0.8 MHz) and the second high frequency power RF L2 (13 MHz) for attracting ions has been fixed (at about 4500 W). Further, a power ratio as a parameter has been selected from six examples from 4500/0 W to 0/4500 W.
  • the trade-off problem in the HARC process can be readily solved. Further, in accordance with the dual frequency bias method of the present disclosure, it may be also possible to solve a trade-off between selectivity and a top CD/a bowing CD/a bottom CD in an etching process for forming a hole and a trade-off between a deposition rate and a seamless shape in plasma CVD.
  • the DC voltage V DC from the variable DC power supply 82 is applied to the upper electrode 48 .
  • the appropriate DC voltage V DC particularly, the DC voltage V DC having an appropriate magnitude (absolute value)
  • etching resistance of a photoresist film (particularly, an ArF resist film) used as a mask in the plasma etching process can be improved.
  • the DC voltage V DC as a negative high voltage (desirably, a negative voltage having an absolute value higher than an absolute value of a self-bias voltage generated on the upper electrode 48 by applying the third high frequency power RF H ) is applied to the upper electrode 48 from the variable DC power supply 82 , an upper ion sheath formed between the upper electrode 48 and the plasma may become thick. Accordingly, ions in the plasma are accelerated in an electric field of the upper ion sheath, and, thus, ion impact energy when the ions collide with the electrode plate 50 of the upper electrode 48 may be increased. As a result, secondary electrons released from the electrode plate 50 by a ⁇ electric discharge may be increased.
  • the secondary electrons released from the electrode plate 50 may be accelerated in a direction opposite to the direction of the ions in the electric field of the upper ion sheath, and may pass through the plasma PR. Thereafter, the secondary electrons pass through a lower ion sheath and then may be introduced, with a certain high energy, into a resist mask on the surface of the semiconductor wafer W on the susceptor 16 . If a polymer of the resist mask absorbs the energy of the electrons, a change in composition or structure and a cross-linking reaction may be made. As a result, a modification (reform) layer may be formed and the etching resistance (plasma resistance) may be increased. As the absolute value of the negative DC voltage V DC applied to the upper electrode 48 is increased, the energy of the electrons introduced into the resist mask can be increased, and the etching resistance in the resist mask can also be increased.
  • the plasma etching apparatus of the present embodiment by applying to the susceptor 16 the first high frequency power RF L1 and the second high frequency power RF L2 each having a different frequency as RF bias powers and by controlling the total power and/or the power ratio of these high frequency powers, in the ion energy distribution (IED) of the ions incident onto the surface of the semiconductor wafer W on the susceptor 16 , the width of the energy band, the distribution shape and the total amount of ion incident energy can be controlled in various manners.
  • IED ion energy distribution
  • the number of incident ions at the intermediate energy band in the ion energy distribution (IED) may be rapidly increased. Accordingly, the total amount of ion incident energy can be increased. However, if the total amount of ion incident energy is increased, the resist mask may be damaged, so that a surface of the resist mask may become rough. Further, uneven deformation or zigzag-shaped deformation of so-called LER (Line Edge Roughness) or LWR (Line Width Roughness) may easily occur.
  • LER Line Edge Roughness
  • LWR Line Width Roughness
  • the control unit 88 may calculate (estimate roughly) the total amount of ion incident energy based on the total power and the power ratio of the first high frequency power RF L1 and the second high frequency power RF L2 . If the total amount of ion incident energy is large, the control unit 88 may increase, through the DC controller 83 , the absolute value of the negative DC voltage V DC applied to the upper electrode 48 so as to improve the etching resistance of the resist mask. However, if the total amount of ion incident energy is small, it is preferable to control the absolute value of the negative DC voltage V DC applied to the upper electrode 48 to be small for the reason that needs for improving the etching resistance of the resist mask are decreased and for the following reason.
  • the electrode plate 50 of the upper electrode 48 is made of a conductive material containing Si, the same reaction may occur on a surface of the electrode plate 50 as well as the surface of the semiconductor wafer W, and, thus, the reactant species may be consumed on the both surfaces.
  • V DC negative DC voltage
  • an etching reaction i.e. consumption of the reactant species
  • an etching rate on the surface of the semiconductor wafer W can be decreased and the deposition may be increased.
  • the control unit 88 controls, through the DC controller 83 , the absolute value of the negative DC voltage V DC applied to the upper electrode 48 to be relatively low.
  • the third high frequency power RF H for generating plasma output from the third high frequency power supply 66 has been applied to the upper electrode 48 .
  • the third high frequency power supply 66 and the matching unit 68 may be electrically connected to the susceptor (lower electrode) 16 and the third high frequency power RF H for generating plasma may be applied to the susceptor 16 .
  • the above-described embodiment is related to a capacitively coupled plasma processing apparatus in which plasma may be generated by high frequency discharge between parallel plate electrodes in a chamber.
  • the present disclosure may be applied to an inductively coupled plasma etching apparatus in which plasma may be generated under an inductive electromagnetic field of a high frequency power by arranging an antenna on an upper surface of a chamber or around the chamber.
  • the present disclosure may be applied to a microwave plasma processing apparatus in which plasma may be generated by using a power of microwave.
  • the present disclosure is not limited to a plasma etching apparatus and can be applied to other plasma processing apparatus for plasma CVD, plasma oxidation, plasma nitrification, sputtering or the like.
  • the target substrate of the present disclosure is not limited to a semiconductor wafer and may include various substrates for a flat panel display, an EL device or a solar cell, or a photomask, a CD substrate, or a print substrate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Plasma Technology (AREA)
US13/214,372 2010-08-23 2011-08-22 Plasma processing method and plasma processing apparatus Expired - Fee Related US8642478B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/214,372 US8642478B2 (en) 2010-08-23 2011-08-22 Plasma processing method and plasma processing apparatus
US14/138,166 US9478387B2 (en) 2010-08-23 2013-12-23 Plasma processing apparatus

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2010-186017 2010-08-23
JP2010186017 2010-08-23
US38255210P 2010-09-14 2010-09-14
JP2011-171005 2011-08-04
JP2011171005A JP5916056B2 (ja) 2010-08-23 2011-08-04 プラズマ処理方法及びプラズマ処理装置
US13/214,372 US8642478B2 (en) 2010-08-23 2011-08-22 Plasma processing method and plasma processing apparatus

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/138,166 Division US9478387B2 (en) 2010-08-23 2013-12-23 Plasma processing apparatus

Publications (2)

Publication Number Publication Date
US20120214313A1 US20120214313A1 (en) 2012-08-23
US8642478B2 true US8642478B2 (en) 2014-02-04

Family

ID=44680977

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/214,372 Expired - Fee Related US8642478B2 (en) 2010-08-23 2011-08-22 Plasma processing method and plasma processing apparatus
US14/138,166 Active 2032-01-13 US9478387B2 (en) 2010-08-23 2013-12-23 Plasma processing apparatus

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/138,166 Active 2032-01-13 US9478387B2 (en) 2010-08-23 2013-12-23 Plasma processing apparatus

Country Status (6)

Country Link
US (2) US8642478B2 (ja)
EP (1) EP2423944B1 (ja)
JP (1) JP5916056B2 (ja)
KR (1) KR101841585B1 (ja)
CN (2) CN104599930B (ja)
TW (2) TWI587379B (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140083977A1 (en) * 2012-09-26 2014-03-27 Kabushiki Kaisha Toshiba Plasma processing apparatus and plasma processing method
US20190221437A1 (en) * 2018-01-18 2019-07-18 Applied Materials, Inc. Etching apparatus and methods
US11328903B2 (en) 2020-05-07 2022-05-10 Samsung Electronics Co., Ltd. Plasma processing system, method of controlling plasma in the plasma processing system, and method of manufacturing semiconductor device by using the method of controlling the plasma

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102133057B1 (ko) * 2012-06-22 2020-07-10 램 리써치 코포레이션 플라즈마 프로세싱 시스템에서의 제어를 위한 방법 및 장치
CN103037613B (zh) * 2012-12-07 2016-01-20 常州中科常泰等离子体科技有限公司 全自动冷等离子体种子处理器控制系统
CN103887146B (zh) * 2012-12-19 2016-08-31 中微半导体设备(上海)有限公司 利用可切换功率发生器的高深宽比微结构刻蚀方法
JP2014225501A (ja) 2013-05-15 2014-12-04 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
WO2015019765A1 (ja) 2013-08-09 2015-02-12 東京エレクトロン株式会社 プラズマ処理装置及びプラズマ処理方法
JP6140575B2 (ja) * 2013-08-26 2017-05-31 東京エレクトロン株式会社 半導体装置の製造方法
JP6170378B2 (ja) * 2013-08-29 2017-07-26 東京エレクトロン株式会社 エッチング方法
CN104538341B (zh) * 2014-12-17 2017-06-27 中国地质大学(北京) 一种真空腔室静电卡盘调节装置
US9824896B2 (en) * 2015-11-04 2017-11-21 Lam Research Corporation Methods and systems for advanced ion control for etching processes
US10622217B2 (en) * 2016-02-04 2020-04-14 Samsung Electronics Co., Ltd. Method of plasma etching and method of fabricating semiconductor device using the same
JP6670697B2 (ja) * 2016-04-28 2020-03-25 東京エレクトロン株式会社 プラズマ処理装置
JP6446418B2 (ja) * 2016-09-13 2018-12-26 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置およびプログラム
KR102227783B1 (ko) * 2016-12-27 2021-03-16 에바텍 아크티엔게젤샤프트 진공 플라즈마 작업편 처리 장치
JP6861535B2 (ja) * 2017-02-28 2021-04-21 東京エレクトロン株式会社 処理方法及びプラズマ処理装置
JP2018206913A (ja) * 2017-06-02 2018-12-27 東京エレクトロン株式会社 部材及びプラズマ処理装置
KR102475069B1 (ko) * 2017-06-30 2022-12-06 삼성전자주식회사 반도체 제조 장치, 이의 동작 방법
US10312055B2 (en) * 2017-07-26 2019-06-04 Asm Ip Holding B.V. Method of depositing film by PEALD using negative bias
JP2019102483A (ja) * 2017-11-28 2019-06-24 東京エレクトロン株式会社 エッチング方法およびエッチング装置
US10714329B2 (en) * 2018-09-28 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Pre-clean for contacts
US20200286757A1 (en) * 2019-03-08 2020-09-10 Dsgi Technologies, Inc. Apparatus for annealing semiconductor integrated circuit wafers
CN112119485B (zh) * 2019-04-22 2024-01-02 株式会社日立高新技术 等离子处理方法
CN112017931B (zh) * 2019-05-30 2022-03-22 北京北方华创微电子装备有限公司 应用于等离子体系统的方法及相关等离子体系统
KR20220010648A (ko) 2020-07-16 2022-01-26 삼성전자주식회사 플라즈마 식각 장치, 플라즈마 식각 방법 및 그를 포함하는 반도체 소자의 제조 방법

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07302786A (ja) 1994-04-28 1995-11-14 Tokyo Electron Ltd プラズマ処理装置
US20050039682A1 (en) 2003-08-22 2005-02-24 Raj Dhindsa Multiple frequency plasma etch reactor
US20050090118A1 (en) * 2003-10-28 2005-04-28 Applied Materials, Inc. Plasma control using dual cathode frequency mixing
US20070029194A1 (en) 2005-03-31 2007-02-08 Naoki Matsumoto Capacitive coupling plasma processing apparatus and method
US20070087455A1 (en) * 2005-10-18 2007-04-19 Applied Materials, Inc. Independent control of ion density, ion energy distribution and ion dissociation in a plasma reactor
US20070247074A1 (en) * 2006-04-24 2007-10-25 Alexander Paterson Process using combined capacitively and inductively coupled plasma sources for controlling plasma ion radial distribution
US20080236750A1 (en) * 2007-03-27 2008-10-02 Tokyo Electron Limited Plasma processing apparatus
US20130087284A1 (en) * 2008-07-17 2013-04-11 Lam Research Corporation Organic line width roughness with h2 plasma treatment

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050061445A1 (en) * 1999-05-06 2005-03-24 Tokyo Electron Limited Plasma processing apparatus
US20040025791A1 (en) * 2002-08-09 2004-02-12 Applied Materials, Inc. Etch chamber with dual frequency biasing sources and a single frequency plasma generating source
US7625460B2 (en) * 2003-08-01 2009-12-01 Micron Technology, Inc. Multifrequency plasma reactor
US7510665B2 (en) * 2003-08-15 2009-03-31 Applied Materials, Inc. Plasma generation and control using dual frequency RF signals
US7517801B1 (en) * 2003-12-23 2009-04-14 Lam Research Corporation Method for selectivity control in a plasma processing system
CN1983518B (zh) * 2004-06-21 2011-06-08 东京毅力科创株式会社 等离子体处理装置和方法
US7988816B2 (en) 2004-06-21 2011-08-02 Tokyo Electron Limited Plasma processing apparatus and method
US7829471B2 (en) * 2005-07-29 2010-11-09 Applied Materials, Inc. Cluster tool and method for process integration in manufacturing of a photomask
KR100878467B1 (ko) * 2006-06-05 2009-01-14 삼성전자주식회사 반도체 기판 처리장치
JP2008053507A (ja) * 2006-08-25 2008-03-06 Matsushita Electric Ind Co Ltd ドライエッチング方法
US20080099450A1 (en) * 2006-10-30 2008-05-01 Applied Materials, Inc. Mask etch plasma reactor with backside optical sensors and multiple frequency control of etch distribution
KR100978886B1 (ko) * 2007-02-13 2010-08-31 가부시키가이샤 히다치 하이테크놀로지즈 플라즈마처리방법 및 플라즈마처리장치
JP5014166B2 (ja) * 2007-02-13 2012-08-29 株式会社日立ハイテクノロジーズ プラズマ処理方法およびプラズマ処理装置
KR101500995B1 (ko) * 2008-11-06 2015-03-18 삼성전자 주식회사 플라즈마 식각장치
US8383001B2 (en) * 2009-02-20 2013-02-26 Tokyo Electron Limited Plasma etching method, plasma etching apparatus and storage medium
JP2011228436A (ja) * 2010-04-19 2011-11-10 Hitachi High-Technologies Corp プラズマ処理装置およびプラズマ処理方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07302786A (ja) 1994-04-28 1995-11-14 Tokyo Electron Ltd プラズマ処理装置
US20050039682A1 (en) 2003-08-22 2005-02-24 Raj Dhindsa Multiple frequency plasma etch reactor
US20050090118A1 (en) * 2003-10-28 2005-04-28 Applied Materials, Inc. Plasma control using dual cathode frequency mixing
US20070029194A1 (en) 2005-03-31 2007-02-08 Naoki Matsumoto Capacitive coupling plasma processing apparatus and method
US20070087455A1 (en) * 2005-10-18 2007-04-19 Applied Materials, Inc. Independent control of ion density, ion energy distribution and ion dissociation in a plasma reactor
US20070247074A1 (en) * 2006-04-24 2007-10-25 Alexander Paterson Process using combined capacitively and inductively coupled plasma sources for controlling plasma ion radial distribution
US20080236750A1 (en) * 2007-03-27 2008-10-02 Tokyo Electron Limited Plasma processing apparatus
US20130087284A1 (en) * 2008-07-17 2013-04-11 Lam Research Corporation Organic line width roughness with h2 plasma treatment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140083977A1 (en) * 2012-09-26 2014-03-27 Kabushiki Kaisha Toshiba Plasma processing apparatus and plasma processing method
US10381198B2 (en) * 2012-09-26 2019-08-13 Toshiba Memory Corporation Plasma processing apparatus and plasma processing method
US20190221437A1 (en) * 2018-01-18 2019-07-18 Applied Materials, Inc. Etching apparatus and methods
US10707086B2 (en) * 2018-01-18 2020-07-07 Applied Materials, Inc. Etching methods
US11328903B2 (en) 2020-05-07 2022-05-10 Samsung Electronics Co., Ltd. Plasma processing system, method of controlling plasma in the plasma processing system, and method of manufacturing semiconductor device by using the method of controlling the plasma
US12112920B2 (en) 2020-05-07 2024-10-08 Samsung Electronics Co., Ltd. Plasma processing system

Also Published As

Publication number Publication date
JP5916056B2 (ja) 2016-05-11
EP2423944A1 (en) 2012-02-29
KR20120022648A (ko) 2012-03-12
TWI587379B (zh) 2017-06-11
US9478387B2 (en) 2016-10-25
CN102376559B (zh) 2015-01-28
US20140102638A1 (en) 2014-04-17
KR101841585B1 (ko) 2018-03-23
CN104599930A (zh) 2015-05-06
TW201643950A (zh) 2016-12-16
TW201234442A (en) 2012-08-16
CN104599930B (zh) 2017-04-12
EP2423944B1 (en) 2017-08-02
US20120214313A1 (en) 2012-08-23
CN102376559A (zh) 2012-03-14
TWI585834B (zh) 2017-06-01
JP2012069921A (ja) 2012-04-05

Similar Documents

Publication Publication Date Title
US9478387B2 (en) Plasma processing apparatus
US9659756B2 (en) Plasma etching apparatus and plasma cleaning method
US9034198B2 (en) Plasma etching method
US9852922B2 (en) Plasma processing method
EP2026374B1 (en) Plasma processing apparatus, plasma processing method and storage medium
KR100810773B1 (ko) 플라즈마 에칭 방법 및 컴퓨터 판독 가능한 기억 매체
US8440050B2 (en) Plasma processing apparatus and method, and storage medium
US8404595B2 (en) Plasma processing method
US20100224587A1 (en) Plasma etching method, plasma etching apparatus and computer-readable storage medium
JP6438831B2 (ja) 有機膜をエッチングする方法
US20150235861A1 (en) Plasma etching method and plasma etching apparatus
EP3046138A1 (en) Etching method
TW201630068A (zh) 電漿蝕刻方法
US10957515B2 (en) Plasma processing method and plasma processing apparatus
JP6045646B2 (ja) プラズマエッチング方法
EP3046137A1 (en) Etching method

Legal Events

Date Code Title Description
AS Assignment

Owner name: TOKYO ELECTRON LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OOYA, YOSHINOBU;TANABE, AKIRA;YASUTA, YOSHINORI;REEL/FRAME:026836/0919

Effective date: 20110828

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20220204