US8570094B2 - Semiconductor integrated circuit and method for driving the same - Google Patents

Semiconductor integrated circuit and method for driving the same Download PDF

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Publication number
US8570094B2
US8570094B2 US13/286,462 US201113286462A US8570094B2 US 8570094 B2 US8570094 B2 US 8570094B2 US 201113286462 A US201113286462 A US 201113286462A US 8570094 B2 US8570094 B2 US 8570094B2
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command
rupture
fuse
integrated circuit
semiconductor integrated
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US20130027095A1 (en
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Yeon-Uk Kim
Jung-Taek You
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SK Hynix Inc
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Hynix Semiconductor Inc
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Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, YEON-UK, YOU, JUNG-TAEK
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links

Definitions

  • Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor integrated circuit and a method for driving the same.
  • a semiconductor integrated circuit is provided with a redundancy memory cell in addition and performs a repair operation for replacing a defective memory cell with the redundancy memory cell in order to achieve a high yield.
  • the repair operation may be performed by a fuse circuit.
  • the repair operation may be performed by using a method of cutting a fuse by flowing over-current to the fuse, blowing out a fuse by using a laser beam, connecting a cut fuse by using a laser beam, or programming a fuse by using an erasable programmable read only memory (EPROM).
  • EPROM erasable programmable read only memory
  • the method of blowing out the fuse by using the laser beam is widely used since it may be simple and have much reliability in blowing out the fuse.
  • an anti-type fuse (Hereinafter, referred to as an ‘anti-fuse’) has been introduced.
  • the method of using the anti-fuse may be used to replace a defective memory cell with a redundancy memory cell in a package state.
  • the anti-fuse has an electrical characteristic opposite to the fuse.
  • the anti-fuse is a kind of resistive element to have a high resistance, higher than or equal to 100 M ⁇ , in an un-programmed state and to have a low resistance lower than 100 K ⁇ in a programmed state. That is, when the anti-fuse is implemented with a transistor whose source and drain are electrically connected, the anti-fuse may serve as a capacitor in the un-programmed state and a resistor in the programmed state.
  • the anti-fuse may include two conductive layers and an insulation layer therebetween.
  • the insulation layer may include a silicon oxide (SiO 2 ), silicon nitride (SiN), tantalum oxide (TaO x ), or silicon dioxide-silicon nitride-silicon dioxide (ONO).
  • a program operation on the anti-fuse is performed by applying a high voltage, e.g., approximately 10 V, to two conductive layers of the anti-fuse, thereby breaking down the insulating properties of the insulation layer therebetween. Accordingly, when the anti-fuse is programmed, two terminals coupled to the two conductive layers of the anti-fuse are short so that the anti-fuse has a low resistance.
  • the voltage level of the high supply voltage terminal may drop more seriously. If the voltage level of the high supply voltage terminal drops below a rupture tolerance range, the program operation may end in the state that some anti-fuses may not be programmed. For reference, since a high supply voltage is generally generated inside a semiconductor integrated circuit, there may be a limit in maintaining the voltage level of the high supply voltage terminal at a target voltage level when the high supply voltage is used at the same time.
  • Exemplary embodiments of the present invention are directed to a semiconductor integrated circuit and a method for driving the same capable of stably supplying a program voltage when a plurality of anti-fuses is programmed at once.
  • a semiconductor integrated circuit includes a command generating unit configured to generate a plurality of second commands in response to a first command, each second command for indicating an operation section of a corresponding anti-fuse circuit and a plurality of anti-fuse circuits, each comprising an anti-fuse and configured to receive a corresponding second command and perform a rupture operation of the anti-fuse in response to the received corresponding second command.
  • a method for driving a semiconductor integrated circuit includes generating a rupture source signal in response to a reset signal and a first rupture command sequentially generating a plurality of second rupture commands in response to the first rupture command and the rupture source signal each indicating an operation section for programming a corresponding anti-fuse, and programming the corresponding anti-fuse in response to each of the second rupture commands.
  • FIG. 1 shows a block diagram of a semiconductor integrated circuit including an anti-fuse circuit in accordance with an embodiment of the present invention.
  • FIG. 2 shows a detailed circuit diagram of a sequential rupture command generating unit shown in FIG. 1 .
  • FIG. 3 is a waveform diagram illustrating an operation of the semiconductor integrated circuit including the anti-fuse circuit shown in FIG. 1 .
  • FIG. 1 shows a block diagram of a semiconductor integrated circuit including an anti-fuse circuit in accordance with an embodiment of the present invention.
  • 4 anti-fuses are provided in a semiconductor integrated circuit in the preferred embodiment.
  • a semiconductor integrated circuit 100 includes a sequential rupture command generating unit 110 and first to fourth anti-fuse circuits 120 A, 120 B, 120 C, and 120 D.
  • the sequential rupture command generating unit 110 is configured to generate first to fourth sequential rupture commands RUPT — ⁇ 1:4>, each indicating a section for a rupture operation of each anti-fuse circuit in response to a rupture command RUPT_CMD which is toggling for a predetermined time.
  • Each of the first to fourth anti-fuse circuits 120 A, 120 B, 120 C, and 120 D includes an anti-fuse to perform a respective rupture operation in response to a corresponding one of the first to fourth sequential rupture commands RUPT — ⁇ 1:4>.
  • the rupture command RUPT_CMD is synchronized with a clock signal (not shown), which is used in the semiconductor integrated circuit 100 , and a period of the rupture command RUPT_CMD may be set to have N times of a period (tCK) of the clock signal, N being a natural number.
  • anti-fuse circuits 120 A to 120 D have substantially the same structure, only the first anti-fuse circuit 120 A is explained and shown for illustration purposes.
  • the first anti-fuse circuit 120 A includes a voltage supply unit 122 A and an anti-fuse 124 A.
  • the voltage supply unit 122 A is configured to supply a high supply voltage VEXT in response to the first sequential rupture command RUPT — ⁇ 1>, and the anti-fuse 124 A is coupled between an output terminal of the voltage supply unit 122 A and a low supply voltage VBBF terminal.
  • the voltage supply unit 122 A includes an inverter INV 1 and a PMOS transistor PM 1 .
  • the inverter INV 1 is configured to invert the first sequential rupture commands RUPT — ⁇ 1>
  • the PMOS transistor PM 1 is configured to selectively couple a high supply voltage VEXT terminal to the output terminal of the voltage supply unit 122 A in response to an output of the inverter INV 1 .
  • the high supply voltage VEXT and the low supply voltage VBBF are generated inside the semiconductor integrated circuit.
  • the high supply voltage VEXT may include a boosting voltage
  • the low supply voltage VBBF may include a back-bias voltage.
  • FIG. 2 shows a detailed circuit diagram of the sequential rupture command generating unit 110 shown in FIG. 1 .
  • the sequential rupture command generating unit 110 includes a rupture source signal generating unit 112 and a sequential rupture command output unit 114 .
  • the rupture source signal generating unit 112 is configured to generate a rupture source signal RUPT_SOURCE in response to a reset signal RST and the rupture command RUPT_CMD.
  • the sequential rupture command output unit 114 is configured to be reset in response to the reset signal RST and sequentially output the first to fourth sequential rupture commands RUPT — ⁇ 1:4> in response to the rupture command RUPT_CMD and the rupture source signal RUPT_SOURCE.
  • the rupture source signal generating unit 112 may include a RS latch, and the sequential rupture command output unit 114 may include first to fourth D flip-flops which are coupled in series to be reset by an inverted reset signal.
  • An inverter 116 may be provided to invert the reset signal RST to output the inverted reset signal.
  • FIG. 3 is a waveform diagram illustrating an operation of the semiconductor integrated circuit shown in FIG. 1 .
  • the rupture source signal generating unit 112 generates the rupture source signal RUPT_SOURCE in response to the reset signal RST and the rupture command RUPT_CMD which is toggling for a predetermined time from an activation of the reset signal RST.
  • the sequential rupture command output unit 114 sequentially outputs the first to fourth sequential rupture commands RUPT — ⁇ 1:4>, each indicating a section for a rupture operation of a corresponding anti-fuse circuit in response to the rupture command RUPT_CMD and the rupture source signal RUPT_SOURCE.
  • a period of the rupture command RUPT_CMD is set to have N times of a period (tCK) of a clock signal (not shown), and the rupture source signal RUPT_SOURCE is sequentially shifted by the period of the rupture command RUPT_CMD, i.e., N*tCK, and outputted as the first to fourth sequential rupture commands RUPT — ⁇ 1:4>.
  • the first to fourth sequential rupture commands RUPT — ⁇ 1:4> are sequentially activated in respond to a toggling of the rupture command RUPT_CMD and have an active duration corresponding to the period of the rupture command RUPT_CMD, i.e., N*tCK.
  • the anti-fuse circuits 120 A to 120 D rupture their own anti-fuse to perform a program operation in response to respective sequential rupture commands RUPT — ⁇ 1:4>.
  • one anti-fuse circuit is described to perform a program operation in response a rupture command in the exemplary embodiment, the present invention is not limited to this structure.
  • two or more anti-fuse circuits may perform a program operation in response a rupture command within unless a voltage level of high supply voltage may drop below a rupture tolerance range.
  • a semiconductor integrated circuit may ensure a section for a rupture operation of each anti-fuse circuit. Accordingly, reliability in the operation of the anti-fuse circuits may be increased for the program operation.

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
US13/286,462 2011-07-26 2011-11-01 Semiconductor integrated circuit and method for driving the same Active 2032-01-11 US8570094B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2011-0074199 2011-07-26
KR1020110074199A KR101811303B1 (ko) 2011-07-26 2011-07-26 반도체 집적회로 및 그의 구동 방법

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US20130027095A1 US20130027095A1 (en) 2013-01-31
US8570094B2 true US8570094B2 (en) 2013-10-29

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US (1) US8570094B2 (ko)
KR (1) KR101811303B1 (ko)
CN (1) CN102903389B (ko)
TW (1) TWI541812B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150049546A1 (en) * 2013-08-14 2015-02-19 Samsung Electronics Co., Ltd. Method of programming fuse cells and repairing memory device using the programmed fuse cells

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130097922A (ko) * 2012-02-27 2013-09-04 에스케이하이닉스 주식회사 펄스 쉬프팅 회로 및 이를 이용한 반도체 집적 회로
KR20170002565A (ko) * 2014-05-09 2017-01-06 산토리 홀딩스 가부시키가이샤 메톡시플라본을 함유하는 NOX 저해제 및 NFκB 저해제

Citations (9)

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KR20040007904A (ko) 2002-07-11 2004-01-28 주식회사 하이닉스반도체 안티퓨즈 제어 회로
US7031218B2 (en) * 2002-11-18 2006-04-18 Infineon Technologies Ag Externally clocked electrical fuse programming with asynchronous fuse selection
US7254079B2 (en) * 2005-01-14 2007-08-07 Matsushita Electric Industrial Co., Ltd. Electrical fuse circuit
KR20080034848A (ko) 2005-06-24 2008-04-22 프리스케일 세미컨덕터, 인크. 안티퓨즈 회로
US7397720B2 (en) * 2005-08-11 2008-07-08 Matsushita Electric Industrial Co., Ltd. Semiconductor storage device including electrical fuse module
US7622982B2 (en) * 2006-08-09 2009-11-24 Panasonic Corporation Electrical fuse device
KR20100014560A (ko) 2007-03-28 2010-02-10 프리스케일 세미컨덕터, 인크. 안티―퓨즈들을 프로그래밍하기 위한 방법 및 디바이스
US8278990B2 (en) * 2009-03-25 2012-10-02 Fujitsu Semiconductor Limited Electric fuse cutoff control circuit renewing cutoff information and semiconductor device
US8368456B2 (en) * 2010-03-31 2013-02-05 SK Hynix Inc. Fuse circuit with ensured fuse cut status

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JP2010182365A (ja) * 2009-02-04 2010-08-19 Elpida Memory Inc アンチヒューズ回路及び半導体記憶装置

Patent Citations (10)

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Publication number Priority date Publication date Assignee Title
KR20040007904A (ko) 2002-07-11 2004-01-28 주식회사 하이닉스반도체 안티퓨즈 제어 회로
US7031218B2 (en) * 2002-11-18 2006-04-18 Infineon Technologies Ag Externally clocked electrical fuse programming with asynchronous fuse selection
US7071729B2 (en) * 2002-11-18 2006-07-04 Infineon Technologies Ag Dual-purpose shift register
US7254079B2 (en) * 2005-01-14 2007-08-07 Matsushita Electric Industrial Co., Ltd. Electrical fuse circuit
KR20080034848A (ko) 2005-06-24 2008-04-22 프리스케일 세미컨덕터, 인크. 안티퓨즈 회로
US7397720B2 (en) * 2005-08-11 2008-07-08 Matsushita Electric Industrial Co., Ltd. Semiconductor storage device including electrical fuse module
US7622982B2 (en) * 2006-08-09 2009-11-24 Panasonic Corporation Electrical fuse device
KR20100014560A (ko) 2007-03-28 2010-02-10 프리스케일 세미컨덕터, 인크. 안티―퓨즈들을 프로그래밍하기 위한 방법 및 디바이스
US8278990B2 (en) * 2009-03-25 2012-10-02 Fujitsu Semiconductor Limited Electric fuse cutoff control circuit renewing cutoff information and semiconductor device
US8368456B2 (en) * 2010-03-31 2013-02-05 SK Hynix Inc. Fuse circuit with ensured fuse cut status

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150049546A1 (en) * 2013-08-14 2015-02-19 Samsung Electronics Co., Ltd. Method of programming fuse cells and repairing memory device using the programmed fuse cells

Also Published As

Publication number Publication date
TW201306036A (zh) 2013-02-01
CN102903389A (zh) 2013-01-30
US20130027095A1 (en) 2013-01-31
TWI541812B (zh) 2016-07-11
KR20130012802A (ko) 2013-02-05
CN102903389B (zh) 2016-08-17
KR101811303B1 (ko) 2017-12-26

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