US8268679B2 - Semiconductor device comprising eFUSES of enhanced programming efficiency - Google Patents

Semiconductor device comprising eFUSES of enhanced programming efficiency Download PDF

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US8268679B2
US8268679B2 US12/579,654 US57965409A US8268679B2 US 8268679 B2 US8268679 B2 US 8268679B2 US 57965409 A US57965409 A US 57965409A US 8268679 B2 US8268679 B2 US 8268679B2
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fuse
region
linear portions
contact
electronic
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US20100107403A1 (en
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Oliver Aubel
Jens Poppe
Andreas Kurz
Roman Boschke
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GlobalFoundries US Inc
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GlobalFoundries Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49107—Fuse making

Definitions

  • the present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to forming electronic fuses for providing device-internal programming capabilities in complex integrated circuits.
  • CMOS complementary metal-oxide-semiconductor
  • NMOS complementary metal-oxide-semiconductor
  • PMOS complementary metal-oxide-semiconductor
  • resistors resistors
  • capacitors capacitors and the like
  • circuit elements Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC). Furthermore, in sophisticated microcontroller devices, an increasing amount of storage capacity may be provided on chip with the CPU core, thereby also significantly enhancing the overall performance of modern computer devices.
  • SoC single chip
  • the various circuit portions may have a significantly different performance, for instance with respect to lifetime, reliability and the like.
  • the operating speed of a digital circuit portion such as a CPU core and the like, may depend on the configuration of the individual transistor elements and also on the characteristics of the metallization system, which may include a plurality of stacked metallization layers so as to comply with a required complex circuit layout.
  • highly sophisticated manufacturing techniques may be required in order to provide the minimum critical feature sizes of the speed-critical circuit components.
  • sophisticated digital circuitry may be used on the basis of field effect transistors which represent circuit components in which conductivity of a channel region is controlled on the basis of a gate electrode that is separated from the channel region by a thin dielectric material.
  • Performance of the individual field effect transistors is determined, among other things, by the capability of the transistor to switch from a high impedance state into a low impedance state at high speeds, wherein, also, a sufficiently high current may be driven in the low impedance state.
  • This drive current capability is determined, among other things, by the length of the conductive channel that forms in the channel region upon application of an appropriate control voltage to the gate electrode.
  • the channel length and thus the length of the gate electrode is continuously being reduced, which in turn may require an appropriate adaptation of the capacitive coupling of the gate electrode to the channel region. Consequently, the thickness of the gate dielectric material may also have to be reduced in order to maintain controllability of the conductive channel at a desired high level.
  • the shrinkage of the gate dielectric thickness may be associated with an exponential increase of the leakage currents, which may directly channel through the thin gate dielectric material, thereby contributing to enhanced power consumption and thus waste heat, which may contribute to sophisticated conditions during operation of the semiconductor device.
  • charge carriers may be injected into the gate dielectric material and may also contribute to a significant degradation of transistor characteristics, such as threshold voltage of the transistors, thereby also contributing to variability of the transistor characteristics over the lifetime of the product. Consequently, reliability and performance of certain sophisticated circuit portions may be determined by material characteristics and process techniques for forming highly sophisticated circuit elements, while other circuit portions may include less critical devices which may thus provide a different behavior over the lifetime compared to critical circuit portions. Consequently, the combination of the various circuit portions in a single semiconductor device may result in a significant different behavior with respect to performance and reliability, wherein the variations of the overall manufacturing process flow may also contribute to a further discrepancy between the various circuit portions.
  • so-called electronic fuses or e-fuses may be provided in the semiconductor devices, which may represent electronic switches that may be activated once in order to provide a desired circuit adaptation.
  • the electronic fuses may be considered as having a high impedance state, which may typically also represent a “programmed” state, and may have a low impedance state, typically representing a non-programmed state of the electronic fuse. Since these electronic fuses may have a significant influence on the overall behavior of the entire integrated circuit, a reliable detection of the non-programmed and the programmed state may have to be guaranteed, which may have to be accomplished on the basis of appropriately designed logic circuitry.
  • FIGS. 1 a - 1 b With reference to FIGS. 1 a - 1 b , a typical electronic fuse in a sophisticated semiconductor device will now be described in order to more clearly set forth the difficulties in providing electronic fuses in advanced semiconductor devices.
  • FIG. 1 a schematically illustrates a top view of a portion of a semiconductor device 150 which may represent any semiconductor device including sophisticated digital circuitry, such as a CPU core, a controller for graphic applications, memory areas and the like.
  • the semiconductor device 150 may thus comprise a circuit portion 160 , which may represent a sophisticated transistor element, such as a field effect transistor having a gate length of 50 nm and less, as previously discussed.
  • the device 150 comprises an electronic fuse 100 that may represent a one-time programmable electronic switch, which may be converted from a low impedance state into a high impedance state upon a current pulse generated by applying an appropriate programming voltage to the electronic fuse 100 .
  • the fuse 100 comprises a first contact area 101 and a second contact area 102 and an intermediate region 103 , provided in the form of a conductive line, which represents the actual fuse element which may alter its impedance state upon connecting the contact areas 101 and 102 with an appropriate voltage source.
  • the contact areas 101 , 102 and the conductive line 103 are formed of an appropriate electrode material, which may also be used for forming corresponding gate electrode structures of field effect transistors, such as is provided in the portion 160 .
  • polysilicon in combination with a metal silicide are frequently used materials for forming the electronic fuse 100 .
  • each of the contact areas 101 , 102 may be connected to corresponding contact elements that are formed in a contact level of the device 150 , as will be described in more detail with reference to FIG. 1 b.
  • FIG. 1 b schematically illustrates a cross-sectional view of the device 150 along the line Ib of FIG. 1 a .
  • the device 150 comprises a substrate 151 , such as a silicon substrate and the like, above which is formed a layer 152 , which may represent a semiconductor layer or an insulating material, depending on the position of the electronic fuse 100 within the semiconductor device 150 .
  • a layer 152 which may represent a semiconductor layer or an insulating material, depending on the position of the electronic fuse 100 within the semiconductor device 150 .
  • an insulating material 153 may be provided, for instance on the basis of a material as may also be used as a gate dielectric material for forming field effect transistors.
  • a contact level 120 is formed above the layer 152 so as to enclose the electronic fuse 100 and other circuit elements, such as transistors and the like.
  • the contact level comprises a dielectric material 122 in combination with an etch stop material 123 , such as silicon dioxide and silicon nitride, respectively, in which are formed the contact elements 121 that usually comprise a conductive material such as tungsten, possibly in combination with a conductive barrier material (not shown), such as titanium nitride and the like.
  • an etch stop material 123 such as silicon dioxide and silicon nitride, respectively, in which are formed the contact elements 121 that usually comprise a conductive material such as tungsten, possibly in combination with a conductive barrier material (not shown), such as titanium nitride and the like.
  • the semiconductor device 150 may be formed on the basis of well-established process techniques in which sophisticated circuit elements such as gate electrodes of field effect transistors and the like may be formed on the basis of critical dimensions of 50 nm and less.
  • an appropriate gate electrode material in combination with a gate dielectric material may be provided and may be patterned on the basis of sophisticated lithography and etch techniques, wherein the contact areas 101 , 102 and the region 103 may also be patterned.
  • the conductive line 103 may have a similar geometric configuration compared to gate electrode structures. That is, a width 103 W ( FIG. 1 a ) may correspond to the gate length of critical transistor elements, while a length 103 L may be several hundred nanometers, depending on the overall configuration.
  • the electronic fuse 100 is also to be designed in view of not unduly consuming valuable die area in the device 150 . Furthermore, in view of programmability of the fuse 100 , that is, of the region 103 , it is preferable to provide a minimum cross-sectional area so as to allow a significant modification of the electrical behavior of the region 103 upon applying a sufficiently high current flowing through the region 103 . Consequently, the region 103 may be designed in accordance with the corresponding design rules for the device under consideration.
  • the conductivity of semiconductor regions may be increased, for instance by forming a metal silicide in corresponding drain and source areas and gate electrodes, thereby also forming a metal silicide 104 in the contact areas 101 , 102 and the region 103 .
  • This may be accomplished on the basis of well-established process techniques.
  • respective sidewalls spacers 105 may also have been formed, which may typically be used for defining corresponding dopant profiles in transistor areas and act as a mask during the silicidation process.
  • the contact level 120 may be formed on the basis of well-established process techniques including the deposition of the materials 123 and 122 and patterning the same in order to obtain appropriate contact openings, which are subsequently filled with conductive material, such as tungsten and the like.
  • conductive material such as tungsten and the like.
  • a plurality of metallization layers are formed, which may provide the wiring fabric for the circuit elements and also for the electronic fuse 100 in accordance with the overall circuit layout.
  • a sufficiently high voltage is to be applied between the contact areas 101 and 102 in order to generate a sufficient high current density, which may result in a permanent modification in order to blow the fuse 100 .
  • the per se negative effect of electromigration may be efficiently used to induce a current-driven material diffusion in the line 103 , which may result in a significant modification of the electrical performance, i.e., a corresponding high impedance state may be achieved due to the “degradation” of the line 103 .
  • Electromigration is a well-known effect which may occur in conductive lines, typically metal-containing lines, when current density is very high so that the flow of electrons may cause a directed “diffusion” of ion cores, thereby increasingly transporting material along the electron flow direction.
  • the corresponding line may increasingly suffer from a depletion of material in the vicinity of the cathode, while material may be deposited at or next to the line in the vicinity of the anode of the fuse 100 .
  • a reliable distinction between a non-programmed state and a programmed state may require a corresponding significant modification of line 103 , which may require significant voltages and may also require appropriately designed contact areas 101 , 102 and an appropriate number of contact elements 121 connecting thereto in order to provide the required current drive capability for effecting a “blowing” of line 103 .
  • an appropriate tightly set “programming voltage window” may be required for sophisticated devices in order to obtain a high difference between the low impedance state and the high impedance state.
  • the corresponding margins for the programming voltage may also have to take account of any process-related fluctuations during the formation of the fuse 100 , thereby requiring more tightly set programming voltages.
  • a corresponding required degree of reliability in detecting the programmed state may require sufficiently high programming voltages, which may not be compatible with the supply voltages used for sophisticated devices.
  • the present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.
  • the present disclosure relates to semiconductor devices and methods for forming the same in which electronic fuses for advanced semiconductor devices may be provided so as to exhibit an increased tolerance with respect to programming voltages, while nevertheless providing a reliable programmed state.
  • the electronic fuses may receive at least one portion that is designed to generate an increased current density when programming the electronic fuse so that an increased electromigration effect may be obtained in the corresponding portion. Consequently, a significant modification of the electric conductivity may be achieved at a reduced current density, thereby enabling the usage of lower voltages and also providing the possibility of generally reducing the size of corresponding contact areas and thus the size and/or the number of corresponding contact elements connected thereto, which in turn results in an overall reduced size of the electronic fuses.
  • One illustrative method disclosed herein relates to the forming of an electronic fuse of an integrated circuit.
  • the method comprises forming an electrode material above an insulating material formed above a substrate of the integrated circuit. Furthermore, the method comprises forming a first contact area, a second contact area and a fuse region of the electronic fuse from the electrode material, wherein the fuse region connects to the first and second contact areas and comprises at least one non-linear portion for generating a zone of increased current density. Furthermore, the method comprises forming contact elements in a contact level of the integrated circuit, wherein the contact elements connect to the first and second contact areas of the electronic fuse.
  • a still further illustrative method disclosed herein relates to the designing of an electronic fuse of a semiconductor device.
  • the method comprises providing a first contact area and a second contact area of the electronic fuse and use a plurality of linear portions of a fuse region.
  • the method further comprises combining the plurality of linear portions to form at least one connection region having a non-linear configuration to define a zone of increased current density.
  • One illustrative semiconductor device disclosed herein comprises a plurality of circuit elements formed in and above a semiconductor layer.
  • the semiconductor device comprises an electronic fuse formed on an insulating material, wherein the electronic fuse comprises a first contact area, a second contact area and a fuse region including at least one non-linear portion that defines a zone of increased current density.
  • the semiconductor device comprises a contact level formed above the semiconductor layer and comprising a plurality of contact elements connecting to the plurality of circuit elements and to the first and second contact areas of the electronic fuse.
  • the device comprises a metallization system formed above the contact level.
  • FIG. 1 a schematically illustrates a top view of a conventional semiconductor device including an electronic fuse
  • FIG. 1 b schematically illustrates a cross-sectional view of the electronic fuse of the conventional device as shown in FIG. 1 a;
  • FIGS. 2 a - 2 b schematically illustrate top views of a portion of a semiconductor device including a circuit portion and an electronic fuse having a zone of increased current density, according to illustrative embodiments;
  • FIGS. 2 c - 2 f schematically illustrate top views of respective layouts or actual electronic fuses including a chain configuration, in which a plurality of linear fuse regions are connected in series so as to obtain two or more zones of increased current density, according to further illustrative embodiments;
  • FIG. 2 g schematically illustrates a layout or an actual electronic fuse including three zones of increased current density obtained on the basis of a chain-like configuration
  • FIG. 2 h schematically illustrates a top view of an exemplary electronic fuse in which portions thereof may be provided in a “u-turn” configuration in laterally restricted areas;
  • FIGS. 2 i - 2 l schematically illustrate top views of a layout or an actual implementation of an electronic fuse including a fuse region comprised of a “u-like” configuration according to still further illustrative embodiments;
  • FIG. 2 m schematically illustrates a top view of a layout or an actual implementation of an electronic fuse in which the fuse region may comprise a plurality of “u-turns,” according to still further illustrative embodiments;
  • FIG. 2 n schematically illustrates a cross-sectional view of a semiconductor device including an electronic fuse, according to illustrative embodiments.
  • the present disclosure provides semiconductor devices, layouts and manufacturing techniques in which an electronic fuse may be provided with enhanced reliability even for highly critical dimensions, such as a width of the fuse region of approximately 50 nm and less, while at the same time providing the possibility of reducing the overall size of the electronic fuse.
  • one or more zones of increased current density may be provided in the actual fuse region, thereby locally increasing the electromigration effect in these zones, possibly in combination with a depletion of dopant species when doped semiconductor material in combination with metal species is used for forming the electronic fuse.
  • the zones of increased current density may be obtained by combining linear segments or portions having a specific critical width such that at least one connection region is provided that contributes to an increased current density during a programming event.
  • respective linear segments or portions may be connected so as to form an angle of approximately 90 degrees so that locally a certain degree of current crowding may be generated upon applying a programming pulse to the electronic fuse. Consequently, the current crowding and thus increased current density may result in an increase of the local current density, which in turn may result in a more pronounced modification of the overall conductivity of the electronic fuse.
  • FIGS. 2 a - 2 n further illustrative embodiments will now be described in more detail, wherein reference may also be made to FIGS. 1 a - 1 b , if appropriate.
  • FIG. 2 a schematically illustrates a top view of a semiconductor device 250 , which may comprise a circuit portion 260 formed on the basis of a plurality of circuit elements, such as transistors 261 , 262 and the like.
  • the circuit portion 260 may represent any portion of a complex circuit, such as a digital circuit portion and the like, which may or may not be functionally connected to an electronic fuse 200 . That is, as previously explained, for detecting a state of the electronic fuse 200 and also for programming the same at any appropriate point in time, corresponding circuitry may be required, for instance in the form of logic gates and the like, which may represent a part of the circuit portion 260 .
  • the electronic fuse 200 may comprise a first contact area 201 and a second contact area 202 and a fuse region 203 , which may represent the region in which a change of conductivity may be generated on the basis of electromigration, dopant depletion and the like, as is also previously explained.
  • the region 203 may comprise one or more portions or zones of increased current density when the electronic fuse 200 is activated on the basis of an appropriate programming voltage.
  • the fuse region 203 may comprise one or more non-linear portions, for instance represented by the corners 203 C, which may be obtained by using a plurality of linear portions 203 K, 203 L, 203 M, 203 N that may be connected so as to define a “fork-like” configuration connecting to the contact area 202 .
  • FIG. 2 b schematically illustrates a top view of the electronic fuse 200 according to further illustrative embodiments in which a single portion 203 C may be provided on the basis of two linear portions 203 K, 203 L which may be connected to define the region 203 C resulting in zone 203 A of increased current density upon applying a programming voltage.
  • the electrical performance of the electronic fuse 200 may be significantly different compared to the conventional electronic fuse 100 ( FIGS. 1 a and 1 b ) due to the provision of a non-linear configuration of the fuse region 203 , which may thus include at least one portion 203 C resulting in a zone of increased current density 203 A upon programming the electronic fuse 200 .
  • the semiconductor device 250 may be formed on the basis of well-established process techniques, as are also described with reference to the semiconductor device 150 , wherein, however, during the design phase of the device 250 , the non-linear configuration of the fuse region 203 is taken into consideration.
  • the enhanced efficiency of applying a programming pulse may also be taken into consideration by, for instance, reducing the lateral size of the first and second contact areas 201 , 202 and by reducing the number and/or the size of corresponding contact elements connecting thereto, since a magnitude of the programming current required may be reduced, thereby offering the possibility of reducing the drive current capabilities of any conductive lines connecting to the electronic fuse 200 .
  • the electronic fuse 200 may be defined on the basis of corresponding critical dimensions for the technology under consideration, while each fuse 200 may consume less die area, thereby providing significant space-saving of the device 250 compared to the conventional device 150 for otherwise identical technology standards.
  • the appropriate process techniques may be applied, as previously described, while the additional die area may be used for additional circuitry, test structures and the like.
  • FIGS. 2 c - 2 f schematically illustrate top views of further designs or actual implementations of the electronic fuse 200 according to further illustrative embodiments.
  • FIG. 2 c schematically illustrates the electronic fuse 200 in which a “chain configuration,” comprised of three linear portions 203 K, 203 L and 203 M, is provided and is connected such that two portions 203 C of increased current density are defined. That is, the linear portions 203 K and 203 L are connected so as to form an angle of approximately 90 degrees and also the portions 203 L and 203 M are combined so as to define an angle of approximately 90 degrees, however of opposite “direction” compared to the linear portions 203 K, 203 L.
  • the length of the linear portions 203 K, 203 M may be significantly greater compared to the length of the portion 203 L, so that the corresponding portions 203 C may be provided in close proximity to each other, thereby even further enhancing the overall current crowd effect, as indicated by arrow 206 .
  • FIGS. 2 d , 2 e and 2 f schematically illustrate various variations of the configuration as shown in FIG. 2 c , wherein, for instance, the length of the corresponding portions 203 L is increased.
  • the individual length of the portions 203 K, 203 L, 203 M may be appropriately selected in accordance with the design requirements while nevertheless providing two portions 203 C providing the desired current crowding upon programming the electronic fuse 200 .
  • FIG. 2 g schematically illustrates a top view of a layout or an actual implementation of the electronic fuse 200 in which three portions 203 C of increased current density may be provided on the basis of a “chain configuration” for linear portions 203 K, 203 L, 203 M, 203 N. Also in this case, two connected linear portions are connected such that the corresponding connection region 203 C defines an angle of approximately 90 degrees.
  • FIG. 2 h schematically illustrates a top view of the electronic fuse 200 , in which three connection portions 203 C may be provided at a laterally restricted area by using a “u-turn” configuration in the form of the linear portions 203 L, 203 M, 203 N in combination with an additional angled configuration by connecting the linear portion 203 K with the portion 203 L according to a 90 degree angle.
  • a high degree of flexibility in creating more than one connection portion 203 C may be provided, wherein the position of the corresponding contact areas 201 , 202 may also be selected with a high design flexibility, thereby also providing the possibility of appropriately taking advantage of the area saving obtained by the efficient non-linear configuration of the fuse region 203 .
  • FIGS. 2 j - 2 l schematically illustrate top views of layouts or actual implementations of the electronic fuse 200 according to further illustrative embodiments in which a basic configuration with respect to the contact areas 201 , 202 and the fuse region 203 is provided, wherein, however, an additional “u-turn” is provided in the fuse region 203 in order to provide connection portions 203 C to define corresponding zones of increased current density.
  • FIG. 2 j schematically illustrates the fuse region 203 with linear portions 203 K, 203 L that connect to a “u-turn” portion 203 U, the “width” of which may be substantially determined by the length of a portion 203 N. Consequently, due to the reduced length of the portion 203 N in the u-turn 203 U, the respective portions 203 C of increased current density formed in combination with the portions 203 K, 203 L may be positioned in close proximity to each other, thereby providing a high efficiency in obtaining an electromigration effect upon programming the fuse 200 .
  • FIGS. 2 k and 2 l schematically illustrate the electronic fuse 200 according to illustrative embodiments in which the corresponding length of the portion 203 N in the u-turn 203 U may be increased, depending on the overall design criteria.
  • FIG. 2 m schematically illustrates a top view of the electronic fuse 200 according to a further illustrative embodiment in which a plurality of u-turns 203 U may be connected in series in order to increase the number of connection portions 203 C while also increasing the total length of the fuse region 203 in a space-efficient manner.
  • the difference between the non-programmed state and the programmed state may be increased since a significantly higher degradation of conductivity may be obtained along the entire length of the fuse region 203 compared to a reduced total length.
  • the relation between contact resistance in the contact areas 201 , 202 relative to the “bridge resistance” of the fuse region 203 may be increased without unduly contributing to overall space consumption of the fuse 200 .
  • FIG. 2 n schematically illustrates a cross-sectional view of an actual implementation of the electronic fuse 200 in the semiconductor device 250 , for instance corresponding to the configuration as shown in FIG. 2 j .
  • the semiconductor 250 may comprise a substrate 251 , such as a semiconductor substrate, a silicon-on-insulator (SOI) substrate and the like.
  • a device layer 252 may be provided, for instance on the basis of an appropriate semiconductor layer which may comprise isolation regions, depending on the overall circuit configuration.
  • the electronic fuse 200 may be positioned above a corresponding isolation region, which may be formed in a corresponding semiconductor layer, while, in other cases, a portion of the fuse 200 or the entire fuse 200 may be formed above a semiconductor material.
  • the device 250 may comprise the electronic fuse 200 , the contact areas 201 , 202 , which may be connected to a metallization system 230 by a contact level 220 .
  • the contact level 220 may comprise a dielectric material 222 , for instance in combination with an etch stop material 223 , in which are provided contact elements 221 connecting to the areas 201 , 202 , respectively.
  • the semiconductor device 250 may be formed on the basis of well-established manufacturing techniques, wherein, however, the basic design of the electronic fuse 200 may be accomplished on the principles as described above.
  • the various components of the electronic fuse 200 may be formed together with other circuit elements, such as transistors and the like, on the basis of the corresponding design rules of the device level and the technology under consideration.
  • the electronic fuse 200 may be formed together with gate electrodes of sophisticated transistor elements, such as the transistors 261 , 262 ( FIG. 2 a ), wherein the gate electrodes may be formed on the basis of a polysilicon material in combination with a metal silicide, thereby forming a metal silicide 204 on a corresponding polysilicon material 207 in the electronic fuse 200 .
  • the region 203 is less sensitive to any process-related fluctuations for a given range of programming voltages compared to conventional devices. That is, for a given programming voltage and for any process-related variations, a reliably detectable high impedance state may be obtained on the basis of the fuse region 203 including one or more areas of increased current density.
  • gate electrodes of sophisticated transistors may be formed on the basis of sophisticated materials, such as a high-k dielectric material for the gate insulation layer in combination with metal-containing gate electrode materials.
  • a corresponding manufacturing sequence may be used for providing the electronic fuse 200 since increased electromigration sensitivity may be accomplished on the basis of the fuse region 203 as described above.
  • a gate dielectric material with increased permittivity for instance having a dielectric constant of 10.0 and significantly higher, may be deposited, followed by the deposition of an appropriate sophisticated gate electrode material.
  • a corresponding insulating material 253 may also be provided in the region 203 , followed by the metal-containing gate electrode material.
  • the material 204 representing a metal-containing material may extend completely down to the insulating layer 253 .
  • the electronic fuse 200 may be formed on the basis of a sophisticated manufacturing technique without adding additional process complexity, while a high degree of sensitivity with respect to an intended electromigration effect during the programming of the fuse 200 may still be accomplished.
  • FIG. 2 i schematically illustrates the electronic fuse 200 such that a “u-like” configuration is obtained. That is, the three linear portions 203 K, 203 L and 203 M are connected in series so as to define two angles of approximately 90 degrees oriented in the same direction so that a corresponding current flow may be anti-parallel in the portions 203 M, 203 K upon programming the electronic fuse 200 .
  • the present disclosure provides techniques, layouts and methods for forming electronic fuses that may exhibit increased sensitivity to electromigration effects, thereby allowing the usage of a wider window of programming voltages while also reducing the sensitivity to process-related variations. Furthermore, the overall space consumption of the electronic fuses may be reduced, since corresponding contact elements may be reduced in size and/or in number.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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US12/579,654 2008-10-31 2009-10-15 Semiconductor device comprising eFUSES of enhanced programming efficiency Active 2030-08-08 US8268679B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9214245B2 (en) 2014-01-23 2015-12-15 Samsung Electronics Co., Ltd. E-fuse structure of semiconductor device
TWI841274B (zh) * 2023-03-03 2024-05-01 南亞科技股份有限公司 半導體結構的製造方法及熔絲結構

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110074538A1 (en) * 2009-09-25 2011-03-31 Kuei-Sheng Wu Electrical fuse structure and method for fabricating the same
US8486743B2 (en) 2011-03-23 2013-07-16 Micron Technology, Inc. Methods of forming memory cells
US8569116B2 (en) * 2011-06-28 2013-10-29 GlobalFoundries, Inc. Integrated circuit with a fin-based fuse, and related fabrication method
US8994489B2 (en) 2011-10-19 2015-03-31 Micron Technology, Inc. Fuses, and methods of forming and using fuses
US8723155B2 (en) 2011-11-17 2014-05-13 Micron Technology, Inc. Memory cells and integrated devices
US9252188B2 (en) 2011-11-17 2016-02-02 Micron Technology, Inc. Methods of forming memory cells
US8546231B2 (en) 2011-11-17 2013-10-01 Micron Technology, Inc. Memory arrays and methods of forming memory cells
US8765555B2 (en) 2012-04-30 2014-07-01 Micron Technology, Inc. Phase change memory cells and methods of forming phase change memory cells
US9136467B2 (en) 2012-04-30 2015-09-15 Micron Technology, Inc. Phase change memory cells and methods of forming phase change memory cells
US9553262B2 (en) 2013-02-07 2017-01-24 Micron Technology, Inc. Arrays of memory cells and methods of forming an array of memory cells
US20140264731A1 (en) * 2013-03-15 2014-09-18 Globalfoundries Inc. Programmable e-fuse for an integrated circuit product
US9881971B2 (en) 2014-04-01 2018-01-30 Micron Technology, Inc. Memory arrays
US9362494B2 (en) 2014-06-02 2016-06-07 Micron Technology, Inc. Array of cross point memory cells and methods of forming an array of cross point memory cells
US9343506B2 (en) 2014-06-04 2016-05-17 Micron Technology, Inc. Memory arrays with polygonal memory cells having specific sidewall orientations
US20170338180A1 (en) * 2016-05-18 2017-11-23 Globalfoundries Inc. Method of making vertical and bottom bias e-fuses and related devices
CN114464595A (zh) * 2022-04-12 2022-05-10 晶芯成(北京)科技有限公司 电熔丝结构

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0451563A (ja) 1990-06-19 1992-02-20 Seiko Epson Corp 半導体装置
EP0563852A1 (en) 1992-04-02 1993-10-06 Siemens Aktiengesellschaft Zag fuse for reduced blow-current applications
US6501107B1 (en) 1998-12-02 2002-12-31 Microsoft Corporation Addressable fuse array for circuits and mechanical devices
US20030141568A1 (en) 2002-01-31 2003-07-31 Fujitsu Limited Semiconductor device and manufacturing method thereof
WO2004075221A2 (en) 2003-02-19 2004-09-02 Cavendish Kinetics Limited Micro fuse
US6933591B1 (en) 2003-10-16 2005-08-23 Altera Corporation Electrically-programmable integrated circuit fuses and sensing circuits
US20070210414A1 (en) * 2006-03-07 2007-09-13 Takeshi Iwamoto Semiconductor device and a method of increasing a resistance value of an electric fuse
US7282751B2 (en) 2003-08-07 2007-10-16 Nec Electronics Corporation Semiconductor device
CN101170099A (zh) 2007-11-30 2008-04-30 上海宏力半导体制造有限公司 多晶硅硅化物电熔丝器件
US20080206939A1 (en) 2007-02-28 2008-08-28 Min Byoung W Semiconductor device with integrated resistive element and method of making
US20090101989A1 (en) * 2007-10-18 2009-04-23 International Business Machines Corporation Metal gate compatible electrical fuse

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0451563A (ja) 1990-06-19 1992-02-20 Seiko Epson Corp 半導体装置
EP0563852A1 (en) 1992-04-02 1993-10-06 Siemens Aktiengesellschaft Zag fuse for reduced blow-current applications
US5420456A (en) 1992-04-02 1995-05-30 International Business Machines Corporation ZAG fuse for reduced blow-current application
US6501107B1 (en) 1998-12-02 2002-12-31 Microsoft Corporation Addressable fuse array for circuits and mechanical devices
US20030141568A1 (en) 2002-01-31 2003-07-31 Fujitsu Limited Semiconductor device and manufacturing method thereof
WO2004075221A2 (en) 2003-02-19 2004-09-02 Cavendish Kinetics Limited Micro fuse
US7282751B2 (en) 2003-08-07 2007-10-16 Nec Electronics Corporation Semiconductor device
US6933591B1 (en) 2003-10-16 2005-08-23 Altera Corporation Electrically-programmable integrated circuit fuses and sensing circuits
US20070210414A1 (en) * 2006-03-07 2007-09-13 Takeshi Iwamoto Semiconductor device and a method of increasing a resistance value of an electric fuse
US20080206939A1 (en) 2007-02-28 2008-08-28 Min Byoung W Semiconductor device with integrated resistive element and method of making
US20090101989A1 (en) * 2007-10-18 2009-04-23 International Business Machines Corporation Metal gate compatible electrical fuse
CN101170099A (zh) 2007-11-30 2008-04-30 上海宏力半导体制造有限公司 多晶硅硅化物电熔丝器件
US20090140382A1 (en) 2007-11-30 2009-06-04 Wen-Yu Gao Electric fuse device made of polysilicon silicide

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PCT Search Report and Written Opinion from PCT/US2009/005901 dated Feb. 15, 2010.
Robson et al., "Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips," IEEE 2007 Custom Integrated Circuits Conference (CICC), pp. 799-804, 2007.
Translation of Official Communication from German Patent Office for German Patent Application No. 10 2008 054 073.0 dated Oct. 5, 2009.

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9214245B2 (en) 2014-01-23 2015-12-15 Samsung Electronics Co., Ltd. E-fuse structure of semiconductor device
US9666526B2 (en) 2014-01-23 2017-05-30 Samsung Electronics Co., Ltd. E-fuse structure of semiconductor device
US9935049B2 (en) 2014-01-23 2018-04-03 Samsung Electronics Co., Ltd. E-fuse structure of semiconductor device
TWI841274B (zh) * 2023-03-03 2024-05-01 南亞科技股份有限公司 半導體結構的製造方法及熔絲結構

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