US8008664B2 - Component comprising a thin-film transistor and CMOS-transistors and methods for production - Google Patents

Component comprising a thin-film transistor and CMOS-transistors and methods for production Download PDF

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US8008664B2
US8008664B2 US12/375,529 US37552907A US8008664B2 US 8008664 B2 US8008664 B2 US 8008664B2 US 37552907 A US37552907 A US 37552907A US 8008664 B2 US8008664 B2 US 8008664B2
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thin
film transistor
polysilicon layer
doping
gate
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US20100032675A1 (en
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Hubert Enichlmair
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Ams Osram AG
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Austriamicrosystems AG
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Definitions

  • the invention relates to a component in which thin-film transistors and CMOS transistors are integrated.
  • Components of this type are used, for instance, as semiconductor memories, wherein the thin-film transistor serves as the switching transistor for a memory cell comprising CMOS transistors.
  • Such a memory is known, for instance, from U.S. Pat. No. 5,298,782 A.
  • An object of the present invention is to provide a semiconductor component with CMOS transistors, in which a thin-film transistor is integrated.
  • An electrical component comprises a crystalline semiconductor body with CMOS transistors formed therein.
  • the CMOS transistors are surrounded with insulation regions, which are constructed as field oxide regions or as STI (Shallow Trench Isolation) regions.
  • insulation regions are constructed as field oxide regions or as STI (Shallow Trench Isolation) regions.
  • one of the insulation regions is increased in surface area sufficiently that space is created there for a thin-film transistor arranged directly on top of the insulation region.
  • the gate of the CMOS transistors and the gate of the thin-film transistor are both structured from a common polysilicon layer and therefore have identical film thicknesses, identical crystal structures and identical doping.
  • the body of the thin-film transistor, as well as its source and drain, are then separated from the gate by a gate dielectric film, formed in an additional polysilicon layer above the gate of the thin-film transistor.
  • the thin-film transistor is completely insulated from the CMOS transistors. No leakage currents to the semiconductor body that forms the substrate of the CMOS transistors can occur.
  • the thin-film transistor can therefore be operated with different operating and switching voltages, just like the CMOS transistors. The insulation is assured up to the breakdown voltage of the insulation region.
  • An insulation region chosen to be appropriately thick can therefore serve to adjust a sufficiently high, or a desired, breakdown voltage between the thin-film transistor and the semiconductor body.
  • Breakdown voltages of ca. 20 V can be achieved for the thin-film transistor. Threshold voltages of ca. 2 V or more can be realized.
  • the thin-film transistor can be connected to the CMOS transistors and can carry out a great diversity of tasks for the component.
  • the thin-film transistor can be utilized as a high-speed switching transistor, as a variable resistance, as a diode or as a symmetrical transistor.
  • the thin-film transistor has low parasitic capacitance and short minority charge carrier lifetime, which makes possible a fast switching process and thus a fast switching transistor.
  • the method starts with the production of the insulation regions by local thermal oxidation, or by producing a trench and filling it with a deposited dielectric, in particular, an oxide.
  • the active regions are kept free from insulating regions, and the individual CMOS transistors are electrically isolated from one another by the insulation regions.
  • a sufficiently high surface above the insulation region is reserved, which is formed with a sufficiently large surface area to serve as a base for the at least one thin-film transistor.
  • the gate electrode of the thin-film transistor is also structured out of the first polysilicon layer above the flat insulation region.
  • the first polysilicon layer is referred to below as the poly-1 level.
  • a second polysilicon layer which also serves for conventional CMOS transistors as the poly-2 level for structural elements of the CMOS transistors, is applied and structured. Above the gate electrode of the thin-film transistor, the body, source and drain of the thin-film transistor are structured from the poly-2 level.
  • Another gate dielectric is produced in the area of the thin-film transistor between the poly-1 level and the poly-2 level; in particular, an oxide is grown or deposited.
  • the method for producing the component can comprise the production of a capacitor consisting of the poly-1 level as the first capacitor electrode, a dielectric and the poly-2 level as the second capacitor electrode.
  • the dielectric for this “CMOS capacitor” can simultaneously serve as the gate dielectric for the thin-film transistor, so that no additional method step is necessary.
  • the first and second polysilicon layers can be deposited undoped; the first can be doped. Two different kinds of doping are necessary in the second polysilicon layer: first, a relatively strong doping for the conductive structural elements of the CMOS transistor, and second, a relatively weaker one for the body of the thin-film transistor.
  • the second polysilicon layer is first implanted with a doping suitable for the body of the thin-film transistor, preferably a weak p-type doping with a doping level of 10 16 -10 17 cm ⁇ 3 by implanting a corresponding amount of doping material.
  • an absorber layer preferably a resist layer, is applied and structured such that it covers the body region of the thin-film transistor, which is arranged directly above the corresponding gate electrode. In the subsequent doping of the other regions of the second polysilicon layer, the absorber layer prevents the doping of the body.
  • the production and structuring of the absorber layer represent an additional mask step, which expands the method according to the invention with respect to a conventional CMOS method.
  • the additional method steps for completing the component are adapted by appropriate modification of conventional CMOS technology, and require no additional method step for the integration of the thin-film transistor into the production of the CMOS component.
  • the source and drain for both component types are doped by introducing an appropriately high doping into the respective regions of the semiconductor body (for the CMOS transistors) or the corresponding regions of the second polysilicon layer (for the thin-film transistor).
  • Doping type, doping method and doping level of the respective source and drain do not differ for the two transistor types, so that the method can be performed in one step by a doping or implantation mask with appropriately formed mask openings.
  • a component according to the invention is produced with a thin-film transistor that has an n-doped gate and an n + -doping for source and drain and a p-doping for the body, then this is an enhancement-type transistor.
  • a transistor In the base state, in which no bias is applied to the gate of the thin-film transistor, such a transistor is in the off state.
  • an inversion channel By applying a positive potential relative to the body to the gate electrode, an inversion channel can be produced by displacing the majority carriers there, so that the minority carriers, the electrons in this case, determine the conductivity of the channel.
  • the level of the current flowing through the channel is proportional to the applied gate voltage, so that the thin-film transistor according to the invention can be used as a variable resistor. It has been shown, however, that such a thin-film transistor has a relatively high leakage current.
  • a respective transition region with a doping gradient was therefore created between the source/drain and the body of the thin-film transistor. This is accomplished in a simple manner by positioning the corresponding mask openings during the production of the source/drain doping such that a reserved region remaining undoped in this doping step is left between the source and drain, respectively, and the body.
  • This initially undoped strip inside the second polysilicon layer can be made into a transition region by causing the high doping of the source/drain regions to diffuse into this initially undoped region in a later thermal step. This thermal step can be part of the CMOS process, so that no separate temperature treatment is necessary.
  • a transition area with a doping gradient ensures a uniform field distribution, which substantially reduces the leakage current of the thin-film transistor.
  • a transition area on the order of 1 ⁇ m has proven advantageous.
  • the temperature budget that acts on the component with the remaining steps of the CMOS leads to an outward diffusion in the range of the order of magnitude, ca. 1 ⁇ m, of this reserve strip.
  • the width of the reserve strip can be appropriately adapted.
  • a suitable gate length is, for instance, 10 ⁇ m and less.
  • the second polysilicon layer can serve in CMOS technology for producing component structures selected from resistors, capacitor electrodes, electrical supply lines and field plates. In the component, the second polysilicon layer is accordingly used for the production of at least one of these structures.
  • a component according to an embodiment of the invention with integrated thin-film transistor can also be produced with a p + -doped source and drain.
  • a thin-film transistor of the enhancement type which is nonconductive without application of the voltage to the gate, is produced.
  • the second polysilicon layer in the region of the thin-film transistor is always p or p + doped, a depletion zone arises because of the work function and the n + -doped gate which, only with a negative gate voltage applied, leads to an enhancement of the majority charge carriers (holes) in the region of the channel and thus to conduction.
  • FIG. 1 shows a component according to an embodiment of the invention in schematic cross section
  • FIG. 2 shows a thin-film transistor in a plan view
  • FIGS. 3 a to 3 d show various process stages in the production of the component
  • FIG. 4 shows a connection of the thin-film transistor as a blocking diode.
  • FIG. 1 shows a possible configuration of a component according to an embodiment of the invention in a schematic cross section.
  • CMOS transistors are realized, of which a low-voltage MOS transistor is shown in the figure for the sake of example.
  • the active regions of the CMOS transistors are separated from one another by insulating regions IG.
  • the insulating regions can be embodied as field oxides or as STI (shallow trench isolation).
  • another insulation region IG′ which has a sufficient surface area to accommodate a thin-film transistor, is realized.
  • the thin-film transistor area is labeled TFT in the figure.
  • the thin-film transistor TFT and the CMOS transistor have respective gates G D , G B , which are structured from the same (first) polysilicon layer in the same process step.
  • the polysilicon layer is deposited to a thickness of, for example, 0.3 ⁇ m doped or undoped, and subsequently doped appropriately by, for example, implantation of phosphorus-containing ions or substances.
  • the first polysilicon layer for the gate G B is applied to a thin layer of a gate dielectric GD B , on a deposited or thermally produced oxide layer, for example, while the gate G D of the thin-film transistor TFT can be situated directly on top of the insulating region IG′.
  • the thin-film transistor TFT further consists of a thin film of gate dielectric GD D and, above it, an additional (second) polysilicon layer PS2, which overlaps the gate G D .
  • the source S and the drain D are realized by an appropriately high doping of the p + or n + type on either side of the gate.
  • the second polysilicon layer PS2 has a weaker body doping, a p-doping in the selected example.
  • the CMOS transistor is completed by highly doped regions for the source S B and the drain D B on either side of the gate G B .
  • FIGS. 3A to 3D The most important steps in the production of the component according to an embodiment of the invention are represented and explained in FIGS. 3A to 3D on the basis of various characteristic process steps.
  • active regions AG B are defined and are free of insulating regions IG, which are realized as a field oxide or STI region.
  • a larger-surface insulating region IG′ is realized in the area of the thin-film transistor TFT.
  • a gate dielectric GD B for the CMOS transistor realized in the bulk material of the semiconductor body HLK is deposited over the entire surface.
  • the first polysilicon layer is produced over a large area and with a thickness, 0.3 ⁇ m, for example, that is suitable for the gate electrodes, and is doped or undoped.
  • FIG. 3B shows the arrangement at this process stage.
  • a spacer structure SP is realized in a known conventional manner around the gate electrode G B of the CMOS transistor.
  • the same spacer technology can be used for the thin-film transistor, but it is not necessary.
  • a gate dielectric GD D for the gate on the TFT side is produced in the next step. This dielectric, an oxide in particular, can again be deposited or thermally produced. In the case of a deposition of the gate dielectric, that can take place over the entire surface in order to serve two steps later as an etch-stop for the structuring of the second polysilicon layer.
  • the second polysilicon layer PS2 is deposited over the entire surface with a thickness of, for example, 0.1-0.3 ⁇ m.
  • the initially undoped layer is subsequently provided in a first step with doping suitable as a body doping for the thin-film transistor TFT.
  • doping suitable as a body doping for the thin-film transistor TFT.
  • a p-doping is imparted by means of implantation.
  • the source and drain regions for the two transistor types are defined in common by producing an implantation mask, for example, by structuring a resist film, and by applying a high doping for the source and drain regions by means of implantation wherein again an n + -doping or a p + -doping can be produced.
  • the implantation is self-adjusting with respect to the gate electrode GD B in the CMOS transistor area.
  • mask openings are created, whose respective edge facing the gate electrode G D does not directly adjoin the gate electrode, but is separated from the gate by d reserve strip TA.
  • FIG. 2 shows the finished thin-film transistor TFT in a plan view.
  • the region TA eliminated from doping, which corresponds to the reserve strip of the implantation mask, is clearly recognizable. This has the effect that the source and the drain are each removed from the edge of the gate G by an offset of length L OFF .
  • the second polysilicon layer in the region of the thin-film transistor outside of source S and drain D has only body doping, for instance, the aforementioned p-type doping.
  • the gate G and the second polysilicon layer PS2 are each structured in a strip shape in the area of the thin-film transistor TFT in such a manner that they cross one another.
  • these active regions of the transistors are electrically connected via contacts, in particular, via source contacts SK, drain contacts DK and gate contacts GK. They can be connected in a later step by structuring contact holes and filling these contact holes with conductive material, in particular, with tungsten.
  • FIG. 3D shows the arrangement at this process stage in a schematic cross section.
  • FIG. 3D shows an additional detail of the method according to an embodiment of the invention, in which the second polysilicon layer PS2 is used for producing not only the source, drain and body of the thin-film transistor but also the component structures in the area of the CMOS transistor, for instance, conductive connections which, for example, run directly over the insulating regions IG.
  • additional structures can be produced in intermediate layers under the second polysilicon layer.
  • Both transistors typically become fully functional in a number of thermal steps that can be carried out in various subsequent process stages.
  • the doping of the source and drain of the CMOS transistor is activated.
  • the temperature budget that is expended in the area of the thin-film transistor leads to a diffusion of the doping substances from the source and drain in the direction of the body, with a region TA (see FIG. 2 ) being produced in the area of the reserve strip, in which a doping gradient is formed that produces a gradual transition between the high doping of the source and drain and the relatively weak body doping.
  • An advantageous body doping lies in the range from 10 16 cm ⁇ 3 -10 17 cm ⁇ 3 .
  • the doping material gradient in the transition area TA brings about a uniform field distribution, which avoids high field peaks between the gate and the source or drain. This has the effect that the thin-film transistor that is obtained has a lowered leakage current.
  • the leakage current can be adjusted to a desired value, and in particular reduced, by enlarging the offset length L OFF , by means of the width of the transition region or the offset length with which the openings in the mask are offset from the gate during the doping of the source and drain of the thin-film transistor.
  • FIG. 4 shows a possible wiring of the thin-film transistor as a blocking diode.
  • the source S and the gate G are placed at the same potential or are electro-conductively connected to one another.
  • this transistor blocks the flow of current if there is a positive potential at terminal T 2 , but 0 V or a negative potential is present at terminal T 1 .
  • current can flow from T 1 to T 2 .
  • the thin-film transistor can thus fulfill a diode function, which allows the current to pass in only one direction.
  • a floating body is obtained in all cases, the potential of which is essentially determined by the forward-biased semiconductor junction.
  • the gate electrode In the forward direction, the gate electrode is at the same potential as the drain, with an inversion channel being formed.
  • gate, source and body In the blocking case, gate, source and body are at nearly the same potential and thereby produce the blocking effect.
  • a component according to the invention can also comprise, alternatively or in addition to the illustrated low-voltage transistor, a high-voltage CMOS transistor, into the production of which the production of the thin-film transistor can be equally well integrated.
  • the method according to the invention does not exclude additional method steps being performed before, between and after the above-mentioned method steps, in order to adapt the method in this specific case to the process steps for high-voltage CMOS technology.
  • a high-voltage CMOS transistor can comprise a drain-side drift region between the gate and the drain.
  • An additional insulation region can run above the drift region, with the gate electrode of the CMOS transistor then being situated in part on this additional insulation region.
  • the structure of the thin-film transistor is also presented only in principle in FIG. 1 and can differ therefrom in details. Nor is the structuring of the second polysilicon layer on the side of the thin-film transistor limited to the geometry presented in FIG. 2 .
  • CMOS transistor and a thin-film transistor in a joint process, only one additional step with respect to the known CMOS process being required for integration of the thin-film transistor.
  • This facilitates the production of the component and leads to a fully insulated thin-film transistor that is almost completely decoupled from the substrate and the active component structures realized therein.
  • the component can be produced in standardized CMOS technology without having to adapt its parameters, except for the mask structures.
  • the thin-film transistor can be used as a high-speed switching transistor, wherein source/drain breakdown voltages of approximately 20 V can be achieved.
  • the thin-film transistor can serve as a fast switching transistor for a semiconductor memory element comprising the CMOS transistors.

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  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
US12/375,529 2006-07-28 2007-07-25 Component comprising a thin-film transistor and CMOS-transistors and methods for production Expired - Fee Related US8008664B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102006035073.1A DE102006035073B4 (de) 2006-07-28 2006-07-28 Halbleiterbauelement mit einem Dünnfilmtransistor und CMOS-Transistoren, Verfahren zur Herstellung eines solchen Bauelements sowie Verwendung eines solchen Bauelements
DE102006035073 2006-07-28
DE102006035073.1 2006-07-28
PCT/EP2007/057675 WO2008012332A1 (de) 2006-07-28 2007-07-25 Bauelement mit einem dünnfilmtransistor und cmos-transistoren sowie verfahren zur herstellung

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