US7808418B2 - High-speed time-to-digital converter - Google Patents

High-speed time-to-digital converter Download PDF

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Publication number
US7808418B2
US7808418B2 US12/041,403 US4140308A US7808418B2 US 7808418 B2 US7808418 B2 US 7808418B2 US 4140308 A US4140308 A US 4140308A US 7808418 B2 US7808418 B2 US 7808418B2
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signal
delay
flip
flop
delayed
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US20090219187A1 (en
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Bo Sun
Zixiang Yang
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Qualcomm Inc
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Qualcomm Inc
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Priority to US12/041,403 priority Critical patent/US7808418B2/en
Priority to TW098106873A priority patent/TW200943734A/zh
Priority to PCT/US2009/035908 priority patent/WO2009111491A1/en
Priority to JP2010549822A priority patent/JP2011517160A/ja
Priority to EP09716634A priority patent/EP2250732A1/en
Priority to CN2009801073613A priority patent/CN102089983A/zh
Priority to KR1020107021650A priority patent/KR20100130205A/ko
Publication of US20090219187A1 publication Critical patent/US20090219187A1/en
Publication of US7808418B2 publication Critical patent/US7808418B2/en
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]

Definitions

  • the disclosure relates to the design of time-to-digital converters (TDC's), and more specifically, to the design of TDC's having sub-unit delay resolution.
  • Time-to-digital converters are designed to generate a digital representation of a time interval elapsing between two events.
  • TDC's discretize time intervals, just as analog-to-digital converters (ADC's) discretize analog signal amplitudes.
  • ADC's analog-to-digital converters
  • the difference between an actual time interval and the discretized version of that time interval is known as the quantization error, and is determined by the TDC resolution.
  • TDC resolution is typically limited by the delay of a unit cell in a delay line of the TDC.
  • the delay may be the gate delay of an inverter, which is a characteristic of the particular semiconductor processing technology employed.
  • An aspect of the present disclosure provides a time-to-digital converter comprising a delay line for generating a delayed version A(m) of a signal A, wherein A(m) is delayed relative to A by m delay units; and a sampling mechanism for sampling a difference between A(m) and a signal B[A(m)] at a time instant, wherein B[A(m)] is delayed relative to A by at least one delay unit.
  • Another aspect of the present disclosure provides a method for converting a time interval to a digital representation, the method comprising generating at least one delayed version A(m) of a signal A, wherein A(m) is delayed relative to A by m delay units; and sampling a difference between A(m) and a signal B[A(m)] at a time instant, wherein B[A(m)] is delayed relative to A by at least one delay unit.
  • TDC time-to-digital converter
  • Yet another aspect of the present disclosure provides a computer program product for converting a time interval to a digital representation, the product comprising computer-readable medium comprising code for causing a computer to generate at least one delayed version A(m) of a signal A, wherein A(m) is delayed relative to A by m delay units; and code for causing a computer to sample a difference between A(m) and a signal B[A(m)] at a time instant, wherein B[A(m)] is delayed relative to A by at least one delay unit.
  • FIG. 1 depicts an implementation of a portion of a prior art TDC.
  • FIG. 2 illustrates an example of the timing of the signals depicted in FIG. 1 .
  • FIG. 3 depicts an embodiment according to the present disclosure for achieving sub-inverter delay resolution.
  • FIG. 4 illustrates an example of the timing of the differential input signal coupled to an interpolating flip-flop ADQ.m, in comparison with the timing of the differential input signals coupled to flip-flops DQ.m and DQ.(m+1).
  • FIG. 5 depicts the steps according to a method of the present disclosure.
  • FIG. 1 depicts an implementation of a portion of a prior art TDC.
  • inverting buffers B.n each having a delay T D , form a delay line 100 .
  • the delay line 100 generates progressively delayed versions A(n) of an original single-ended signal A, wherein n is an index ranging from zero (no delay) up to the maximum delay of the delay line 100 .
  • A′ complementary to A.
  • the signals A and A′ are logical inverses of each other, and allow for differential signal processing in the TDC datapath. Advantages of differential processing over single-ended processing are well-known in the art, and include, for example, better rejection of common-mode noise at the inputs and outputs of the flip-flops.
  • A′ is provided with its own delay line 110 , which generates progressively delayed versions A′(n) of A′ using inverting buffers B′.n.
  • FIG. 1 further depicts a plurality of differential D-Q flip-flops 120 .
  • Each D-Q flip-flop is designed to sample the voltage (or current) difference at its differential input D/D′ on the rising edge of a signal REF.
  • the nomenclature X/Y denotes a differential signal composed of single-ended signals X and Y.
  • Each flip-flop provides a logical value of the sampled voltage difference at its differential input to the differential flip-flop output Q/Q′ at a subsequent time. For example, in an embodiment, if the single-ended input D has a voltage level higher than the voltage level of single-ended input D′, then the differential output Q/Q′ may generate a level of HIGH at a subsequent time, and vice versa. In this specification, a logical level of HIGH will be associated with a positive differential input signal D/D′ for ease of description.
  • One of ordinary skill in the art will realize that the discussion applies also to the reverse convention.
  • TDC implementations may employ differential sampling mechanisms other than D-Q flip-flops.
  • the techniques of the present disclosure may be readily applied to such alternative implementations.
  • each flip-flop DQ.n is coupled to a corresponding differential input A(n)/A′(n) tapped from the delay lines 100 and 110 . It is seen that collectively, the flip-flops DQ.n simultaneously sample the progressively delayed versions A(n)/A′(n) of the differential signal A/A′ on the rising edge of REF.
  • the plurality of flip-flop outputs Q/Q′ may be coupled to a decoder (not shown)
  • the TDC may output a discretized representation (not shown) of the relative timing thus measured.
  • FIG. 2 illustrates an example of the timing of the signals depicted in FIG. 1 .
  • plot 200 shows a rising edge of the signal REF at time t s .
  • Plot 210 shows a differential signal A(m)/A′(m) coupled to the input D/D′ of flip-flop DQ.m, wherein m is the index to the specific instance of the signals depicted.
  • Plot 220 shows the differential signal A(m+1)/A′(m+1) coupled to the input D/D′ of flip-flop DQ.(m+1).
  • DQ.(m+1) is the flip-flop that immediately follows the flip-flop DQ.m in the flip-flops 120 of FIG. 1 .
  • flip-flop DQ.m samples a logical LOW on the rising edge of REF at time t s
  • flip-flop DQ(m+1) also samples a logical LOW at t s
  • the two consecutive LOW's sampled by flip-flops DQ.m and DQ.(m+1) indicate that a logical transition occurs in the signal A during a time interval from m T D to (m+1) T D prior to the rising edge of REF.
  • the resolution of the prior art TDC in FIG. 1 is limited to a single inverter delay T D , the TDC is unable to determine the timing of the logical transition to an accuracy better than ⁇ T D /2.
  • the resolution of the TDC in FIG. 1 may alternatively be understood with reference to the difference between the zero-crossing times of consecutively delayed versions of the original signal A/A′.
  • a zero-crossing time represents the time at which a differential signal transitions from logical HIGH to logical LOW, or vice versa.
  • time instants t(m) and t(m+1) reflect the zero-crossing times for differential signals A(m)/A′(m) and A(m+1)/A′(m+1), respectively.
  • the timing resolution of the TDC may be computed as t(m+1)-t(m), which corresponds to the delay T D of a single delay buffer. To improve the resolution of the TDC, it would be desirable to decrease the difference between consecutive zero-crossing times available in the TDC.
  • sub-inverter delay resolution may be achieved by utilizing an alternative TDC architecture, such as depicted in FIG. 3 .
  • a set 330 of “interpolating” flip-flops ADQ.n is provided in addition to the set 320 of D-Q flip-flops DQ.n.
  • Each interpolating flip-flop ADQ.n samples a differential input D/D′ to produce a differential output Q/Q′.
  • the D input to each ADQ.n is coupled to the signal A(n) generated by delay line 300
  • the D′ input is coupled to the signal A(n+1) generated by delay line 300 .
  • the D and D′ inputs to ADQ.n are seen to be inverted versions of each other, spaced one unit delay apart, e.g., one inverter delay.
  • instances of a dummy load “LOAD” are provided to the delay line 310 to balance the loading on delay line 310 with the loading on delay line 300 .
  • FIG. 4 illustrates an example of the timing of the differential input signal coupled to a single flip-flop ADQ.m, in comparison with the timing of the differential input signals coupled to DQ.m and DQ.(m+1).
  • plot 400 shows the same reference signal REF as shown in FIG. 2 .
  • Plots 410 and 420 show differential signals A(m)/A′(m) and A(m+1)/A′(m+1) coupled to the inputs of DQ.m and DQ.(m+1), respectively.
  • Plot 415 shows the differential input signal A(m)/A(m+1) coupled to the inputs of ADQ.m.
  • the zero-crossing times are shown to be t(m) and t(m+1), respectively, similar to plots 210 and 220 in FIG. 2 .
  • the zero-crossing time for A(m)/A(m+1) is shown to be t′(m), which lies between t(m) and t(m+1).
  • the signal A may accordingly be sampled with a timing resolution less than the unit delay, e.g., the delay T D of a single inverter.
  • the actual delay of an interpolated signal relative to the original signal may be more or less than halfway between m T D and (m+1) T D .
  • factors affecting the actual delay of the interpolated signal may include imbalance in the rise and fall times of the buffers due to, e.g., device mismatches and/or process variations.
  • variations in the level of TDC sampling due to imbalance in rise and fall times may be factored into the TDC measurement by, e.g., monitoring the rise and fall times and cancelling out the expected inaccuracy from the final measurement.
  • the differential inputs to the flip-flops DQ.n may be successively flipped in polarity.
  • non-inverting buffers may be employed in place of the inverting buffers B.n shown in FIGS. 1 and 3 .
  • the input D/D′ to an interpolating D-Q flip-flop ADQ.n may be coupled to signals A(n)/A′(n+1), wherein A(n) is tapped from a first delay line corresponding to the original signal A, and A′(n+1) is tapped from a second delay line corresponding to the complementary signal A′.
  • zero-crossing times described are merely chosen to illustrate the behavior of the sampling mechanism near the TDC quantization boundaries.
  • One of ordinary skill in the art will realize that the zero-crossing times are mentioned for illustration purposes only, and that a typical differential input signal A may generally remain constant, without transitioning to another level, over an arbitrary period of time.
  • FIG. 5 depicts the steps according to a method of the present disclosure.
  • delayed versions A(n) and A′(n) of a signal A are generated at step 500 .
  • A(n)/A′(n) is sampled on the rising edge of REF.
  • A(n)/A(n+1) is also sampled on the rising edge of REF.
  • the samples are provided to a decoder for further processing.
  • the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
  • Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage media may be any available media that can be accessed by a computer.
  • such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.
  • any connection is properly termed a computer-readable medium.
  • the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave
  • the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.
  • Disk and disc includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
  • the instructions or code associated with a computer-readable medium of the computer program product may be executed by a computer, e.g., by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuitry.
  • processors such as one or more digital signal processors (DSPs), general purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuitry.

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  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
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Application Number Priority Date Filing Date Title
US12/041,403 US7808418B2 (en) 2008-03-03 2008-03-03 High-speed time-to-digital converter
EP09716634A EP2250732A1 (en) 2008-03-03 2009-03-03 High-speed time-to-digital converter
PCT/US2009/035908 WO2009111491A1 (en) 2008-03-03 2009-03-03 High-speed time-to-digital converter
JP2010549822A JP2011517160A (ja) 2008-03-03 2009-03-03 高速時間ディジタル・コンバータ
TW098106873A TW200943734A (en) 2008-03-03 2009-03-03 High-speed time-to-digital converter
CN2009801073613A CN102089983A (zh) 2008-03-03 2009-03-03 高速时间-数字转换器
KR1020107021650A KR20100130205A (ko) 2008-03-03 2009-03-03 고속 시간-디지털 변환기

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EP (1) EP2250732A1 (zh)
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US20100271100A1 (en) * 2009-04-27 2010-10-28 Sun Microsystems, Inc. Minimal bubble voltage regulator
US20100271076A1 (en) * 2009-04-27 2010-10-28 Sun Microsystems, Inc. Precision sampling circuit
US20100271099A1 (en) * 2009-04-27 2010-10-28 Sun Microsystems, Inc. Fine grain timing
US8242823B2 (en) 2009-04-27 2012-08-14 Oracle America, Inc. Delay chain initialization
US20120319741A1 (en) * 2011-06-17 2012-12-20 Texas Instruments Incorporated Reduced crosstalk wiring delay effects through the use of a checkerboard pattern of inverting and noninverting repeaters
US8421661B1 (en) * 2011-11-01 2013-04-16 Postech Academy-Industry Foundation Noise-shaping time to digital converter (TDC) using delta-sigma modulation method
US9490831B2 (en) 2014-12-01 2016-11-08 Samsung Electronics Co., Ltd. Time-to-digital converter using stochastic phase interpolation
US9606228B1 (en) 2014-02-20 2017-03-28 Banner Engineering Corporation High-precision digital time-of-flight measurement with coarse delay elements

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KR101797625B1 (ko) 2012-02-16 2017-11-15 한국전자통신연구원 저전력 고해상도 타임투디지털 컨버터
US9337997B2 (en) * 2013-03-07 2016-05-10 Qualcomm Incorporated Transcoding method for multi-wire signaling that embeds clock information in transition of signal state
JP5747070B2 (ja) * 2013-12-07 2015-07-08 株式会社アイカデザイン 位相同期ループ回路及び発振方法
KR101621853B1 (ko) 2014-12-26 2016-05-17 연세대학교 산학협력단 데이터 송신 장치, 데이터 수신 장치 및 그를 이용하는 스마트 디바이스
CN106354001B (zh) * 2016-08-31 2019-03-12 中国科学院上海高等研究院 时间数字转换电路
US10848138B2 (en) 2018-09-21 2020-11-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for precision phase skew generation
US10928447B2 (en) * 2018-10-31 2021-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Built-in self test circuit for measuring phase noise of a phase locked loop
US20240045382A1 (en) * 2022-08-02 2024-02-08 Apple Inc. Multi-Chain Measurement Circuit

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Cited By (11)

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Publication number Priority date Publication date Assignee Title
US20100271100A1 (en) * 2009-04-27 2010-10-28 Sun Microsystems, Inc. Minimal bubble voltage regulator
US20100271076A1 (en) * 2009-04-27 2010-10-28 Sun Microsystems, Inc. Precision sampling circuit
US20100271099A1 (en) * 2009-04-27 2010-10-28 Sun Microsystems, Inc. Fine grain timing
US8179165B2 (en) * 2009-04-27 2012-05-15 Oracle America, Inc. Precision sampling circuit
US8198931B2 (en) 2009-04-27 2012-06-12 Oracle America, Inc. Fine grain timing
US8242823B2 (en) 2009-04-27 2012-08-14 Oracle America, Inc. Delay chain initialization
US8283960B2 (en) 2009-04-27 2012-10-09 Oracle America, Inc. Minimal bubble voltage regulator
US20120319741A1 (en) * 2011-06-17 2012-12-20 Texas Instruments Incorporated Reduced crosstalk wiring delay effects through the use of a checkerboard pattern of inverting and noninverting repeaters
US8421661B1 (en) * 2011-11-01 2013-04-16 Postech Academy-Industry Foundation Noise-shaping time to digital converter (TDC) using delta-sigma modulation method
US9606228B1 (en) 2014-02-20 2017-03-28 Banner Engineering Corporation High-precision digital time-of-flight measurement with coarse delay elements
US9490831B2 (en) 2014-12-01 2016-11-08 Samsung Electronics Co., Ltd. Time-to-digital converter using stochastic phase interpolation

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JP2011517160A (ja) 2011-05-26
TW200943734A (en) 2009-10-16
KR20100130205A (ko) 2010-12-10
CN102089983A (zh) 2011-06-08
EP2250732A1 (en) 2010-11-17
US20090219187A1 (en) 2009-09-03
WO2009111491A1 (en) 2009-09-11

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