US7193401B1 - Control circuit and control method for DC-DC converter - Google Patents

Control circuit and control method for DC-DC converter Download PDF

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US7193401B1
US7193401B1 US11/374,196 US37419606A US7193401B1 US 7193401 B1 US7193401 B1 US 7193401B1 US 37419606 A US37419606 A US 37419606A US 7193401 B1 US7193401 B1 US 7193401B1
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signal
phase
state
timing
accordance
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Morihito Hasegawa
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Cypress Semiconductor Corp
Morgan Stanley Senior Funding Inc
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a control circuit and a control method for a current mode control type DC—DC converter, more particularly, it relates to the prevention of a subharmonic oscillation occurring when an on-duty exceeds 50%.
  • FIG. 9 is a circuit diagram of a current mode DC—DC converter 100 of fixed off-time control.
  • a main switching transistor FET 1 When a main switching transistor FET 1 is turned on, an inductor current flowing through a choke coil L 1 is increased.
  • the inductor current fed back via an input terminal FB 1 becomes larger than an error amplification signal Vc, the transistor FET 1 is turned off only for a fixed time. After the fixed off-time, the transistor FET 1 is turned on again.
  • a start of an on-cycle of the transistor FET 1 of the DC—DC converter 100 is performed after the fixed off-time ends. That is, even if a load applied to the DC—DC converter 100 is suddenly increased, the transistor FET 1 cannot be turned on until the off-time of the DC—DC converter 100 ends. Thereupon, a problem is caused that a response delay of the DC—DC converter 100 to a sudden fluctuation of the load is generated.
  • the present invention was made, and it is an object of the present invention to provide a control circuit and a control method for a DC—DC converter capable of preventing a reduction of an output current and preventing a subharmonic oscillation of a coil current even in an area in which an on-duty exceeds 50%.
  • a control circuit of a current mode control type DC—DC converter that controls a main switching transistor in accordance with a clock signal, comprising: a timing adjustment circuit that outputs a timing signal for determining a timing for shifting the main switching transistor from a second state to a first state; and a phase comparator that detects a phase difference between the timing signal and the clock signal to output a phase difference signal to the timing adjustment circuit in accordance with the phase difference, wherein the timing adjustment circuit prolongs a delay time after the main switching transistor shifts from the first state to the second state until the timing adjustment circuit outputs the timing signal in accordance with an advance amount of a phase when the phase of the timing signal is more advanced than a phase of the clock signal, and the timing adjustment circuit shortens the delay time in accordance with a delay amount of a phase when the phase of the timing signal is delayed behind a phase of the clock signal.
  • a so-called fixed off-time type current mode control system DC—DC converter When a first state is a conductive state, a second state is a non-conductive state and a main switching transistor shifts from the first state to the second state in accordance with that an inductor current value becomes higher than a set value, a so-called fixed off-time type current mode control system DC—DC converter is constituted.
  • the first state when the first state is a non-conductive state, the second state is a conductive state and the main switching transistor shifts from the first state to the second state in accordance with that an inductor current value becomes lower than the set value, a so-called fixed on-time type current mode control system DC—DC converter is constituted.
  • a timing adjustment circuit outputs a timing signal for determining a timing for shifting the main switching transistor from the second state to the first state.
  • a phase comparator detects a phase difference between the timing signal and a clock signal to output a phase difference signal in accordance with the phase difference to the timing adjustment circuit.
  • a time after the main switching transistor shifts from the first state to the second state until the timing adjustment circuit outputs the timing signal is defined as a delay time.
  • the phase comparator detects that a phase of the timing signal is more advanced than a phase of the clock signal in a certain switching period to determine that a period of the timing signal is shorter than a period of the clock signal. And then, the phase comparator transmits this determination to the timing adjustment circuit via a phase difference signal. Accordingly, the timing adjustment circuit prolongs a delay time in accordance with an advance amount of the phase to prolong the period of the timing signal from the succeeding next switching period.
  • the phase comparator determines that a period of the timing signal is longer than a period of the clock signal to transmit this determination to the timing adjustment circuit via a phase difference signal. Accordingly, the timing adjustment circuit shortens the delay time in accordance with a delay amount of the phase to shorten the period of the timing signal from the succeeding next switching periods. As described above, a feed-back control of the delay time is performed by the phase comparator and the timing adjustment circuit.
  • a delay time in the current switching period is thus determined in accordance with a phase difference between a timing signal and a clock signal in a period before the current switching period. Accordingly, a phase difference between a timing signal and a clock signal generated in the current switching period does not have an influence on the delay time in the current switching period. And then, an inductor current value when the second state in the current switching period ends is made substantially equal to an average value of an inductor current value when the second state in the previous switching period ends. That is, a disturbance of an inductor current generated by a load fluctuation in the current switching period can be prevented from transmitting to the succeeding switching periods. Thus, a subharmonic oscillation can be prevented in the control circuit of the current mode control type DC—DC converter operating at a fixed frequency even if an on-duty is not less than 50%.
  • the delay time can be adjusted so that a period of the clock signal corresponds to a period of the timing signal and that the phase difference between the clock signal and the timing signal becomes zero. Accordingly, a switching period of the DC—DC converter equipped with the control circuit of the DC—DC converter according to the present invention can be made to synchronize with the clock signal. Thus, a switching frequency of the main switching transistor can be prevented from fluctuating depending on the input voltage.
  • a control method for a current mode control type DC—DC converter of the invention for controlling a main switching transistor in accordance with a clock signal comprises the steps of: detecting a phase difference between a shift timing when the main switching transistor shifts from a second state to a first state and the clock signal; shifting the main switching transistor from the first state to the second state in accordance with that an inductor current exceeds a set value after the shift of the main switching transistor to the first state; and delaying the shift timing in accordance with an advance amount of a phase when the phase of the previous shift timing is more advanced than a phase of the clock signal, and bringing the shift timing forward in accordance with an advance amount of a phase when the phase of the previous shift timing is delayed behind a phase of the clock signal, at the subsequent determination of the shift timing.
  • a step for detecting a phase difference detects a phase difference between a shift timing, in which the main switching transistor shifts from the second state to the first state, and a clock signal.
  • a step for shifting the main switching transistor from the first state to the second state is performed after the step for detecting a phase difference. The shift is performed in accordance with that an inductor current value exceeds the set value.
  • a step for adjusting the shift timing is performed after the step for shifting the main switching transistor from the first state to the second state.
  • a feed-back control of the shift timing is performed by the above-described steps.
  • a subharmonic oscillation can be thus prevented in the control circuit of the current mode control type DC—DC converter operating at the fixed frequency even if an on-duty is not less than 50%.
  • a switching frequency of the main switching transistor can be prevented from fluctuating depending on the input voltage.
  • FIG. 1 is a circuit diagram of a DC—DC converter 1 ;
  • FIG. 2 is a circuit diagram of a phase comparator FC
  • FIG. 3 is a circuit diagram of a delay circuit DLY
  • FIG. 4 is a timing chart of a current mode control type DC—DC converter
  • FIG. 5 is a timing chart of the DC—DC converter 1 (No. 1);
  • FIG. 6 is a timing chart of the DC—DC converter 1 (No. 2);
  • FIG. 7 is a timing chart of the DC—DC converter 1 (No. 3);
  • FIG. 8 is a circuit diagram of a DC—DC converter 1 a ;
  • FIG. 9 is a circuit diagram of a current mode DC—DC converter 100 of fixed off-time control.
  • the DC—DC converter 1 includes a control section 3 , a choke coil L 1 , a main switching transistor FET 1 , a synchronous rectification transistor FET 2 , a smoothing capacitor C 1 and a current sense resistor Rs.
  • an input voltage Vin is connected to an input terminal of the transistor FET 1 , and an input terminal of the choke coil L 1 is connected to an output terminal of the transistor FET 1 .
  • An output voltage Vout is outputted from an output terminal of the choke coil L 1 .
  • An output terminal DH of the control section 3 is connected to a control terminal of the transistor FET 1 .
  • An input terminal of the transistor FET 2 as a synchronous rectification switch circuit is grounded, and an output terminal thereof is connected to the input terminal of the choke coil L 1 .
  • An output terminal DL of the control section 3 is connected to a control terminal of the transistor FET 2 .
  • the smoothing capacitor C 1 is connected between the output terminal of the choke coil L 1 and a ground.
  • the output terminal of the choke coil L 1 is connected to an input terminal FB 1 of the control section 3 .
  • the control section 3 includes a voltage amplifier AMP 1 , an error amplifier ERA 1 , a voltage comparator COMP 1 , a flip-flop FF, an oscillator OSC, a phase comparator FC and a delay circuit DLY.
  • An output voltage Vout of the DC—DC converter applied to the FB 1 terminal of the control section 3 is divided at a connection node N 2 of an input resistor R 1 and a ground resistor R 2 which are connected in series between the FB 1 terminal and the ground.
  • a divided voltage at the node N 2 is inputted to an inverting input terminal of the error amplifier ERA 1 .
  • a reference voltage e 1 from the ground is inputted to a non-inverting input terminal of the error amplifier ERA 1 .
  • An error amplification signal Vc outputted from the error amplifier ERA 1 is inputted to an inverting input terminal of the voltage comparator COMP 1 .
  • An input terminal CS 1 is connected to a non-inverting input terminal of the voltage amplifier AMP 1 and the input terminal FB 1 is connected to an inverting input terminal of the Voltage amplifier AMP 1 in order to measure a voltage drop generated by a current flowing through the current sense resistor Rs.
  • An inductor current signal VIL outputted from the voltage amplifier AMP 1 is inputted to a non-inverting input terminal of the voltage comparator COMP 1 .
  • An output signal Vo 1 outputted from the voltage comparator COMP 1 is inputted to a reset input terminal R of the flip-flop FF.
  • Anon-inverting output terminal Q of the flip-flop FF is connected to the transistor FET 1 via the output terminal DH of the control section 3 .
  • a non-inverting output terminal *Q of the flip-flop FF is connected to the transistor FET 2 via the output terminal DL of the control section 3 .
  • An output terminal of the delay circuit DLY is connected to and a delay signal FP is inputted to one input terminal of the phase comparator FC.
  • An output terminal of the oscillator OSC is connected to and a reference clock signal FR is inputted to the other input terminal of the phase comparator FC.
  • An output terminal of the phase comparator FC is connected to and a comparison result signal CONT outputted from the phase comparator FC is inputted to the delay circuit DLY.
  • the delay signal FP outputted from the delay circuit DLY is inputted to a set input terminal S of the flip-flop FF and to the phase comparator FC.
  • the phase comparator FC includes a phase detection section 21 and an integrating section 22 .
  • the phase detection section 21 includes flip-flops FF 11 and FF 12 , AND-gates AND 1 and AND 2 and transistors M 1 and M 2 .
  • the reference clock signal FR is inputted to a reset input terminal R of the flip-flop FF 12 , and an output terminal of the AND-gate AND 2 is connected to a set input terminal S of the flip-flop FF 12 .
  • a signal ⁇ P outputted from an output terminal *Q of the flip-flop FF 11 and the delay signal FP are inputted to the AND-gate AND 2 .
  • a signal ⁇ R is outputted from a non-inverting output terminal Q of the flip-flop FF 12 .
  • the transistors M 1 and M 2 are connected between a source voltage Vdd and a grounded voltage Vss.
  • the signal ⁇ P is inputted to a gate of the transistor M 1 .
  • the signal ⁇ R is inputted to a gate of the transistor M 2 . Drains of the both transistors are connected with each other to be connected to the integrating section 22 .
  • the integrating section 22 includes a resistance element RI and a capacitor CI.
  • the comparison result signal CONT is outputted from the integrating section 22 .
  • a connective relationship of the flip-flop FF 11 is similar to that of the flip-flop FF 12 , and therefore a detailed explanation thereof will be omitted.
  • the delay circuit DLY includes a delay time control circuit 31 and a delay time generation circuit 32 .
  • the delay time control circuit 31 includes a resistance element R 11 and transistors M 11 to M 14 .
  • the transistors M 11 and M 12 and the transistors M 13 and M 14 respectively constitute current mirror circuits.
  • the comparison result signal CONT is inputted to the resistance element R 11 .
  • the delay time generation circuit 32 includes a constant current circuit CG, a capacitor C 11 , a voltage comparator COMP 11 , a reference voltage Vref and a transistor M 15 .
  • An output terminal of the constant circuit CG, a drain terminal of the transistor M 15 and one end of the capacitor C 11 are connected to a non-inverting input terminal of the voltage comparator COMP 11 .
  • a source terminal of the transistor M 15 is grounded.
  • An output signal SQ 1 is inputted to a gate terminal of the transistor M 15 .
  • the reference voltage Vref is inputted to an inverting input terminal of the voltage comparator COMP 11 .
  • the delay signal FP is outputted from the voltage comparator COMP 11 .
  • the current mode control type DC—DC converter of the fixed switching period has a constitution that an output signal from the oscillator OSC is inputted to the set input terminal S of the flip-flop FF. An on-timing of the transistor FET 1 is controlled by the oscillator OSC.
  • a waveform (dot line) of an inductor current signal VIL 100 is shown in FIG. 4 , the signal VIL 100 being in a steady state that an output voltage of the current mode control type DC—DC converter of the fixed switching period is stably outputted.
  • a switching period TT 100 is always kept fixed. All lower limit values of the inductor current signal VIL 100 at times t 100 and t 101 when the transistor FET 1 is turned on become a fixed bottom voltage Von.
  • the inductor current signal VIL 100 is increased at a tilt m 1 of a linear function with the passage of time.
  • the tilt m 1 is expressed by the following expression (1) with use of the on-time Ton 100 and an off-time Toff 100 of the transistor FET 1 and an inductance L of the choke coil L 1 .
  • m1 ( V in ⁇ V out)/L ⁇ T on100 Expression (1)
  • the inductor current signal VIL is decreased at a tilt m 2 of a linear function.
  • an inductor current signal VIL 101 in this case (solid line) is increased at the tilt m 1 in an on-time and is decreased at the tilt m 2 in an off-time.
  • a deviation amount ⁇ V 1 from the bottom voltage Von is generated in the inductor current signal VIL 101 at the next time t 101 .
  • the operation of the DC—DC converter 1 according to the present invention will be explained with reference to FIG. 5 to FIG. 8 .
  • the DC—DC converter 1 performs the operation of a non-fixed off-time of the transistor FET 1 and the operation which makes a switching frequency correspond to a clock frequency of the oscillator OSC in the steady state.
  • the DC—DC converter 1 performs the operation of a fixed off-time of the transistor FET 1 and the operation for preventing the subharmonic oscillation in a load fluctuation time.
  • the delay circuit DLY When the switching period TT 12 is started at the time t 10 , the delay circuit DLY outputs a high-level delay signal FP to set the flip-flop FF.
  • the flip-flop When the flip-flop is set, the transistor FET 1 is turned on and a current is supplied to a load from the input voltage Vin via the choke coil L 1 , therefore an inductor current signal VIL 11 is raised.
  • the output signal SQ 1 outputted from the non-inverting output terminal Q makes a transition to high-level in accordance with that the flip-flop FF is brought into a set state.
  • the delay circuit DLY changes the delay signal FP to low-level without delay as described below.
  • the output signal Vo 1 of the voltage comparator COMP 1 makes a transition from low-level to high-level.
  • the output signal Vo 1 subjected to the transition to high-level is inputted to the reset input terminal R so that the flip-flop is reset.
  • the output signal SQ 1 is turned into low-level, and the main transistor FET 1 is brought into a non-conductive state. Further, an output signal SQB 1 is turned into high-level, and the synchronous rectification transistor FET 2 is brought into a conductive state.
  • the delay signal FP as a high-level pulse signal is outputted from the delay circuit DLY at the time t 12 after the passage of a prescribed delay time DT 12 determined by the delay circuit DLY.
  • the delay circuit DLY is a circuit which outputs the delay signal FP as a high-level pulse signal after the passage of a prescribed delay time DT from an input of a trailing edge of the output signal SQ 1 .
  • the delay circuit DLY further has performance for adjusting a value of the delay time DT in accordance with a value of the comparison result signal CONT.
  • a value of a delay time DT 11 in the preceding period is increased or decreased in accordance with a phase difference between the reference clock signal FR and the delay signal FP at the time t 10 so that a value of the delay time DT 12 can be obtained as described below.
  • the phase of the reference clock signal FR and the phase of the delay signal FP are uniform at the time t 10 , and therefore an increase/decrease amount of the value of the delay time DT 11 is zero, and the value of the delay time DT 12 becomes equal to that of DT 11 .
  • phase comparator FC Operation of the phase comparator FC from the time t 12 to a time t 13 will be explained with reference to FIG. 2 .
  • the high-level delay signal FP and a high-level signal ⁇ P are inputted to the AND-gate AND 2 .
  • a high-level signal outputted from the AND-gate AND 2 is inputted to the set input terminal S of the flip-flop FF 12 .
  • the signal ⁇ R makes a transition to high-level (arrow Y 12 ) so that the transistor M 2 becomes conductive.
  • a high-level reference clock signal FR delayed by a time P 2 to the delay signal FP is inputted to the reset input terminal R of the flip-flop FF 12 at the time t 13 .
  • the signal ⁇ R makes a transition to low-level (arrow Y 13 ) so that the transistor M 2 is brought into anon-conductive state.
  • a signal ⁇ R is generated by the flip-flop FF 12 , the signal ⁇ R being a positive pulse signal during the time equivalent to the time P 2 corresponding to a delay amount of the phase from a rising edge of the delay signal FP to a rising edge of the reference clock signal FR.
  • a PMW signal DO outputted from the phase detection section 21 is turned into low-level while the signal ⁇ R is high-level. That is, the phase detection section 21 serves as a PWM circuit which outputs a low-level signal during the time difference when the phase of the delay signal FP is more advanced than the phase of the reference clock signal FR.
  • a capacitor CI of the integrating section 22 is discharged in the time P 2 in accordance with an input of a low-level PMW signal DO. Accordingly, a voltage value of the comparison result signal CONT outputted from the integrating section 22 lowers in accordance with the PMW signal DO.
  • the comparison result signal CONT is inputted to the delay time control circuit 31 of the delay circuit DLY.
  • a current i 2 in prosection to the comparison result signal CONT flows through the transistor M 11 . Since the transistor M 11 and M 12 constitute the current mirror circuit, the current i 2 flows through the transistor M 12 .
  • a current flowing through the transistor M 12 and a current flowing through the transistor M 13 are the same, so the current i 2 flows through the transistor M 13 .
  • the current i 2 further flows through the transistor M 14 since the transistor M 13 and M 14 constitute the current mirror circuit. Since the transistor M 14 is connected in parallel with the constant current circuit CG, a current charging a capacitor C 11 of the delay circuit is equal to the total of a current i 1 flowing through the constant current circuit CG and the current i 2 .
  • the transistor M 15 When the output signal SQ 1 makes a transition from high-level to low-level at the time t 14 , the transistor M 15 is turned off. Therefore, the capacitor C 11 is charged by the current i 1 flowing through the constant current circuit CG and the current i 2 . A voltage of the capacitor C 11 is raised for a time determined by the i 1 and i 2 fed into the capacitor C 11 and a time constant of the capacitor C 11 . When the voltage of the capacitor C 11 becomes equal to or more than the reference voltage Vref, the voltage comparator COMP 11 outputs the high-level delay signal FP, and a delay time DT 13 ends. That is, the delay time DT is determined by a charging time of the capacitor C 11 .
  • the delay time DT 13 becomes longer than the delay time DT 12 .
  • a feed-back control is performed that the delay time DT 13 in the current switching period TT 13 is adjusted in accordance with a phase difference between the delay signal FP and the reference clock signal FR in the switching period TT 12 before the current switching period TT 13 .
  • a delay time DT 14 can be obtained that the clock period TT 11 of the reference clock signal FR corresponds to a period TT 12 a of the delay signal FP and that a phase difference between the reference clock signal FR and the delay signal FP becomes zero.
  • the delay circuit DLY outputs the high-level delay signal FP to set the flip-flop FF so that an inductor current signal VIL 21 is raised (arrow Y 20 ).
  • the flip-flop FF is reset, and the low-level output signal SQ 1 is inputted to the delay circuit DLY.
  • a delay signal FP as a high-level pulse signal is outputted from the delay circuit DLY (area A 21 ).
  • a value of a delay time DT 21 in a preceding switching period TT 21 is increased or decreased in accordance with a phase difference between the reference clock signal FR and the delay signal FP at the time t 20 so that a value of the delay time DT 22 can be obtained.
  • the phase of the reference clock signal FR and the phase of the delay signal FP are uniform at the time t 20 , therefore an increase/decrease amount of the value of the delay time DT 21 becomes zero. Accordingly, the value of the delay time DT 22 becomes equal to the value of the delay time DT 21 .
  • the phase comparator FC can generate a signal ⁇ P, which is a positive pulse signal during the time equivalent to a time P 3 corresponding to a delay amount of the phase of the delay signal FP from the reference clock signal FR, from a time T 22 to the time T 23 .
  • the PMW signal DO outputted from the phase detection section 21 is turned into high-level while the signal (DP is high-level. Accordingly, the voltage value of the comparison result signal CONT outputted from the integrating section 22 is raised in accordance with the PMW signal DO, therefore a delay time in a switching period from the time t 23 becomes shorter than the delay time DT 22 .
  • the delay time DT 14 can be obtained that the clock period TT 11 of the reference clock signal FR corresponds to the period TT 12 a of the delay signal FP and a phase difference between the reference clock signal FR and the delay signal FP becomes zero, by the above-described feed-back control.
  • an inductor current signal VIL 1 (broken line) being in a steady state is changed to an inductor current signal VIL 32 (solid line) by increase of an inductor current signal by a deviation amount ⁇ V 0 from the bottom voltage Von at a time 30
  • the inductor current signal VIL 32 is increased at the tilt m 1 in an on-time Ton 1 of the transistor FET 1 .
  • the output signal Vo 1 of the voltage comparator COMP 1 makes a transition from low-level to high-level, the flip-flop FF is reset, and the output signal SQ 1 is inverted into low-level.
  • the output signal SQ 1 is turned into low-level during a prescribed delay time DT 31 determined by the delay circuit DLY, the transistor FET 1 is turned off during the delay time DT 31 . Further, the inductor current signal VIL 32 is decreased at the tilt m 2 during the delay time DT 31 .
  • the delay time DT 31 in a switching period TT 31 can be obtained by feed-back of a phase difference between a timing signal and a clock signal in a period before the switching period TT 31 . Accordingly, even if a phase difference between the delay signal FP and the reference clock signal FR is caused by the load fluctuation, etc., in the switching period TT 31 , the delay time DT 31 in the switching period TT 31 does not fluctuate to become equal to a delay time DT 30 . Further, the inductor current signal VIL 32 is decreased at the tilt m 2 during the delay time DT 31 so that a value of the inductor current signal VIL 32 becomes equal to the bottom voltage Von at a time t 33 when the delay time DT 31 ends (area A 30 ). Thus, a deviation amount of the inductor current signal VIL 32 from the bottom voltage Von during the on-time of the transistor FET 1 generated at the time t 30 is converged at the time t 33 .
  • a feed-back control is performed that the delay time DT in the current switching period is adjusted in accordance with a phase difference between the delay signal FP and the reference clock signal FR in a switching period before the current switching period.
  • an off-time Toff can be adjusted so that a clock period of the reference clock signal FR corresponds to a switching period of the DC—DC converter and that the phase of rising edge of the reference clock signal FR and a phase of a rising edge of a switching timing become uniform. Accordingly, the switching period of the DC—DC converter provided with the control circuit of the DC—DC converter according to the present invention can be synchronized with the clock period. Further, the switching period can be prevented from fluctuating depending on the input voltage Vin.
  • the control circuit of current mode control type DC—DC converter controls the main switching transistor FET 1 in accordance with the reference clock signal FR being in the steady state that the output voltage of the DC—DC converter is stably outputted, therefore an off-time is not fixed, and therefore a switching frequency can be synchronized with the reference clock signal FR.
  • off-times are fixed every switching period by the feed-back control between the phase comparator FC and the delay circuit DLY during the over response when an output current is changed by the load fluctuation so that the subharmonic oscillation can be prevented. Since the off-time is thus brought into a semi-fixed state, the subharmonic oscillation can be prevented even if the on-duty of the transistor FET 1 is not less than 50%, and the switching frequency can be prevented from fluctuating depending on the input voltage Vin.
  • a DC—DC converter 1 a according to a second embodiment of the present invention will be explained with reference to FIG. 8 .
  • a control circuit of the DC—DC converter 1 a includes a control section 3 a in place of the control section 3 of the DC—DC converter 1 shown in FIG. 1 .
  • the control section 3 a further includes voltage comparators COMP 2 and COMP 3 , an AND-gate AND 3 and OR-gate OR 1 to the control section 3 .
  • An output terminal of the error amplifier ERA 1 is connected to the inverting input terminal of the voltage comparator COMP 1 and a non-inverting input terminal of the voltage comparator COMP 3 .
  • a reference voltage e 3 is connected to an inverting input terminal of the voltage comparator COMP 3 .
  • An output terminal of the voltage comparator COMP 3 is connected to one input terminal of the AND-gate AND 3 , and the output terminal of the delay circuit DLY is connected to the other input terminal of the AND-gate AND 3 .
  • the node N 2 is connected to an inverting input terminal of the voltage comparator COMP 2
  • the reference voltage e 2 is connected to a non-inverting input terminal of the voltage comparator COMP 2 .
  • An output terminal of the AND-gate AND 3 and an output terminal of the voltage comparator COMP 2 are connected to an input terminal of the OR-gate OR 1 .
  • An output terminal of the OR-gate OR 1 is connected to the set input terminal S of the flip-flop FF.
  • Output signals of Vo 2 and Vo 3 are respectively outputted from the voltage comparators COMP 2 and COMP 3 .
  • Each of the reference voltages e 2 and e 3 has an individual prescribed value. Moreover, other constitutions are similar to those of the control section 3 shown in FIG. 1 , and therefore a detailed explanation thereof will be omitted hereinafter.
  • the voltage comparator COMP 2 is a circuit which aims to enable the DC—DC converter 1 a to respond to a sudden load fluctuation at high speed.
  • the voltage comparator COMP 2 is a circuit which aims to enable the DC—DC converter 1 a to respond to a sudden load fluctuation at high speed.
  • a high-level output signal Vo 2 is outputted from the voltage comparator COMP 2 .
  • the reference voltage e 2 is a voltage value previously determined in accordance with a lower limit value of the output voltage Vout.
  • the high-level output signal Vo 2 is inputted to the set input terminal S before a timing of input of the high-level delay signal FP.
  • the flip-flop FF is forcibly set before the passage of the off-time Toff, and the off-time Toff is forcibly terminated.
  • the output signal SQ 1 makes a transition from low-level to high-level, and a high-level output signal SQ 1 is inputted to the delay circuit DLY.
  • the transistor M 15 (see FIG. 3 ) becomes conductive in accordance with the high-level output signal SQ 1 , and the capacitor C 11 brought into a charging state is immediately discharged. Accordingly, a delay time generated in the delay circuit DLY is cancelled, and the delay signal FP is kept-low-level.
  • the high-level output signal Vo 1 is inputted to the reset input terminal R so that the flip-flop FF is reset. Thereafter, the above-described operations are repeated.
  • the transistor FET 1 can be forcibly brought in to an on-state. Accordingly, a high-speed response to the sudden load fluctuation can be realized.
  • the error amplifier ERA 1 amplifies a difference between the divided voltage value at the node N 2 of the output voltage Vout and the reference voltage e 1 to output the error amplification signal Vc.
  • the voltage comparator COMP 3 compares the error amplification signal Vc with the reference voltage e 3 .
  • the reference voltage e 3 is a voltage previously determined in accordance with an upper limit value of the output voltage Vout.
  • the error amplification signal Vc becomes lower than the reference voltage e 3 , and the voltage comparator COMP 3 outputs a low-level output signal Vo 3 .
  • the AND-gate AND 3 masks the delay signal FP.
  • the off-time Toff of the transistor FET 1 ends.
  • the delay signal FP is masked, and therefore the flip-flop FF is maintained in a reset state and the transistor FET 1 is maintained in an off-state. Accordingly, the output voltage Vout of the DC—DC converter can be prevented from rising.
  • the output voltage Vout of the DC—DC converter 1 a becomes lower than the upper limit value
  • the error amplification signal Vc becomes higher than the reference voltage e 3
  • the voltage comparator COMP 3 outputs a high-level output signal Vo 3 .
  • the AND-gate AND 3 stops masking the delay signal FP. Accordingly, the flip-flop FF is brought into a set state in accordance with the high-level delay signal FP, and the output voltage Vout of the DC—DC converter is raised.
  • the switching period of the transistor FET 1 is controlled so as to correspond to the period of the reference clock signal FR of the oscillator OSC. Accordingly, even if the DC—DC converter 1 is in a non-load state, the transistor FET 1 is periodically brought into a conductive state. And then, the whole energy stored in the choke coil L 1 is used only for raising a voltage of the smoothing capacitor C 1 so that the output voltage Vout rises above a set voltage value.
  • the transistor FET 1 can be forcibly maintained in the off-state by the voltage comparator COMP 3 and the AND-gate AND 3 during the rising time when the output voltage Vout exceeds a set value set at the reference voltage e 3 . Accordingly, the output voltage Vout can be prevented from rising above the set voltage value.
  • the transistor FET 1 when the output voltage Vout of the DC—DC converter is reduced by the sudden load fluctuation, the transistor FET 1 can be forcibly brought into the on-state even if being in the off-time Toff. Accordingly, the high-speed response to the sudden load fluctuation can be realized.
  • the transistor FET 1 in the rising time when the output voltage Vout exceeds the set value set at the reference voltage e 3 , the transistor FET 1 can be forcibly maintained in the off-state. Accordingly, the output voltage Vout can be prevented from rising above the set voltage value.
  • the present invention is not limited to the embodiments described above, and that various improvements and modifications can be performed without departing from the scope of the present invention.
  • the fixed off-time type current mode control system DC—DC converter is explained in the present embodiments, but the present invention is not limited thereto. It is obvious that the present invention is also applicable to a fixed on-time type current mode control system DC—DC converter.
  • the error amplifier ERA 1 is connected to the non-inverting input terminal of the voltage comparator COMP 1
  • the voltage amplifier AMP 1 is connected to the inverting input terminal of the voltage amplifier AMP 1 .
  • the output terminal of the voltage comparator COMP 1 is connected to the set input terminal S of a flip-flop FF 1 .
  • the non-inverting output terminal Q is connected to the output terminal DH, and further connected to the reset input terminal R of the flip-flop FF 1 via the delay circuit DLY.
  • other constitutions are similar to those of the DC—DC converter 1 , and therefore an explanation in detail will be omitted hereinafter.
  • the voltage comparator COMP 1 When the inductor current signal VIL is reduced to the error amplification signal Vc, the voltage comparator COMP 1 outputs the high-level input signal Vo 1 to set the flip-flop FF 1 . Then, the flip-flop FF 1 is reset in accordance with that the delay circuit DLY outputs the high-level delay signal FP after the passage of the delay time DT.
  • the fixed on-time type DC—DC converter is constituted by repeating these operations.
  • the voltage comparator COMP 11 is employed in an output step in the delay circuit DLY of the present embodiment (see FIG. 3 ), but the present invention is not limited thereto.
  • a driver circuit may be employed in place of the voltage comparator COMP 11 .
  • the output signal SQ 1 is in a high-level state
  • a ground potential is inputted to the driver circuit so that a low-level delay signal FP is outputted from the driver circuit.
  • a voltage of the capacitor C 11 becomes equal to or more than a threshold voltage of the driver circuit after the passage of a prescribed time from a transition of the output signal SQ 1 to low-level, a high-level delay signal FP is outputted from the driver circuit.
  • the circuit can be simplified.
  • a step-down DC—DC converter is explained in the present embodiments.
  • a point of the present invention is that the feed-back control is performed that the delay time DT in the current switching period is adjusted in accordance with the phase difference between the delay signal FP and the reference clock signal FR in a switching period before the current switching period. Accordingly, it is obvious that the present invention is also applicable to a step-up DC—DC converter.
  • the delay signal FP is an example of a timing signal
  • the delay circuit DLY is an example of a timing adjustment circuit
  • the reference clock signal FR is an example of a clock signal
  • the comparison result signal CONT is an example of a phase difference signal
  • the transistor M 2 is an example of a second switch
  • the transistor M 1 is an example of a third switch
  • the reference voltage Vref is an example of a first set voltage
  • the reference voltage e 2 is an example of a second set voltage
  • the voltage comparator COMP 11 is an example of a first comparator
  • the voltage comparator COMP 2 is an example of a second comparator
  • the voltage comparator COMP 3 is an example of a monitoring circuit.
  • the subharmonic oscillation can be prevented even if the on-duty of the main switching transistor is not less than 50%, and the switching frequency can be prevented from fluctuating depending on the input voltage.

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US20070236971A1 (en) * 2006-04-07 2007-10-11 Yung-Chih Chen Reverse current preventing circuit with an automatic correction of reference
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US7948219B2 (en) * 2006-09-28 2011-05-24 Fujitsu Semiconductor Limited Control circuit of synchronous rectification type power supply unit, synchronous rectification type power supply unit and control method thereof
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CN102215037B (zh) * 2010-04-06 2013-10-02 安凯(广州)微电子技术有限公司 一种延迟信号产生电路
CN102215037A (zh) * 2010-04-06 2011-10-12 安凯(广州)微电子技术有限公司 一种延迟信号产生电路
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US20120274134A1 (en) * 2011-04-29 2012-11-01 Stmicroelectronics S.R.L. Dc-dc converter, method for operating the dc-dc converter, environmental energy harvesting system comprising the dc-dc converter, and apparatus comprising the energy harvesting system
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US9160223B2 (en) 2011-04-29 2015-10-13 Stmicroelectronics S.R.L. Rectifier circuit, and environmental energy harvesting system comprising the rectifier circuit
US20140029150A1 (en) * 2012-03-06 2014-01-30 Evan M. Fledell Interposer to regulate current for wafer test tooling
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US20130335052A1 (en) * 2012-06-14 2013-12-19 Chengdu Monolithic Power Systems Co., Ltd. High side buck converters and control methods thereof
US9106131B2 (en) * 2012-08-14 2015-08-11 Chengdu Monolithic Power Systems Co., Ltd. High side buck converters and control methods thereof
US9461504B2 (en) 2012-09-27 2016-10-04 Stmicroelectronics S.R.L. Enhanced efficiency energy-scavenging interface, method for operating the energy-scavenging interface, and energy-scavenging system comprising the energy-scavenging interface
US9954394B2 (en) 2012-09-27 2018-04-24 Stmicroelectronics S.R.L. Enhanced-efficiency energy-scavenging interface, method for operating the energy-scavenging interface, and energy-scavenging system comprising the energy-scavenging interface
US20140210445A1 (en) * 2013-01-28 2014-07-31 Fujitsu Semiconductor Limited Power supply control circuit, power supply device, electronic apparatus, and power supply control method
US9301278B2 (en) * 2013-01-28 2016-03-29 Socionext Inc. Power supply control circuit, power supply device, electronic apparatus, and power supply control method
US20160118893A1 (en) * 2014-10-23 2016-04-28 Qualcomm Incorporated Circuits and methods providing dead time adjustment at a synchronous buck converter
US9654002B2 (en) * 2014-10-23 2017-05-16 Qualcomm Incorporated Circuits and methods providing dead time adjustment at a synchronous buck converter
US20190044445A1 (en) * 2017-08-04 2019-02-07 Dialog Semiconductor (Uk) Limited Power Dissipation Regulated Buck Architecture
US10790746B2 (en) * 2017-08-04 2020-09-29 Dialog Semiconductor (Uk) Limited Power dissipation regulated buck architecture

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KR100718905B1 (ko) 2007-05-18
CN1980026A (zh) 2007-06-13

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