US7151462B2 - Circuit arrangement and method for load diagnosis of a semiconductor switch - Google Patents

Circuit arrangement and method for load diagnosis of a semiconductor switch Download PDF

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US7151462B2
US7151462B2 US10/909,017 US90901704A US7151462B2 US 7151462 B2 US7151462 B2 US 7151462B2 US 90901704 A US90901704 A US 90901704A US 7151462 B2 US7151462 B2 US 7151462B2
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current
connecting terminal
load
current direction
terminal
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US20050083086A1 (en
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Wolfgang Horn
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Infineon Technologies AG
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/18—Modifications for indicating state of switch
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches

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  • the present invention relates to a circuit arrangement and a method for load diagnosis of a semiconductor switch.
  • diagnostic function which, by way of example, serves for identifying an interruption of the line connection to a load connected to the semiconductor switch, or a short circuit of the output to which the load is connected, with respect to a supply potential.
  • diagnostic functions are employed both for high-side switches, in which the load is located between the semiconductor switch and a reference-earth potential and for low-side switches, in which the load is located between a supply potential, for example a battery, and the semiconductor switch.
  • a diagnostic circuit that carries out the diagnosis has to be doubly provided, namely a first diagnostic circuit at a first load terminal and a second diagnostic circuit at a second load terminal of the semiconductor switch.
  • a first diagnostic circuit at a first load terminal e.g., a first diagnostic circuit at a first load terminal
  • a second diagnostic circuit e.g., a second diagnostic circuit at a second load terminal of the semiconductor switch.
  • either the results of the first or the second diagnostic circuit are used in this case, which necessitates an initial initialization of the diagnostic circuit depending on the interconnection of the semiconductor switch and the load.
  • the known circuits are unable to carry out a diagnosis if the semiconductor switch is connected up in floating fashion, that is, if a load is located between supply potential and a first load terminal and a load is additionally located between the second load terminal and reference-earth potential.
  • One embodiment of the present invention provides a circuit arrangement and a method for load diagnosis of a semiconductor switch that can be used universally both for semiconductor switches in high-side operation and in low-side operation, without necessitating an initialization independently of the interconnection, and that are suitable in particular for diagnosis during floating operation of the semiconductor switch.
  • the circuit arrangement according to one embodiment of the invention for load diagnosis of a switch having a first and a second load connecting terminal comprises a first current source arrangement with a first connecting terminal, that can be connected to the first load connecting terminal of the switch.
  • the first current source arrangement is designed to supply a current in a first current direction to the first connecting terminal if the first load terminal is coupled to a first supply potential, and to supply a current in an opposite current direction to the first connecting terminal if the first load terminal is coupled to a second supply potential.
  • the circuit arrangement furthermore comprises a second current source arrangement with a second connecting terminal, which can be connected to the second load connecting terminal of the switch.
  • the second current source arrangement is designed to supply a current in a second current direction to the second connecting terminal if the second load terminal is coupled to the second supply potential, and to supply a current in an opposite direction to the second connecting terminal if the second load terminal is coupled to the first supply potential.
  • an evaluation circuit is present, which provides a load state signal depending on the said currents.
  • the load state signal assumes a first state, which indicates a fault-free operation, if a current flows in the first direction to the first connecting terminal and a current flows in the second direction to the second connecting terminal, that is, if the first connecting terminal is coupled to the first supply potential and the second connecting terminal is coupled to the second supply potential.
  • the load state signal assumes a second state, which indicates a first faulty operation, if no current flows to the first connecting terminal and/or if no current flows to the second connecting terminal. This state occurs if the first connecting terminal is coupled neither to the first supply potential nor to the second supply potential, that is, if the semiconductor switch turns off and a line connection between the semiconductor switch and the first supply potential is interrupted, which indicates, for example, chopping of the load.
  • the load state signal also assumes a second state when the semiconductor switch turns off and when a line connection between the second connecting terminal and the second supply potential is interrupted, which indicates, for example, chopping of a load connected between the said second load terminal and the said second supply potential.
  • This second fault state is indicated, independently of whether the semiconductor switch is operated as a high-side switch, as a low-side switch or as a switch arranged in floating fashion, as soon as one of the two loads undergoes chopping, that is, a current flow to one of the two connecting terminals is not possible.
  • the load diagnosis is effected, of course, when the semiconductor switch turns off since the first and second connecting terminals of the diagnostic circuit would otherwise be short-circuited.
  • the load state signal assumes a third state, which indicates a second faulty operation, if a current flows oppositely to the first current direction to the first connecting terminal and/or if a current flows oppositely to the second current direction to the second connecting terminal.
  • a current flows oppositely to the first current direction to the first connecting terminal when the first connecting terminal is not coupled to the first supply potential, but rather to the second supply potential, that is, when a load, for example, is incorrectly connected to the second supply potential, or causes a short circuit with respect to this supply potential.
  • the first current source arrangement which supplies, depending on the potential conditions at the first connecting terminal, a current in a first current direction or oppositely to the said first current direction to the first connecting terminal.
  • the second current source arrangement may correspondingly be realized as a current mirror which supplies a second reference current in the second current direction to the second connecting terminal if the second connecting terminal is connected to the second supply potential, and which supplies the current in a current direction opposite to the second current direction to the second connecting terminal if the second connecting terminal is connected to the first supply potential.
  • the second reference current is dependent on the current to the first connecting terminal. This leads to circuitry simplifications to the effect that only one reference current source has to be provided for the two current mirror arrangements. For example, in a fault case in which no current flows to the first connecting terminal, no current flows to the second connecting terminal either. This has the effect that a fault is indicated at the first connecting terminal with greater reliability and that, on the other hand, a diagnosis of the load state at the second connecting terminal does not occur. This does not have negative consequences, however, owing to the fault state indicated anyway at the first connecting terminal.
  • one embodiment of the invention provides for the sum of the currents to the first and second connecting terminals to be evaluated and for this sum to be compared with a first and a second reference value, which are of different magnitudes, in order to provide the load state.
  • a first and a second reference value which are of different magnitudes
  • the second reference value is greater than the first reference value
  • These three cases correspond to the three states of the load state signal indicating normal operation, the first fault state and the second fault state.
  • the method according to one embodiment of the invention for load diagnosis of a switch having a first and a second load connecting terminal provides for the provision of a first current source arrangement in accordance with the above explanations, which can be connected to the first load connecting terminal of the switch, a second current source arrangement in accordance with the above explanations, which can be connected to the second load connecting terminal of the switch, and for the evaluation of the currents flowing to the first and second connecting terminals in order to provide the load state signal.
  • FIG. 1 schematically illustrates a circuit arrangement according to the invention for load diagnosis of a semiconductor switch.
  • FIG. 2 illustrates the circuit in accordance with FIG. 1 together with a semiconductor switch used as a low-side switch for illustrating various fault states.
  • FIG. 3 illustrates a circuit arrangement in accordance with FIG. 1 with a semiconductor switch used as a high-side switch for illustrating various fault states.
  • FIG. 4 illustrates a circuit arrangement in accordance with FIG. 1 with a semiconductor switch used as a switch arranged in floating fashion for illustrating various fault states.
  • FIG. 5 illustrates an example of the circuitry realization of a current source arrangement for connection to a first connecting terminal.
  • FIG. 6 illustrates an example of the circuitry realization of a current source arrangement for connection to the second connecting terminal.
  • FIG. 7 illustrates an advantageous example of the circuitry realization of the first and second current source arrangements and of the evaluation circuit.
  • FIG. 8 illustrates the circuit arrangement in accordance with FIG. 7 together with a semiconductor switch used as a low-side switch for illustrating various fault states.
  • FIG. 9 illustrates a circuit arrangement in accordance with FIG. 7 together with a semiconductor switch used as a high-side switch for illustrating various fault states.
  • FIG. 10 illustrates a semiconductor switch used as a switch arranged in floating fashion for illustrating various fault states.
  • FIG. 11 illustrates, in tabular form, the switching states of output signals of the circuit in accordance with FIGS. 7–10 depending on various operating states.
  • FIG. 1 schematically illustrates an exemplary embodiment of a circuit arrangement according to one embodiment of the invention for load diagnosis of a semiconductor switch.
  • a semiconductor switch T designed as a MOSFET
  • the circuit arrangement comprises a first current source arrangement 10 with a first connecting terminal K 1 , which can be connected to a first load connecting terminal, the drain terminal D of the MOSFET T in the example.
  • the circuit arrangement furthermore comprises a second current source arrangement 20 with a second connecting terminal K 2 , which can be connected to a second load connecting terminal, the source terminal S of the MOSFET T in the example.
  • the first current source arrangement 10 is designed to supply a current I 2 to the first connecting terminal K 1 , the direction of the said current being dependent on whether the first connecting terminal K 1 is coupled to a first or a second supply potential, as will be explained below with reference to FIGS. 2–4 .
  • the first current direction of the current 12 corresponds to the current direction depicted in FIG. 1 , that is, a current flows from the first connecting terminal K 1 in the direction of the current source arrangement 10 .
  • the second current source arrangement 20 is designed to supply, depending on whether the second connecting terminal K 2 is connected to a first or a second supply potential, a current I 5 to the said second connecting terminal K 2 in a second direction or oppositely to the second direction.
  • a current I 5 to the said second connecting terminal K 2 in a second direction or oppositely to the second direction.
  • the second current direction corresponds to the current direction depicted in FIG. 1 , in the case of which the current I 5 flows from the second current source arrangement 20 to the second connecting terminal K 2 .
  • the circuit arrangement additionally comprises an evaluation circuit 30 , which evaluates the currents I 2 , I 5 to the first and second connecting terminals K 1 , K 2 at least with regard to their current direction, and which provides, depending on this evaluation, a load state signal ST dependent on the load state determined.
  • FIG. 2 illustrates the circuit arrangement for the diagnosis of a MOSFET T used as a low-side switch, in the case of which a load Z is connected between a first supply potential V, corresponding to a positive supply potential in the example, and drain terminal D of the said MOSFET.
  • the source terminal S of the MOSFET T is at a second supply potential GND, corresponding to reference-earth potential or earth in the exemplary embodiment.
  • the first connecting terminal K 1 of the diagnosis circuit is coupled to the first supply potential V via the load Z, so that the current I 2 flows in the first current direction illustrated, and the second connecting terminal K 2 is coupled to the second supply potential GND so that the current I 5 flows in the second current direction, that is to say from the second current source arrangement 20 to the second connecting terminal K 2 .
  • the evaluation circuit 30 supplies a load state signal ST which assumes a first state, which indicates a normal operation of the semiconductor switch.
  • the evaluation circuit 30 supplies a state signal ST which assumes a second state, which indicates this load interruption 1 .
  • a second fault state is designated by “2”, in the case of which the first connecting terminal K 1 is coupled to the second supply potential GND.
  • Such a fault may result for example from an incorrect connection of the load to the second supply potential GND instead of the first supply potential V.
  • the first current source arrangement 10 is designed, in the event of this fault case, to supply a current I 2 oppositely to the first current direction depicted in FIG. 2 .
  • the evaluation circuit 30 evaluating this current flow supplies a state signal ST which assumes a third operating state, which indicates this incorrect connection of the drain terminal D of the MOSFET T to reference-earth potential GND. It should be pointed out that in order to detect this fault state, the drain terminal D and the first connecting terminal K 1 , respectively, do not have to be connected directly to the second supply potential GND, rather this connection may, of course, also be effected via a load.
  • FIG. 3 illustrates the circuit arrangement for diagnosis of a MOSFET T used as a high-side switch, the drain terminal D of the MOSFET being connected to the first supply potential V and a load Z being connected between the source terminal S of the MOSFET and the second supply potential GND.
  • the first connecting terminal K 1 is thus coupled to the first supply potential V and the second connecting terminal K 2 is coupled, in disturbance-free operation, via the load Z to the second supply potential GND. Consequently, a current I 2 flows in the depicted direction from the first connecting terminal K 1 to the first current source arrangement 10 and a current I 5 flows in the depicted direction from the second current source arrangement 20 to the second connecting terminal K 2 .
  • FIG. 3 illustrates a fault case designated by “3” in the case of which there is an interruption between the source terminal S and the load Z. Consequently, with MOSFET T turned off, no current can flow, so that the evaluation circuit 30 provides a state signal ST with a second state, which indicates such load chopping.
  • FIG. 3 illustrates a further fault case, designated by “4” in the case of which the source terminal S is coupled to the first supply potential, which may be effected for example as a result of an incorrect connection of the load.
  • the current source arrangement 20 provides a current I 5 which flows counter to the current direction depicted in FIG. 3 .
  • the evaluation circuit 30 provides a load state signal ST with a third state, which indicates this incorrect connection of this source terminal S.
  • the source terminal S does not, of course, have to be connected directly to the first supply potential V, but rather may also be connected via a load to the said supply potential V.
  • FIG. 4 illustrates the circuit arrangement with a MOSFET T arranged in floating fashion in the case of which a first load Z 1 is connected between the first supply potential V and the drain terminal D and a second load Z 2 is connected between the source terminal S and the second supply potential GND.
  • the first connecting terminal K 1 is coupled to the first supply potential V via the first load Z 1 , thereby bringing about a current I 2 in the depicted direction through the current source arrangement 10 .
  • the second connecting terminal K 2 is coupled via the second load Z 2 to the second supply potential GND, thereby bringing about a current I 5 in the depicted second direction from the second current source arrangement 20 .
  • the evaluation circuit 30 provides a state signal ST with a first state, which indicates a disturbance-free operation.
  • “11” designates a fault case in which the connection between the first load Z 1 and the drain terminal D is interrupted, so that the current I 2 is zero.
  • the evaluation circuit 30 provides a state signal ST with a second state, indicating the load interruption.
  • “12” designates the fault case in which the connection between the second load Z 2 and the source terminal S is interrupted. In this case, the current I 5 becomes zero, so that the evaluation circuit 30 provides a load state signal which likewise has the second state, which indicates this load interruption.
  • “21” designates a fault case in which the drain terminal D of the MOSFET is coupled to the second supply potential GND.
  • the current source arrangement 10 brings about a current oppositely to the first current direction depicted in FIG. 4 .
  • the evaluation circuit 30 provides a state signal ST which has the third state, which indicates the incorrect interconnection of the said drain terminal D.
  • “22” designates the fault case in which the source terminal S is incorrectly coupled to the first supply potential V.
  • the second current source arrangement 20 brings about a current I 5 to the second connecting terminal K 2 which flows oppositely to the second current direction depicted in FIG. 4 .
  • the evaluation circuit 30 supplies a state signal which assumes the third state, which indicates this incorrect interconnection of the source terminal S.
  • the evaluation circuit 30 also supplies a state signal ST having the second state when both the fault case “11” and the fault case “12” are present.
  • a load state signal ST is provided which assumes the third state if both the fault case “21” and the fault case “22” are present.
  • FIG. 5 illustrates an example of the circuitry realization of the first current source arrangement, which brings about a current 12 in the first current direction depicted in FIGS. 1–3 or oppositely to this first current direction, depending on the polarity of the first connecting terminal K 1 .
  • the current source arrangement 10 comprises a reference current source Iq 1 , which supplies a reference current I 1 to a current mirror having a first and a second transistor M 1 , M 2 .
  • the current mirror transistors M 1 , M 2 are designed as n-channel MOSFET in the example.
  • the source terminals of these transistors M 1 , M 2 are connected to reference-earth potential via at least two diodes D 10 , D 11 , the anode of one of the two diodes being connected to the source terminals of the transistors M 1 , M 2 .
  • the two diodes D 10 , D 11 illustrated may also be designed in each case as a transistor connected up as a diode.
  • the transistor M 1 of the circuit is connected up as a diode.
  • the drain terminal of the other transistor M 2 is coupled to the first connecting terminal K 1 via a current sensing circuit 31 .
  • the transistor M 2 has an integrated backward or body diode, which is explicitly illustrated in the example and is designated by the reference symbol D 2 .
  • a current I 2 flows in the first direction from the said connecting terminal K 1 via the current mirror transistor M 2 and via the diodes D 10 , D 11 to reference-earth potential GND, this current I 2 being related to the reference current I 1 by way of the ratio of the current mirror M 1 , M 2 .
  • the reference current I 1 flows via the first current mirror transistor M 1 and the backward diode D 2 of the second current mirror transistor M 2 to the connecting terminal K 1 , so that a current flows counter to the first current direction depicted in FIG. 5 .
  • the voltage drop across the current sensing circuit 31 and across the line between the current sensing circuit 31 and reference-earth potential GND together is less than a diode forward voltage if a voltage which is less than twice a diode forward voltage is present between the source terminals of the two transistors M 1 , M 2 and reference-earth potential.
  • the use of at least two diodes in the diode chain D 10 , D 11 ensures that no current flows via this diode chain D 10 , D 11 to reference-earth potential GND, so that the current flows completely via the backward diode D 2 and the current sensing circuit 31 .
  • FIG. 6 illustrates an example of the circuitry realization for the second current source arrangement 20 .
  • This circuit arrangement comprises a second reference current source Iq 4 , which supplies a second reference current I 2 to a current mirror having two n-channel transistors M 3 , M 4 , the source terminals of which are connected to the second supply potential GND.
  • the circuit arrangement comprises a second current mirror having p-channel transistors M 5 , M 6 , the source terminals of which are connected to the first supply potential V via a diode chain having at least two diodes D 20 , D 21 , the anode of one of the diodes D 20 , D 21 being connected to supply potential V.
  • This second current mirror M 5 , M 6 is coupled to the first current mirror M 3 , M 4 , the drain terminal of the transistor M 5 being connected to the drain terminal of the transistor M 4 .
  • the drain terminal of the further transistor M 6 of the second current mirror M 5 , M 6 is coupled to the second connecting terminal K 2 .
  • the second reference current 120 supplied by the second reference current source Iq 4 brings about, via the current mirror M 3 , M 4 , a current 14 through the second transistor M 4 of the first current mirror and the first transistor M 5 of the second current mirror.
  • a current I 5 flows in the second current direction detected, which current, by way of the current mirror ratio of the second current mirror, is related to the current I 4 and thus to the second reference current I 20 , to the second connecting terminal K 2 .
  • a current I 5 flows oppositely to the second direction depicted from the second connecting terminal K 2 via a backward diode D 6 of the second current mirror transistor M 6 of the second current mirror, via the first current mirror transistor M 50 of the said second current mirror and the current mirror transistor M 40 to reference-earth potential GND.
  • a state signal ST with a first state is provided if a disturbance-free operation of the semiconductor switch T is present, to be precise independently of whether the semiconductor switch is used as a high-side switch, as a low-side switch or as a floating switch.
  • the state signal ST has a second state, which indicates a load chopping, to be precise, independently of whether the semiconductor switch T is used as a high-side switch, as a low-side switch or as a floating switch.
  • the state signal ST has a third state, which indicates a connection of one of the two load terminals or both load terminals to the “incorrect” supply potential, to be precise, independently of whether the semiconductor switch is used as a high-side switch, as a low-side switch or as a floating switch.
  • FIG. 7 illustrates an exemplary embodiment of the circuit arrangement according to the invention with the first current source arrangement 10 , the second current source arrangement 20 and the evaluation circuit 30 , which exemplary embodiment can be realized with a comparatively low circuitry outlay.
  • a semiconductor switch T to be monitored designed as a MOSFET, is represented by broken lines in FIG. 7 .
  • the first current source arrangement 10 comprises a reference current source Iq 1 connected between the first supply potential V and a current mirror having two n-channel transistors M 1 , M 2 .
  • the reference current source Iq 1 supplies a first reference current I 1 .
  • the current mirror transistor M 1 connected downstream of the current source Iq 1 is connected up as a diode.
  • the source terminals of the two transistors M 1 , M 2 are connected to one another and the drain terminal of the second current mirror transistor M 2 is connected to the first connecting terminal K 1 .
  • the circuit having the first reference current source Iq 1 and the first and second current mirror transistors M 1 , M 2 corresponds to the circuit having the reference current source Iq 1 and the current mirror transistor M 1 , M 2 in FIG. 5 .
  • a current I 3 is available, which serves as a reference current for the second current source arrangement 20 , the construction of which corresponds, moreover, to the construction of the current source arrangement in accordance with FIG. 6 , with the difference that the source terminals of the current mirror transistors M 5 , M 6 are connected to the first supply potential V via a transistor M 7 of a further current mirror that is yet to be explained.
  • the current mirror transistor M 3 serves as a load for the current mirror M 1 , M 2 instead of the diode chain D 10 , D 11 in accordance with FIG. 5 .
  • the first current mirror M 3 , M 4 of the second current source arrangement 20 has a current mirror ratio of 2:1, which will be explained below.
  • a current I 6 flowing into the second current mirror M 5 , M 6 of the second current source arrangement 20 is evaluated.
  • the said current I 6 is compared with a reference current Iref 2 , provided by a reference current source Iq 2 , and with a reference current Iref 3 , provided by a further reference current source Iq 3 , in order to provide, depending on this comparison result, a first and second two-valued output signal S 8 , S 9 , which jointly represent the state signal ST.
  • the evaluation circuit 30 comprises a current mirror in which the current I 6 is mapped onto a current I 8 by means of current mirror transistors M 7 , M 8 , the current mirror transistor M 8 being connected in series with the reference current source Iq 2 between the first supply potential V and the second supply potential GND.
  • the first signal S 8 can be tapped off at a node common to the current mirror transistor M 8 and the reference current source Iq 2 .
  • the current mirror ratio of the current mirror ratio formed by the transistors M 7 , M 8 is preferably 1:1, so that the current I 8 corresponds to the current I 6 .
  • the first output signal S 8 assumes a high level if the said current I 6 is greater than the reference current Iref 2 .
  • the current I 6 is correspondingly compared with the reference current Iref 3 .
  • a current mirror transistor M 9 coupled to the current mirror transistor M 7 is provided, and is coupled in series with the further reference voltage source Iq 3 between the first supply potential V and the second supply potential GND.
  • the second signal S 9 can be tapped off at the node common to the current mirror transistor M 9 and the reference current source Iq 3 , this signal assuming a high level if the current I 6 is greater than the reference current Iref 3 , and assuming a low level if the current I 6 is less than the reference current Iref 3 .
  • FIG. 8 showing the circuit arrangement in connection with a semiconductor switch T used as a low-side switch
  • FIG. 9 showing the circuit arrangement in connection with a semiconductor switch T used as a high-side switch
  • FIG. 10 showing the circuit arrangement in connection with a semiconductor switch arranged in floating fashion.
  • a normal operation of the semiconductor switch T is present when the drain terminal D, that is, the first connecting terminal K 1 of the diagnosis circuit, is connected to the first supply potential V directly (in high-side operation) or via a load (in low-side operation or floating operation), and when the source terminal S is connected to the second supply potential GND directly (in low-side operation) or via a load (in high-side operation or floating operation).
  • a current I 2 then flows from the first connecting terminal K 1 in the first direction depicted in the figures via the current mirror transistors M 2 , M 3 to reference-earth potential GND.
  • the magnitude of this current I 2 corresponds to the first reference current I 1 .
  • the second reference current Iref 2 is chosen such that it is less than twice the first reference current I 1 , so that the following holds true: Iref 2 ⁇ 2 ⁇ I 1 .
  • the further reference current Iref 3 is less than the second reference current, that is to say Iref 3 ⁇ Iref 2 . It then holds true in normal operation that the current I 6 is greater than the second and third reference current Iref 2 , Iref 3 , so that the first and second output signals S 8 , S 9 are at a high level.
  • FIG. 11 illustrates the value of the current I 6 and also the levels of the signal S 8 , S 9 of the diagnostic circuit for various operating states of the semiconductor switch T.
  • “1” designates a fault case in which the line connection between the load Z and the drain terminal of the MOSFET is interrupted.
  • the current I 2 is equal to zero
  • the second reference current Iref 2 is greater than the first reference current I 1 , so that the output signal S 8 assumes a low level in the event of this fault case of a chopped load.
  • the third reference current Iref 3 which is less than the second reference current Iref 2 , is less than the said first reference current I 1 , so that the second output signal S 9 assumes a high level.
  • a corresponding situation with a current I 6 corresponding to the first reference current I 1 results in the event of the fault case designated by “11” in FIG. 10 , in which there is an interruption of the connection between the first load Z 1 and the drain terminal D.
  • “2” designates one of the other faults, in the case of which the drain terminal of the MOSFET T is coupled to reference-earth potential GND instead of the first supply potential V.
  • the first reference current I 1 flows via the current mirror transistor M 1 and the integrated backward diode D 2 of the current mirror transistor M 2 to the first connecting terminal K 1 .
  • the magnitude of the second current I 2 corresponds to the first reference current I 1 .
  • the current I 2 flows counter to the first current direction depicted in FIG. 8 to the first connecting terminal K 1 .
  • the summation current I 3 and thus the current I 4 through the first current mirror of the second current source arrangement 20 is thus zero.
  • This fault also corresponds to the fault case designated by “21” in FIG. 10 , in the case of which, with a floating semiconductor switch T, the drain terminal is coupled to the second supply potential GND.
  • “3” designates a fault case in which, in high-side operation of the semiconductor switch T, the connection between the source terminal S and the load Z is interrupted, while no fault is present at the drain terminal of the semiconductor switch T.
  • the output signal S 8 assumes a low level, while the second output signal S 9 assumes a high level.
  • the first output signal S 8 assumes a low level and the second output signal S 9 assumes a high level if, in the event of the fault case designated by “12” in FIG. 10 , a load interruption occurs between the source terminal S and the second load Z 2 .
  • the first output signal S 8 assumes a low level and the second output signal S 9 assumes a high level, provided that the above conditions for the second reference current Iref 2 and the third reference current Iref 3 are met.
  • This output signal constellation results for each of the possible load interruptions, namely load interruption in low-side operation ( FIG. 8 ), in high-side operation ( FIG. 9 ) and in floating operation both in the event of interruption of only one load and in the event of interruption of both loads.
  • “4” designates a fault case in which, in high-side operation, the source terminal of the MOSFET is coupled to the first supply potential V instead of the second supply potential GND.
  • This current I 4 through the first current mirror transistor M 5 of the second current mirror M 5 , M 6 and the second current mirror transistor M 4 of the first current mirror M 3 , M 4 is supplied by the current I 5 which flows via the backward diode D 6 of the current mirror transistor M 6 counter to the second current direction illustrated in FIG. 9 .
  • a corresponding constellation results in the case of the fault designated by “22” in FIG. 10 , in the case of which the source terminal S is coupled to the first supply potential V, assuming that the drain terminal D of the MOSFET T is correctly interconnected.

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DE10335083A DE10335083B3 (de) 2003-07-31 2003-07-31 Schaltungsanordnung und Verfahren zur Lastdiagnose eines Halbleiterschalters
DE10335083.7 2003-07-31

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* Cited by examiner, † Cited by third party
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US6828814B2 (en) * 2000-08-10 2004-12-07 Infineon Technologies Ag Circuit configuration and display element
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US7466150B2 (en) * 2005-09-30 2008-12-16 Infineon Technologies Ag Apparatus and method for generating a power signal from a load current

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US20050083086A1 (en) 2005-04-21

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