US6690754B1 - Method and apparatus for reducing the computational complexity and relaxing the critical path of reduced state sequence estimation (RSSE) techniques - Google Patents

Method and apparatus for reducing the computational complexity and relaxing the critical path of reduced state sequence estimation (RSSE) techniques Download PDF

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US6690754B1
US6690754B1 US09/326,785 US32678599A US6690754B1 US 6690754 B1 US6690754 B1 US 6690754B1 US 32678599 A US32678599 A US 32678599A US 6690754 B1 US6690754 B1 US 6690754B1
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taps
intersymbol interference
sequence estimation
technique
processing
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Erich Franz Haratsch
Harish Viswanathan
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Avago Technologies International Sales Pte Ltd
Nokia of America Corp
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Agere Systems LLC
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Priority to EP00304366A priority patent/EP1058406A3/en
Priority to CA002310178A priority patent/CA2310178C/en
Priority to JP2000166158A priority patent/JP2001036437A/ja
Priority to KR1020000030585A priority patent/KR100913926B1/ko
Priority to TW089110860A priority patent/TW484272B/zh
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03203—Trellis search techniques
    • H04L25/03235—Trellis search techniques with state-reduction using feedback filtering
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03184—Details concerning the metric
    • H04L25/03197—Details concerning the metric methods of calculation involving metrics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03248—Arrangements for operating in conjunction with other apparatus
    • H04L25/03299—Arrangements for operating in conjunction with other apparatus with noise-whitening circuitry

Definitions

  • the present invention relates generally to channel equalization and decoding techniques, and more particularly, to sequence estimation techniques with reduced complexity.
  • the transmission rates for local area networks (LANs) that use twisted pair conductors have progressively increased from 10 Megabits-per-second (Mbps) to 1 Gigabit-per-second (Gbps).
  • the Gigabit Ethernet 1000 Base-T standard operates at a clock rate of 125 MHz and uses four copper pairs to transmit 1 Gbps.
  • Trellis-coded modulation (TCM) is employed by the transmitter, in a known manner, to achieve asymptotic coding gains.
  • the signals arriving at the receiver are typically corrupted by intersymbol interference (ISI), crosstalk, echo, and noise.
  • ISI intersymbol interference
  • a major challenge for receivers in such a channel environment is to jointly equalize the channel and decode the corrupted trellis-coded signals at such high clock rates.
  • ISI intersymbol interference
  • Another issue is to meet the speed requirements, as the algorithms for joint equalization and decoding incorporate non-linear feedback loops which cannot be pipelined.
  • a maximum likelihood sequence estimator considers all possible sequences and determines which sequence was actually transmitted, in a known manner.
  • the maximum likelihood sequence estimator is the optimum decoder and applies the well-known Viterbi algorithm to the combined code and channel trellis.
  • the computation and storage requirements of the Viterbi algorithm are proportional to the number of states.
  • the number of states of the combined trellis is given by S ⁇ 2 mL , where S is the number of code states, m is the number of bits for each information symbol, and L is the length of the channel memory.
  • S the number of code states
  • m the number of bits for each information symbol
  • L the length of the channel memory.
  • reduced state sequence estimation techniques reduce the complexity of the maximum likelihood sequence estimators by merging multiple states of the full combined channel/code trellis.
  • RSSE techniques reduce the number of states for Viterbi decoding, the required computations are still too complex at the high clock rates associated with the Gigabit Ethernet standard, as the high processing speeds require a parallel implementation without resource sharing.
  • the RSSE technique incorporates non-linear feedback loops which cannot be pipelined. The critical path associated with these feedback loops is the limiting factor for high-speed implementations.
  • L memory length
  • f k the coefficient for channel tap k.
  • the signal energy of a pulse that has gone through a minimum-phase channel is concentrated in the initial taps.
  • taps one through U are referred to as the initial taps
  • taps U+1 through L are referred to as the tail taps, where U is a prescribed number.
  • the tap number, U is selected to ensure that the initial taps contribute a predefined percentage of the overall signal energy.
  • the less significant tail taps (U+1 through L) are processed with a lower complexity cancellation algorithm, such as a decision-feedback equalizer technique, that cancels the tail taps using tentative decisions.
  • a decision-feedback equalizer technique that cancels the tail taps using tentative decisions.
  • only the more significant initial taps (1 through U) are processed with a reduced state sequence estimation technique.
  • the DFE technique initially removes the intersymbol interference associated with the tail taps, then the RSSE technique is applied only to the more important tail taps.
  • taps one through U are processed using the RSSE technique, while taps U+1 through L are processed with a lower complexity decision-feedback equalizer.
  • the present invention does not further reduce the number of states which are processed in the RSSE circuit, thus ensuring a good bit error rate versus signal-to-noise ratio performance for a well-chosen value of U. Meanwhile, the computational complexity and processing time of the decision-feedback computations in the RSSE circuit are substantially reduced. The hardware complexity of the survivor memory unit (SMU) in the RSSE circuit can also be reduced.
  • SMU survivor memory unit
  • a receiver includes a tentativnre decision/tail processing circuit for processing the less significant tail taps and an RSSE circuit for processing the initial taps.
  • the tentative decision/tail processing circuit processes the less significant tail taps with a lower complexity DFE algorithm, to cancel the tail taps using tentative decisions.
  • the RSSE circuit processes only the initial taps with the RSSE technique.
  • FIG. 1 is a schematic block diagram of a conventional receiver
  • FIG. 2 is a schematic block diagram of a receiver in accordance with the present invention.
  • FIG. 3 illustrates the signal energy of a pulse that has undergone dispersion through a minimum-phase channel
  • FIG. 4 illustrates an implementation of the tentative decision/tail processing circuitry of FIG. 2.
  • FIG. 5 illustrates an implementation of the reduced state sequence estimation circuitry of FIG. 2 .
  • FIG. 1 shows the block diagram for a conventional receiver 100 in a channel environment associated with, for example, the Gigabit Ethernet 1000 Base-T standard.
  • a major challenge for such receivers 100 is to jointly equalize the channel and decode the corrupted trellis-coded signals at the high clock rates of the Gigabit Ethernet 1000 Base-T standard.
  • the receiver 100 includes an analog-to-digital (A/D) converter 100 for converting the received analog signal to a digital signal.
  • A/D analog-to-digital
  • the digitized data is then processed by a feed forward equalizer (FFE) 120 , an echo canceller 130 and a crosstalk canceller 140 .
  • the feed forward equalizer 120 makes the channel impulse response causal and minimum-phase, and additionally whitens the noise.
  • the echo canceller 130 removes echo from the received signal and the crosstalk canceller 140 removes the crosstalk, in a known manner.
  • the equalizer/decoder 150 performs data detection, for example, using maximum likelihood sequence estimation, to produce the output symbols or bits.
  • FIG. 2 illustrates a receiver 200 in accordance with the present invention that reduces the hardware complexity of reduced state sequence estimation algorithms for a given number of states, while also relaxing the critical path problem.
  • L the channel impulse response
  • f k the coefficient for channel tap k.
  • the signal energy of a pulse that has undergone channel dispersion is concentrated in the initial taps. As shown in FIG. 3, the initial taps provide the largest contribution to the signal energy of the channel output, and the corresponding power decreases to zero as the taps approach infinity.
  • taps one through U are referred to as the initial taps, and taps U+1 through L are referred to as the tail taps, where U is a prescribed number.
  • the tap number, U can be established using simulations or experimental results to ensure that the initial taps contribute a predefined percentage of the overall signal energy.
  • the less significant tail taps are processed with a lower complexity cancellation algorithm, such as a decision-feedback equalizer technique, that cancels the tail taps using tentative decisions.
  • a decision-feedback equalizer technique that cancels the tail taps using tentative decisions.
  • only the initial taps are processed with a reduced state sequence estimation technique.
  • the DFE technique initially removes the intersymbol interference associated with the tail taps, then the RSSE technique is applied only to the more important tail taps.
  • taps one through U are processed using the RSSE technique and taps U+1 through L are processed with a lower complexity decision-feedback equalizer.
  • FIG. 2 is a schematic block diagram of a receiver 200 in accordance with the present invention.
  • the receiver 200 includes a slicer 210 that slices the digital data into symbol values.
  • the receiver 200 includes tentative decision/tail processing circuitry 400 , discussed further below in conjunction with FIG. 4, for processing the less significant tail taps with a lower complexity cancellation algorithm, such as a decision-feedback equalizer technique, to cancel the tail taps using tentative decisions.
  • the receiver 200 also includes RSSE circuitry 500 , discussed further below in conjunction with FIG. 5, for processing only the initial taps with a reduced state sequence estimation technique (FIG. 5 ).
  • FIG. 4 illustrates a decision-feedback equalizer implementation of the tentative decision/tail processing circuitry 400 of FIG. 2 .
  • the critical path inside the RSSE circuit consisting of the decision-feedback cell, branch metric cell (BMC), add-compare-select cell (ACSC) and survivor memory cell (SMC), as shown in FIG. 5, is the bottleneck for high speed implementations of the RSSE technique.
  • the tentative decision/tail processing circuitry 400 is not part of the critical path.
  • the present invention reduces the computational complexity of the decision-feedback unit L/U times.
  • computational delay through the decision feedback cell (FIG. 5) is reduced L/U times so that the critical path problem is relaxed significantly as well.
  • the present invention also allows for a survivor depth D of the survivor memory unit, which is smaller than L.
  • the survivor depth D must be at least L, as the L past survivor symbols are needed for the computations in the decision feedback unit.
  • the present invention also allows for a hardware reduction of the survivor memory unit (FIG. 5 ).
  • DFSE decision-feedback sequence estimation
  • U the decision feedback unit and thus the feedback loop is removed and the decision-feedback sequence estimation becomes a pure Viterbi decoder.
  • the present invention permits pipelining in all processing blocks outside the add-compare-select unit (ACSU), and the critical path reduces to one add-compare-select cell.
  • the tentative decision/tail processing circuitry 400 has been implemented in FIG. 4 using a decision-feedback equalizer, the tentative decision/tail processing circuitry 400 could likewise be implemented using a soft DFE approach.
  • soft DFE techniques see, for example, S. L. Ariyavisitakul and Y. Li, “Joint Coding and Decision Feedback Equalization for Broadband Wireless Channels”, IEEE Journal on selected Areas in Communications, vol. 16, no. 9, December 1998, incorporated by reference herein.
  • FIG. 5 illustrates the reduced state sequence estimation circuit of FIG. 2 which processes only the initial taps of the channel impulse response.
  • reduced state sequence estimation techniques reduce the complexity of the maximum likelihood sequence estimators by merging multiple states of the full combined channel/code trellis.
  • P. R. Chevillat and E. Eleftheriou “Decoding of Trellis-Encoded Signals in the Presence of Intersymbol Interference and Noise”, IEEE Trans. Commun., vol. 37, 669-76, (July 1989) and M. V. Eyuboglu and S. U. H. Qureshi, “Reduced-State Sequence Estimation For Coded Modulation On Intersymbol Interference Channels”, IEEE JSAC, vol. 7, 989-95 (August 1989), each incorporated by reference above.
  • Reduced state sequence estimation considers only partial information about the information symbol for the reduced combined trellis.
  • FIG. 5 shows a block diagram for reduced state sequence estimation which is also valid for its specializations, decision-feedback sequence estimation and PDFE.
  • BMU branch metric unit
  • Each decision-feedback cell takes L past symbols from the corresponding survivor memory cell.
  • Decision-feedback sequence estimation is a specialization of reduced state sequence estimation and employs a trellis that takes into account only the first K of the L channel coefficients ⁇ f k ⁇ , 0 ⁇ K ⁇ L.
  • Intersymbol interference terms not represented in the combined state are estimated and subtracted in the metric computation using the path history of each state.
  • the RSSE circuit 500 may be replaced by an M-algorithm (MA).
  • M-algorithm M-algorithm
  • the M-algorithm techniques work on the complete combined trellis, but retain at each processing step only M paths with the best metrics.
  • M-algorithms see, for example, N. Seshadri and J. B. Anderson, “Decoding of Severely Filtered Modulation Codes Using the (M,L) Algorithm”, IEEE JSAC, vol. 7, 1006-1016 (March 1989), incorporated by reference herein.
  • the M-algorithm uses M DFEs to cancel the intersymbol interference for the M best paths.
  • the M-algorithm is not as inherently parallel as the reduced state sequence estimation implementation shown in FIG. 5 or the Viterbi algorithm itself, as the testing and sorting operation in the add-test-sort unit (ATSoU) is performed over all bM path extensions.
  • Each decision-feedback cell takes L past symbols from the corresponding survivor memory cell.
  • the M-algorithm would process the combined trellis that results from the concatenation of the TCM code and a channel with the first U taps of the channel impulse response.
  • the tail of the channel impulse response would be processed with a lower complexity cancellation algorithm as discussed above.

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  • Engineering & Computer Science (AREA)
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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
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US09/326,785 1999-06-04 1999-06-04 Method and apparatus for reducing the computational complexity and relaxing the critical path of reduced state sequence estimation (RSSE) techniques Expired - Lifetime US6690754B1 (en)

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US09/326,785 US6690754B1 (en) 1999-06-04 1999-06-04 Method and apparatus for reducing the computational complexity and relaxing the critical path of reduced state sequence estimation (RSSE) techniques
EP00304366A EP1058406A3 (en) 1999-06-04 2000-05-23 Method and apparatus for reducing the computational complexity and relaxing the critical path of reduced state sequence estimation (RSSE) techniques
CA002310178A CA2310178C (en) 1999-06-04 2000-05-29 Method and apparatus for reducing the computational complexity and relaxing the critical path of reduced state sequence estimation (rsse) techniques
JP2000166158A JP2001036437A (ja) 1999-06-04 2000-06-02 分散チャネルから受信された信号を処理するための方法および分散チャネルからの信号を受信する受信機
KR1020000030585A KR100913926B1 (ko) 1999-06-04 2000-06-03 계산 복잡도를 감소시키고 감소된 상태 시퀀스 추정 기술의 임계 경로를 릴랙싱하는 방법 및 장치
TW089110860A TW484272B (en) 1999-06-04 2000-06-27 Method and apparatus for reducing the computational complexity and relaxing the critical path of reduced state sequence estimation (RSSE) techniques

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