US6667223B2 - High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern - Google Patents

High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern Download PDF

Info

Publication number
US6667223B2
US6667223B2 US09/905,357 US90535701A US6667223B2 US 6667223 B2 US6667223 B2 US 6667223B2 US 90535701 A US90535701 A US 90535701A US 6667223 B2 US6667223 B2 US 6667223B2
Authority
US
United States
Prior art keywords
trenches
insulating material
resist
depositing
over
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US09/905,357
Other languages
English (en)
Other versions
US20030013270A1 (en
Inventor
Mihel Seitz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Polaris Innovations Ltd
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Assigned to INFINEON TECHNOLOGIES NORTH AMERICA CORP. reassignment INFINEON TECHNOLOGIES NORTH AMERICA CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SEITZ, MIHEL
Priority to US09/905,357 priority Critical patent/US6667223B2/en
Priority to DE10228717A priority patent/DE10228717B4/de
Publication of US20030013270A1 publication Critical patent/US20030013270A1/en
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
Publication of US6667223B2 publication Critical patent/US6667223B2/en
Application granted granted Critical
Assigned to QIMONDA AG reassignment QIMONDA AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INFINEON TECHNOLOGIES AG
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: QIMONDA AG
Assigned to POLARIS INNOVATIONS LIMITED reassignment POLARIS INNOVATIONS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INFINEON TECHNOLOGIES AG
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Definitions

  • the present invention relates generally to the fabrication of integrated circuits (IC's), and more particularly to the fabrication of memory IC's.
  • DRAM dynamic random access memory
  • a DRAM typically includes a large number of individual DRAM cells arranged in an array, with each cell storing one bit of data.
  • a DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor.
  • FET access field effect transistor
  • the access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations.
  • the data charges on the storage capacitor are periodically refreshed during a refresh operation.
  • FIG. 1 illustrates a cross-sectional view of a prior art DRAM 10 having closely nested features 2 and isolated features 4 having no minimum feature size and having no minimum distance apart. Often these two areas 2 / 4 are referred to as lines and spaces (L/S).
  • the nested features 2 may comprise an array of densely-packed DRAM cells on minimum pitch, for example.
  • Nested features 2 typically include lines and spaces that both comprise a minimum feature size, for example.
  • Isolated features 4 also have the minimum pitch or feature size but are surrounded by a comparatively large space 6 . Isolated features 4 are typically found in the peripheral circuitry of a DRAM layout, for example.
  • a substrate 12 is patterned with isolation trenches (IT's) 15 .
  • the depth requirement of the isolation trenches is a function of the individual circuitry and depends on the requirement of providing sufficient electrical insulation either between devices or n- or p-doped wells for improved latch-up immunity, for example.
  • the electrical insulation provided by the isolation trenches is often referred to as shallow trench isolation (STI).
  • STI regions typically function to separate the element regions of the DRAM array and define the outline of the vertical array device with a bitline contact, for example.
  • the element regions may include active areas, storage capacitors and other electronic devices such as transistors.
  • the isolation trenches 15 also prevent cross-talk between two neighboring DRAM cells connected via the same wordline, for example. Preventing cross-talk in this manner ensures that only one cell is modified when being written to by accessing one row and a corresponding column in the DRAM array, for example.
  • a typical prior art process flow for achieving a high aspect ratio gapfill will next be described.
  • a pad nitride 14 is deposited over the substrate 12 prior to the isolation trench 15 formation.
  • the trenches 15 are filled with an insulator 16 , which insulator 16 may comprise high-density plasma (HDP) oxide deposited by chemical vapor deposition (CVD), which has become a common material and isolation technique used in semiconductor device manufacturing.
  • HDP oxide 16 typically forms peaks 22 (also referred to as huts or miters) over features.
  • the HDP oxide huts 22 may cause a void 18 to form between high-aspect ratio features.
  • the HDP oxide huts 22 ‘pinch’ off the flow of HDP oxide 16 into the trenches 15 , thereby leading to incomplete gapfills. Incomplete gapfills become a problem in subsequent processing, for example, when a conductive layer is deposited on the wafer.
  • a problem in prior art isolation techniques is the formation of these voids 18 in high-aspect ratio trenches. As the minimum feature size is made smaller, the oxide gap fill of isolation trenches 15 becomes more challenging, especially in devices having vertical long channel transistors, for example. Leaving voids 18 in a finished semiconductor device results in device failures. Voids 18 may inadvertently be filled with conductive material in subsequent processing steps, for example.
  • Preventing the formation of voids 18 when an HDP oxide 16 insulator is used requires additional deposition steps: e.g., one or more additional HDP oxide deposition processes steps may be required in order to completely fill the trenches 15 to the top surface of the pad nitride 14 .
  • the HDP oxide 16 may be etched back to the top of the pad nitride 14 , and at least one additional layer of HDP oxide (not shown) may be deposited and etched back until the trenches 15 are filled.
  • Conductive material left in voids exposed after CMP processing steps may enter the trenches 15 and short elements in the substrate 12 .
  • isolation trenches 15 of a DRAM cell that minimizes the number of insulating layers 16 required to be deposited and prevents possible shorting of elements in the substrate 12 .
  • the present invention provides a method of filling isolation trenches of a semiconductor device.
  • a method of isolating active areas of a semiconductor memory device the memory device including a plurality of trenches separating a plurality of element regions, the method comprising depositing a first insulating material over the trenches, the first insulating material comprising a first top portion and a second top portion.
  • a resist is formed over the first insulating material over at least the trenches, leaving the first top portion of the first insulating material exposed. At least the second top portion of the first insulating material is removed.
  • a method of manufacturing a memory device comprising providing a semiconductor wafer having a substrate, forming isolation trenches between substrate element regions, and depositing a first insulating material over the trenches, the first insulating material including a first top portion and a second top portion, the second top portion being larger than the first top portion.
  • a resist is formed over portions of the trenches, leaving the first insulating material first top portion exposed, and at least the second top portion of the first insulating material is removed.
  • a method of isolating element regions of a semiconductor wafer comprising forming trenches between element regions, forming a first HDP oxide layer over the trenches, the first HDP oxide layer including huts, forming a resist over at least the trenches leaving a top portion of the first HDP oxide layer huts exposed, removing at least the first HDP oxide layer huts, and removing the resist.
  • Advantages of embodiments of the invention include providing a process flow in which the removal of insulating material within isolation trenches is self-aligned, and does not require an additional mask.
  • the number of insulating material deposition steps is reduced in accordance with an embodiment of the present invention.
  • a pad nitride layer and liner may serve as an etch stop during removal of the top portion of the first insulating material deposited, and an optional nitride liner provides increased processing parameters.
  • FIG. 1 illustrates a cross-sectional view of a prior art DRAM device
  • FIGS. 2 through 6 show cross-sectional views of an embodiment of the present invention in various stages of manufacturing
  • FIGS. 7 and 8 illustrate cross-sectional views of another embodiment of the present invention including a nitride liner.
  • FIGS. 2 through 6 show cross-sectional views of a DRAM device in accordance with a preferred embodiment of the present invention at various stages of manufacturing.
  • a wafer 100 having a substrate 112 is provided.
  • the substrate typically comprises single-crystal silicon, although alternatively, compound semiconductors such as GaAs, InP, Si/Ge, and SiC may be used in place of silicon as a substrate material, as examples.
  • the substrate 112 may include oxide layers, conductive layers or other semiconductor elements, e.g., transistors or diodes, for example.
  • a pad nitride 114 is deposited over the substrate 112 .
  • Pad nitride 114 preferably comprises SiN, as an example.
  • the pad nitride 114 layer is preferably between around 100 to 200 nm, for example.
  • Trenches 115 are formed within pad nitride 114 and substrate 112 .
  • Trenches 115 provide isolation between element regions, which may include active areas and storage capacitors within the substrate 112 , as examples.
  • the wafer 100 may comprise nested features 102 and isolated features 104 .
  • the nested features 102 may include a DRAM array, for example. Each memory cell within the DRAM array 102 must be isolated from adjacent memory cells, which isolation is provided by the trenches 115 formed.
  • Insulating material 116 is deposited within the trenches 115 and over the pad nitride 114 , as shown.
  • Insulating material 116 preferably has anisotropic fill characteristics, and preferably comprises silicon oxide deposited by HDP-CVD, as an example.
  • Insulating material 116 is also referred to herein as HDP oxide.
  • HDP oxide is preferably used for insulating material 116 because HDP oxide is typically more effective in filling the high-aspect ratio trenches 115 between active areas than other insulating material depositions, particularly in applications where high thermal budgets are applied in subsequent processing.
  • Depositing HDP oxide 116 over the wafer 100 results in the phenomenon of huts 122 that are formed over features such as the memory cells being isolated.
  • the huts 122 appear as peaks or oxide that forms points over underlying features, as shown.
  • the huts 122 may also be described as Bishop's miters (referring to the shape of a Bishop's hat).
  • an amount of HDP oxide 116 is selected so that the HDP huts 122 have a spacing between one another of 20-30 nm. Such a spacing preferably results in 1 ⁇ 2 to 3 ⁇ 4 of the trench 115 depth being filled, with the depth being the total depth of the trench 115 within the substrate 112 .
  • the HDP oxide 116 is preferably between around 200 to 500 nm thick.
  • a resist 120 is deposited over the HDP oxide 116 .
  • the resist 120 may comprise a commercial mid-ultraviolate (MUV) positive contrast, e.g., TOK 3250, and may alternatively comprise other photoresists, as examples.
  • the resist 120 is between around 300-600 nm thick, for example.
  • a top portion of the resist 120 is removed to expose a top portion of insulating layer 116 , as shown in FIG. 3 . Because of the phenomena of hut 122 formation found with HDP oxide, the tip of the huts 122 are now exposed through the resist 120 , as shown.
  • the resist 120 portions are removed by exposure to MUV light, for example, for a predetermined period of time, e.g., between 5-30 seconds.
  • the resist 120 remains only between the features, e.g., over trenches 115 , as shown in FIG. 3 .
  • the resist 120 is preferably removed elsewhere over the wafer, in order to obtain the most efficient gapfill process.
  • a resist 120 pattern residing only over trenches 115 is achieved in a preferred embodiment of the present invention by taking advantage of the topography of the wafer surface and the small dimensions of the technology.
  • An appropriate resist 120 may be selected that has a shallow light absorption coefficient, leading to an incomplete resist development, leaving resist in the troughs over trenches 115 behind.
  • a resist 120 pattern residing only over trenches 115 as shown in FIG. 3 is achieved using a flood exposure e.g., using no mask, of a wafer coated with resist. Due to the small spacing between the lines (e.g. trench 115 width), the pad nitride 114 material, which comprises an optically dense medium in a preferred embodiment, and a comparatively large wavelength selected and used for the flood exposure, the resist 120 between the lines over trenches 115 cannot be exposed and therefore remains during the developing process between the lines e.g., over trenches 115 .
  • a top portion of the resist 120 is removed by exposure of the entire wafer 100 to light, for example, with a much longer optical wavelength than the spacing between the wafer features, for example, the distance between the trenches 115 .
  • the resist 120 between the huts 122 is not developed because of resolution.
  • the lines and spaces function as a grid for the light if the distance within the grid is much smaller than the used wavelength.
  • the resist 120 is partially exposed, which may be achieved by determining an optimized absorption constant of the photoresist 120 .
  • the tops 122 of the miter-shaped HDP oxide 116 remain exposed.
  • the miter tips 122 of the HDP oxide 116 may be removed in a subsequent etch step with the resist 120 in place, in accordance with an embodiment of the present invention, as shown in FIG. 4 .
  • a top portion of the HDP oxide 116 is preferably selectively removed from the wafer surface.
  • the pad nitride 114 may be used as a stopping layer during the removal of the HDP oxide 116 top portion, for example. When used as an etch stop, the pad nitride 114 provides some process margin for the selective HDP oxide 116 etch.
  • the pad nitride 114 thickness determines how much process control is needed for the insulating material 116 etch, for example.
  • the wafer 100 may be exposed to a timed etch process to remove a top portion of the insulating material 116 from beneath the resist 120 .
  • the insulating material 116 timed etch is preferably isotropic.
  • the insulating material 116 etch may comprise, as an example, a hydrofluoric (HF) acid-based wet etch, or alternatively, the insulating material 116 may be removed by reactive ion etching (RIE) or other dry etch.
  • RIE reactive ion etching
  • the insulating material 116 etch stops before reaching the silicon sidewalls 112 , and more preferably, the insulating material 116 etch stops before any insulating material 116 is removed from within the trenches 115 . Also, the insulating material 116 etchant must not come in contact with a gate oxide of elements within active regions of the substrate 112 .
  • the resist 120 is then removed.
  • the resist 120 may be removed by exposure to light, for example.
  • a second layer of insulating material 126 is deposited over the wafer after the resist removal to completely fill the trenches 115 , illustrated in FIG. 5 . Because the aspect ratio of the portion of the trench 115 that remains to be filled is lower than the original aspect ratio of the trench 115 , the remainder of the isolation trenches 115 may be completely filled in the second insulating material deposition step, in accordance with an embodiment of the present invention.
  • the wafer 100 may then be polished, e.g., by CMP, to remove the insulating material 126 from the top of the pad nitride 114 , as shown in FIG. 6 . Subsequent processing of the wafer 100 is then performed, such as removal of the pad nitride 114 and other processing steps.
  • a single etch step may be used that is selective to nitride, that etches resist 120 and oxide 116 at the same etch rate.
  • the etch may comprise a timed RIE etch, for example, comprising 20 sec.
  • FIGS. 7 and 8 illustrate another preferred embodiment of the present invention.
  • An optional nitride liner 228 is deposited over the pad nitride 214 and isolation trenches 215 prior to the deposition of the first insulating material 216 , shown in FIG. 7 .
  • nitride liner 228 comprises SiN, for example.
  • Nitride liner 228 is preferably several nanometers thick, e.g., approximately 6 nanometers thick.
  • a resist (not shown) is deposited preferably over only trenches 215 , and a top portion of the first insulating material 216 is removed from beneath the resist 120 , as previously described for FIGS. 2 through 6.
  • a second insulating material 226 is deposited after the removal of the resist, and the wafer 200 is planarized, e.g., by CMP to remove portions of the second insulating material 226 from the top of the nitride liner 228 , as shown in FIG. 8 .
  • embodiments of the present invention are described herein with reference to a DRAM, they also have useful application in ferroelectric random access memories (FRAM's) and other semiconductor devices.
  • FRAM's ferroelectric random access memories
  • embodiments of the present method may be used for isolating element regions of a semiconductor memory device or for p- and n-well separation in logic devices, as examples.
  • the present invention provides several advantages over prior art trench isolation methods for semiconductors. Advantages of the invention include providing a self-aligned process of filling isolation trenches that does not require the use of an additional mask.
  • the process flow accomplishes filling isolation trenches 115 / 215 with insulating material 116 / 126 / 216 / 226 in only two deposition steps, optimizing the number of insulating layers required to be deposited is optimized. Non-uniformity in oxide 116 / 126 / 216 / 226 thickness is minimized, resulting in a robust subsequent CMP process.
  • nitride liner 228 provides increased processing parameters.
  • the pad nitride 114 / 214 and nitride liner 228 around trenches 115 / 215 may serve as an etch stop during removal of the top portion 122 / 222 of first insulating material 116 / 216 deposited.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
US09/905,357 2001-07-13 2001-07-13 High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern Expired - Lifetime US6667223B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09/905,357 US6667223B2 (en) 2001-07-13 2001-07-13 High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern
DE10228717A DE10228717B4 (de) 2001-07-13 2002-06-27 Verfahren zum Isolieren aktiver Bereiche von Halbleiterspeicherelementen und zum Isolieren von Elementgebieten eines Halbleiterwafers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/905,357 US6667223B2 (en) 2001-07-13 2001-07-13 High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern

Publications (2)

Publication Number Publication Date
US20030013270A1 US20030013270A1 (en) 2003-01-16
US6667223B2 true US6667223B2 (en) 2003-12-23

Family

ID=25420686

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/905,357 Expired - Lifetime US6667223B2 (en) 2001-07-13 2001-07-13 High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern

Country Status (2)

Country Link
US (1) US6667223B2 (de)
DE (1) DE10228717B4 (de)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040126986A1 (en) * 2002-12-30 2004-07-01 Michael Wise Improved deep isolation trenches
US6887785B1 (en) 2004-05-13 2005-05-03 International Business Machines Corporation Etching openings of different depths using a single mask layer method and structure
US20080020534A1 (en) * 2006-07-20 2008-01-24 Marcus Culmsee Semiconductor device fabrication methods
US20080132016A1 (en) * 2006-12-04 2008-06-05 Hynix Semiconductor Inc. Method of manufacturing a flash memory device
US20080176379A1 (en) * 2006-10-31 2008-07-24 Hynix Semiconductor Inc. Method for forming isolation structure in semiconductor device
US20090159947A1 (en) * 2007-12-19 2009-06-25 International Business Machines Corporation SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION
US20160247878A1 (en) * 2006-03-14 2016-08-25 Micron Technology, Inc. Isolation Trench Fill Using Oxide Liner and Nitride Etch Back Technique With Dual Trench Depth Capability
DE102015115940A1 (de) * 2015-08-31 2017-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Tiefe Grabenisolationen und Verfahren zu ihrer Herstellung

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100443126B1 (ko) * 2002-08-19 2004-08-04 삼성전자주식회사 트렌치 구조물 및 이의 형성 방법
US7091103B2 (en) * 2002-12-09 2006-08-15 International Business Machines Corporation TEOS assisted oxide CMP process
US6982207B2 (en) * 2003-07-11 2006-01-03 Micron Technology, Inc. Methods for filling high aspect ratio trenches in semiconductor layers
US6914015B2 (en) * 2003-10-31 2005-07-05 International Business Machines Corporation HDP process for high aspect ratio gap filling
US7285433B2 (en) * 2003-11-06 2007-10-23 General Electric Company Integrated devices with optical and electrical isolation and method for making
JP4564272B2 (ja) * 2004-03-23 2010-10-20 株式会社東芝 半導体装置およびその製造方法
US20150200111A1 (en) * 2014-01-13 2015-07-16 Globalfoundries Inc. Planarization scheme for finfet gate height uniformity control
JP7316757B2 (ja) * 2018-02-23 2023-07-28 ローム株式会社 半導体装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5480763A (en) * 1991-01-11 1996-01-02 Victor Company Of Japan, Ltd. Method for manufacturing a stamper for high-density recording discs
US6171962B1 (en) * 1997-12-18 2001-01-09 Advanced Micro Devices, Inc. Shallow trench isolation formation without planarization mask
US6171896B1 (en) * 1997-02-03 2001-01-09 Taiwan Semiconductor Manufacturing Company Method of forming shallow trench isolation by HDPCVD oxide
US6210846B1 (en) * 1999-08-13 2001-04-03 Advanced Micro Devices, Inc. Exposure during rework for enhanced resist removal
US6251783B1 (en) * 1998-09-02 2001-06-26 United Microelectronics Corp. Method of manufacturing shallow trench isolation
US6265302B1 (en) * 1999-07-12 2001-07-24 Chartered Semiconductor Manufacturing Ltd. Partially recessed shallow trench isolation method for fabricating borderless contacts
US20010049179A1 (en) * 2000-01-18 2001-12-06 Katsumi Mori Semiconductor wafer, method for processing the same and method for manufacturing semiconductor device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5851899A (en) * 1996-08-08 1998-12-22 Siemens Aktiengesellschaft Gapfill and planarization process for shallow trench isolation
US5721173A (en) * 1997-02-25 1998-02-24 Kabushiki Kaisha Toshiba Method of forming a shallow trench isolation structure
KR100230815B1 (ko) * 1997-03-18 1999-11-15 김영환 반도체 메모리 소자 격리 방법
JPH11214499A (ja) * 1998-01-27 1999-08-06 Mitsubishi Electric Corp 半導体装置の製造方法
JPH11233609A (ja) * 1998-02-13 1999-08-27 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6057207A (en) * 1998-03-25 2000-05-02 Taiwan Semiconductor Manufacturing Company Shallow trench isolation process using chemical-mechanical polish with self-aligned nitride mask on HDP-oxide
US6004863A (en) * 1998-05-06 1999-12-21 Taiwan Semiconductor Manufacturing Company Non-polishing sacrificial layer etchback planarizing method for forming a planarized aperture fill layer
US6204149B1 (en) * 1999-05-26 2001-03-20 Micron Technology, Inc. Methods of forming polished material and methods of forming isolation regions
TW432600B (en) * 1999-12-16 2001-05-01 United Microelectronics Corp Process for shallow trench isolation structure

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5480763A (en) * 1991-01-11 1996-01-02 Victor Company Of Japan, Ltd. Method for manufacturing a stamper for high-density recording discs
US6171896B1 (en) * 1997-02-03 2001-01-09 Taiwan Semiconductor Manufacturing Company Method of forming shallow trench isolation by HDPCVD oxide
US6171962B1 (en) * 1997-12-18 2001-01-09 Advanced Micro Devices, Inc. Shallow trench isolation formation without planarization mask
US6251783B1 (en) * 1998-09-02 2001-06-26 United Microelectronics Corp. Method of manufacturing shallow trench isolation
US6265302B1 (en) * 1999-07-12 2001-07-24 Chartered Semiconductor Manufacturing Ltd. Partially recessed shallow trench isolation method for fabricating borderless contacts
US6210846B1 (en) * 1999-08-13 2001-04-03 Advanced Micro Devices, Inc. Exposure during rework for enhanced resist removal
US20010049179A1 (en) * 2000-01-18 2001-12-06 Katsumi Mori Semiconductor wafer, method for processing the same and method for manufacturing semiconductor device

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
A. Kersch, et al., Recent Advances in Feature Scale Simulation.
C.J. Radens, et al., An orthogonal 6F<2 >Trench-Sidewall Vertical Device Cell for 4Gb/16Gb DRAM; and.
C.J. Radens, et al., An orthogonal 6F2 Trench-Sidewall Vertical Device Cell for 4Gb/16Gb DRAM; and.
U. Gruening, et al., A Novel Trench DRAM Cell with VERtlcal Access Transistor and BuriEd Strap (VERI BEST) for 4Gb/16Gb.

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6821865B2 (en) 2002-12-30 2004-11-23 Infineon Technologies Ag Deep isolation trenches
US20040126986A1 (en) * 2002-12-30 2004-07-01 Michael Wise Improved deep isolation trenches
US6887785B1 (en) 2004-05-13 2005-05-03 International Business Machines Corporation Etching openings of different depths using a single mask layer method and structure
US9799727B2 (en) * 2006-03-14 2017-10-24 Micron Technology, Inc. Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability
US20160247878A1 (en) * 2006-03-14 2016-08-25 Micron Technology, Inc. Isolation Trench Fill Using Oxide Liner and Nitride Etch Back Technique With Dual Trench Depth Capability
US20080020534A1 (en) * 2006-07-20 2008-01-24 Marcus Culmsee Semiconductor device fabrication methods
US7364975B2 (en) 2006-07-20 2008-04-29 Infineon Technologies Ag Semiconductor device fabrication methods
US7763524B2 (en) * 2006-10-31 2010-07-27 Hynix Semiconductor Inc. Method for forming isolation structure of different widths in semiconductor device
US20080176379A1 (en) * 2006-10-31 2008-07-24 Hynix Semiconductor Inc. Method for forming isolation structure in semiconductor device
US7659159B2 (en) * 2006-12-04 2010-02-09 Hynix Semiconductor Inc. Method of manufacturing a flash memory device
US20080132016A1 (en) * 2006-12-04 2008-06-05 Hynix Semiconductor Inc. Method of manufacturing a flash memory device
US20090159947A1 (en) * 2007-12-19 2009-06-25 International Business Machines Corporation SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION
DE102015115940A1 (de) * 2015-08-31 2017-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Tiefe Grabenisolationen und Verfahren zu ihrer Herstellung
US9754993B2 (en) 2015-08-31 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Deep trench isolations and methods of forming the same
DE102015115940B4 (de) * 2015-08-31 2020-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Verfahren zur Herstellung von Grabenisolationsbereichen und integrierte Schaltkreisstruktur mit Grabenisolationsbereichen
US11217621B2 (en) 2015-08-31 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Deep trench isolations and methods of forming the same
US12087801B2 (en) 2015-08-31 2024-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Deep trench isolations and methods of forming the same

Also Published As

Publication number Publication date
DE10228717A1 (de) 2003-01-30
US20030013270A1 (en) 2003-01-16
DE10228717B4 (de) 2007-11-22

Similar Documents

Publication Publication Date Title
JP4074451B2 (ja) 半導体装置の製造方法
JP3434488B2 (ja) Ｄｒａｍセルの製造方法
KR0135803B1 (ko) 상.하로 분리된 커패시터를 갖는 반도체 메모리장치 및 그 제조방법
US6667223B2 (en) High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern
US7364975B2 (en) Semiconductor device fabrication methods
US20040061165A1 (en) Floating gate memory fabrication methods comprising a field dielectric etch with a horizontal etch component
US7250335B2 (en) Methods of fabricating integrated circuit devices including self-aligned contacts with increased alignment margin
US5681773A (en) Method for forming a DRAM capacitor
US20040126986A1 (en) Improved deep isolation trenches
US10424586B2 (en) Memory device including a trench isolation structure between buried word lines and manufacturing method thereof
KR20070020137A (ko) Ａｌ₂Ｏ₃ 유전체를 이용하는 메모리 셀용 격리 구조체
US8242583B2 (en) Semiconductor device having CMP dummy pattern
US6693041B2 (en) Self-aligned STI for narrow trenches
US5759894A (en) Method for forming a DRAM capacitor using HSG-Si
US6808975B2 (en) Method for forming a self-aligned contact hole in a semiconductor device
US6642135B2 (en) Method for forming semiconductor memory device having a fuse
US6812092B2 (en) Method for fabricating transistors having damascene formed gate contacts and self-aligned borderless bit line contacts
US6551874B2 (en) Self-aligned STI process using nitride hard mask
US6479355B2 (en) Method for forming landing pad
US5804480A (en) method for forming a DRAM capacitor using HSG-Si technique and oxygen implant
US20090321805A1 (en) Insulator material over buried conductive line
US6566227B2 (en) Strap resistance using selective oxidation to cap DT poly before STI etch
US7205208B2 (en) Method of manufacturing a semiconductor device
US6967161B2 (en) Method and resulting structure for fabricating DRAM cell structure using oxide line spacer
US6620677B1 (en) Support liner for isolation trench height control in vertical DRAM processing

Legal Events

Date Code Title Description
AS Assignment

Owner name: INFINEON TECHNOLOGIES NORTH AMERICA CORP., CALIFOR

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SEITZ, MIHEL;REEL/FRAME:012011/0328

Effective date: 20010705

AS Assignment

Owner name: INFINEON TECHNOLOGIES AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES NORTH AMERICA CORP.;REEL/FRAME:013905/0123

Effective date: 20030812

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: QIMONDA AG,GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023768/0001

Effective date: 20060425

Owner name: QIMONDA AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023768/0001

Effective date: 20060425

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: INFINEON TECHNOLOGIES AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:035623/0001

Effective date: 20141009

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: POLARIS INNOVATIONS LIMITED, IRELAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:036808/0284

Effective date: 20150708