US6643792B1 - Integrated circuit device having clock frequency changing function, computer system using the integrated circuit device and clock frequency changing method - Google Patents

Integrated circuit device having clock frequency changing function, computer system using the integrated circuit device and clock frequency changing method Download PDF

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US6643792B1
US6643792B1 US09/665,684 US66568400A US6643792B1 US 6643792 B1 US6643792 B1 US 6643792B1 US 66568400 A US66568400 A US 66568400A US 6643792 B1 US6643792 B1 US 6643792B1
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clock frequency
clock
bus
signal
changing
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Yasuhiko Kurosawa
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Toshiba Corp
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Toshiba Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

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  • the present invention relates to a large-scale integrated circuit device (to be referred to as an LSI hereinafter) having a clock frequency changing function and a computer system using the large-scale integrated circuit and a clock frequency changing method.
  • LSI large-scale integrated circuit device
  • the method I is applied to a relatively small number of products such as ASIC (Application Specific Integrated Circuit) for specific applications.
  • ASIC Application Specific Integrated Circuit
  • the method III is used as a method for preventing a timing error by decreasing an operation frequency when an LSI cannot be cooled even though a cooling fan or the like is used in a notebook type personal computer or the like.
  • the design conditions in the method II are milder than those in the method I. However, conditions such as a peripheral temperature and a power supply voltage are often severer than the real usage conditions, and an LSI must be used in a state in which operation performance is lower than the actual operation performance.
  • the practical maximum operation frequency of an LSI is fixedly determined every product within a range of performance lower than the maximum performance of the LSI.
  • a mechanism for multiplying an operation frequency of a processor or the like with a base clock of a system bus or the like by setting a register may be incorporated.
  • a clock frequency is changed by using interruption while the system is operated in a stable condition.
  • a computer (more-specifically, LSI) can be operated to achieve the actual capability of the computer (LSI). For this reason, the technique is useful to solve the problems.
  • the clock frequency changing technique is not always sufficient.
  • the present inventor proposes “Clock Generation Circuit and Clock Generation Method” which can changes a clock frequency in Japanese Patent Application No. 11-318771 (unpublished), so that an LSI to which the clock generation circuit (or the clock generation method) is applied is stably operated to achieve the maximum performance in an actual operation state.
  • a device for dynamically changing a clock frequency in a system operation in synchronism with another LSI (clock generation circuit included therein) is not considered.
  • an object of the present invention to provide an integrated circuit device having a clock frequency changing function which can dynamically change the frequency of a clock generated by the integrated circuit device in synchronism with another integrated circuit device, and a computer system having the integrated circuit device and a clock frequency changing method.
  • an LSI which incorporates a clock generation circuit which can change a clock frequency, which is connected to a system bus and a clock control bus independent of the system bus together with another LSI, which operates in synchronous with the other LSI by the clock generated by the incorporated clock generation circuit, and which has a clock frequency changing function, including clock frequency changing means which dynamically executes changing of a clock frequency of the incorporated clock generation circuit by using at least the clock control bus in synchronism with another LSI.
  • the clock control bus for changing a clock frequency of every LSI, the clock frequency can be dynamically changed during system operation in synchronism with each other.
  • the clock frequency changing means includes clock state determination means for operating the first and second signals such that a present clock state can be designated, so that the clock frequency may be changed on the basis of the clock state designated by the first and second signals.
  • a clock state in which the clock frequency must be changed in the direction opposing the predetermined direction may be indicated.
  • a third signal representing that the clock frequency must be changed in the direction opposing the predetermined direction may be added.
  • the system bus may also be used to change the clock frequency, and the clock frequency may be synchronously changed by using a bus transaction on the system bus.
  • a bus transaction on the system bus is used, a relatively high-speed clock can be controlled depending on the performance of the system bus.
  • the clock frequency changing means for an LSI serving as a master for a clock frequency changing operation using the bus transaction comprises:
  • timing adjustment means for waiting until a second number of clock cycles elapse after a normal completion response notification from the target for the issued bus transaction.
  • the clock frequency is changed after the second number of clock cycles elapse.
  • the clock frequency changing means for an LSI serving as a target which changes a clock frequency by using the bus transaction comprises normal completion response means for notifying a master of a normal completion response of the bus transaction when the bus transaction for clock frequency changing is issued from an LSI serving as a master, if the clock frequency can be changed, upon completion of execution of the bus transaction; and timing adjustment means for waiting until a predetermined number of clock cycles elapse after the normal completion response notification.
  • the clock frequency may be changed after the predetermined number of clock cycles (second number of clock cycle counts) elapse.
  • the frequency changing means for another LSI except for the LSIs of a master and a target comprises timing adjustment means for waiting until a predetermined number of clock cycles elapse after a normal completion response notification of a bus transaction from the target to the master when the bus transaction for clock frequency changing is issued from the master, if the clock frequency can be changed.
  • the clock frequency may be changed after the predetermined number of clock cycles (second number of clock cycles) elapse.
  • the clock frequency can be synchronously changed between LSIs by retrying a bus transaction even though a clock frequency cannot be changed in the target.
  • changing disable notification means for notifying another LSI that the clock frequency cannot be changed by simultaneously asserting two predetermined signals on the system bus which are set in a state in which only one of the signals is asserted in a normal state or a state in which both the signals are deasserted when the clock frequency cannot be changed is added to a clock frequency changing means for another LSI except for the LSIs of the master and the target, another LSI can be notified that the clock frequency cannot be changed without a new special signal. For this reason, a bus transaction can be retried. A function of returning a retry response to the master even though the two predetermined signals are simultaneously asserted may be added to the retry response means of the target.
  • a dedicated changing disable notification signal may be prepared.
  • the clock frequency changing means comprises:
  • synchronization confirmation means for executing, at least once, an operation of confirming that clock frequency changing operations are synchronized with each other between the LSI and another LSI by operating at least the first or second signal at a predetermined timing when the specific state is detected by the detecting means and when the clock frequency can be changed.
  • the clock frequency is changed on the basis of the confirmation result of the synchronization confirmation means.
  • synchronization confirmation means comprises:
  • synchronization confirmation signal operation means for performing an operation of asserting at least one of the first and second signals at a predetermined first timing and then deasserting the asserted signal at a predetermined second timing when synchronization confirmation is executed once;
  • timing detecting means for detecting the presence/absence of coincidence of an operation timing obtained by the synchronization confirmation signal operation means and operation timings obtained by the synchronization confirmation signal operation means of all other LSIs, and synchronization is confirmed depending on the timing coincidence detection performed by the timing detecting means, synchronization confirmation can be easily confirmed.
  • this method since the signals of the clock control buses are simultaneously asserted and deasserted in all the LSIs, an increase in speed of the clock control bus is more different than an increase in speed of the system bus. For this reason, unlike the method for using a bus transaction on the system bus described above, this method is preferably applied to a frequency changing operation of a relatively low-speed clock. As a matter of course, when a clock control bus having a sufficiently high speed as compared with the clock frequency is used, the above limitation is withdrawn.
  • clock frequency changing means comprises:
  • frequency changing preparation incompletion notification signal operation means for operating at least one predetermined signal of the clock control bus to set a state representing clock frequency changing preparation incompletion when the clock frequency cannot be changed;
  • clock frequency changing stop means for stopping a clock frequency changing operation when the clock frequency changing preparation incompletion is represented by an operation of the preparation incompletion notification signal operation means or an operation of a preparation incompletion notification signal operation means of another LSI, it is possible to stop the clock frequency changing operation when preparation for a clock frequency changing operation in any one of the LSIs connected to the system bus and the clock control bus is uncompleted.
  • clock frequency changing delaying means for delaying a clock frequency changing operation when clock frequency changing preparation incompletion is represented by an operation of the preparation incompletion notification signal operation means of its own LSI or another LSI
  • the clock frequency changing operation can be delayed when preparation for a clock frequency changing operation is uncompleted in any one of the LSIs connected to the system bus and the clock control bus.
  • the delay time can be controlled by a duration of time of a state representing clock frequency changing preparation completion.
  • a predetermined time or a time exceeding the predetermined time can be selected as the duration time of a state representing the clock frequency changing preparation incompletion
  • the predetermined time represents that the clock frequency changing operation is stopped
  • the time exceeding the predetermined time represents that the clock frequency changing operation is delayed by the time, so that the stop or delay of the clock frequency changing operation can also be selectively executed.
  • a dedicated signal representing the clock frequency changing preparation incompletion can also be assigned as at least one predetermined signal described above.
  • the specific states may be represented by using the first and second signals.
  • the clock frequency changing preparation incompletion may be represented by the first signal representing that the clock frequency need not be changed and the second signal representing the clock frequency changing preparation incompletion.
  • An LSI according to the present invention and having a clock frequency function includes:
  • Another LSI according to the present invention and having a clock frequency changing function comprises:
  • clock frequency changing operations can be synchronously performed between LSIs by using both the clock control bus and the system bus.
  • a still another LSI according to the present invention and having a clock frequency changing function comprises:
  • a still another LSI according to the present invention and having a clock frequency changing function comprises:
  • clock frequency changing operations can be synchronously performed between LSIs by using a clock control bus.
  • the present invention is also exemplified as an invention related to a computer system including a plurality of LSIs each having the above configuration, the plurality of LSIs being connected to each other by a system bus and a clock control bus.
  • a system monitor bus for connecting the plurality of LSIs to each other and a system monitor device, connected to the system monitor device, for detecting a difference between the clock frequencies of the LSIs by loading pieces of information for determining clock frequencies of the clock generation circuits incorporated in the LSIs and comparing the pieces of information, it can be secured that the set states of the clock frequencies are matched to each other in the entire system.
  • the present invention related to the computer system is also exemplified as an invention related to a method, i.e., a clock frequency changing method.
  • FIG. 1 is a block diagram showing the configuration of a computer system comprising a plurality of LSIs each having a clock frequency changing function according to a first embodiment of the present invention
  • FIG. 2 shows a table indicating the relationship between present clock states and combination output contents of a HOLD signal and a DOWN signal in the first embodiment
  • FIG. 3 shows a table indicating the relationship between combinations of the HOLD signal and the DOWN signal and clock changing operation contents (next clock states) of LSIs in the first embodiment
  • FIG. 4 is a flow chart for explaining a clock frequency changing operation of a master processor 3 in the first embodiment
  • FIG. 5 is a flow chart for explaining a clock frequency changing operation of a target LSI (in this case, memory controller 60 of host-PCI bridge 6 ) in the first embodiment;
  • a target LSI in this case, memory controller 60 of host-PCI bridge 6
  • FIG. 6 is a flow chart for explaining a clock frequency changing operation of another LSI except for the LSI of a master processor and a target LSI in the first embodiment;
  • FIG. 7 is a timing chart obtained when retry is not performed to a bus transaction for clock frequency changing in the first embodiment
  • FIG. 8 is a timing chart obtained when a target LSI (memory controller 60 ) retries in the first embodiment
  • FIG. 9 is a timing chart obtained when another LSI except for the LSI of a master processor 3 and a target LSI make a target LSI (memory controller 60 ) retry in the first embodiment;
  • FIG. 10 is a timing chart obtained when retry is not performed to a bus transaction for clock frequency changing in the first embodiment
  • FIG. 11 is a timing chart obtained when a target LSI (memory controller 60 ) retries in the first embodiment
  • FIG. 12 shows a table indicating the relationship between present clock states and combination output contents of the HOLD signal and the DOWN signal according to a second embodiment of the present invention
  • FIG. 13 shows a table indicating the relationship between combinations of the HOLD signal and the DOWN signal and clock changing operation contents (next clock states) of LSIs in the second embodiment
  • FIG. 14 shows a part of a flow chart for explaining a clock frequency changing operation of each LSI in the second embodiment
  • FIG. 15 shows another part of the flow chart for explaining the clock frequency changing operation of each LSI in the second embodiment
  • FIG. 16 shows another part of the flow chart for explaining the clock frequency changing operation of each LSI in the second embodiment
  • FIG. 17 shows another part of the flow chart for explaining the clock frequency changing operation of each LSI in the second embodiment
  • FIG. 18 shows the rest of the flow chart for explaining the clock frequency changing operation of each LSI in the second embodiment
  • FIG. 19 is a timing chart obtained when a clock frequency changing operation for decreasing a clock frequency is performed at a timing which is not delayed in the second embodiment
  • FIG. 20 is a timing chart obtained when a clock frequency changing operation for decreasing a clock frequency is performed at a timing which is delayed in the second embodiment
  • FIG. 21 is a timing chart obtained when a clock frequency changing operation for increasing a clock frequency is performed at a timing which is not delayed in the second embodiment
  • FIG. 22 is a timing chart obtained when a clock frequency changing operation for increasing a clock frequency is performed at a timing which is delayed in the second embodiment.
  • FIG. 23 is a timing chart obtained when a clock frequency changing operation for increasing a clock frequency is stopped in the second embodiment.
  • FIG. 1 is a block diagram showing the configuration of a computer system (multi-processor system) comprising a plurality of LSIs each having a clock frequency changing function according to the first embodiment of the present invention.
  • a plurality of LSIs i.e., processors 3 to 5 in which clock generation circuits CG which can dynamically change clock frequencies to optimum values depending on various conditions such as temperatures and environments are incorporated, a host-PCI (Peripheral Component Interconnect) bridge 6 , and other devices 7 are connected to a processor bus 1 and a clock control bus 2 .
  • the host-PCI bridge 6 is also connected to a PCI bus 8 and a main memory 9 .
  • the host-PCI bridge 6 contains the function of a main memory controller, and it is also called a memory controller 6 in this document.
  • Each of the clock generation circuits CG includes a frequency setting register R for designating a frequency of a clock generated by the clock generation circuit CG.
  • the frequency setting register R represents the frequency that is generated by the clock generation circuit CG such that larger value of frequency setting register R corresponds to the higher clock frequency that CG generates.
  • the processors 3 to 5 comprise cache memories (not shown), in which parts of information in the main memory 9 are stored, inside or outside the processors 3 to 5 .
  • the contents of the cache memories are controlled such that the main memory 9 and the cache memories are coherent, i.e., cache coherency is kept.
  • the processor bus 1 is a bus (system bus) used when the processors (processors 3 to 5 or the like) mainly access the memory (e.g., the main memory 9 ).
  • a bus structure in which a signal line is used for transferring addresses and data in a time sharing manner or a bus structure in which independent signal lines are arranged for addresses/data is applied. Either one of the bus structures may be used.
  • the processor bus 1 comprises an address line (address bus) and a data line (data bus), and that a plurality of LSIs using the processor bus 1 are connected to both the address bus and the data bus.
  • a PentiumPro R bus used in a PentiumPro processor or the like available from Intel Corporation is known.
  • the device may be connected to only one of an address bus and a data bus as will be described later.
  • the clock control bus 2 is a bus for adjusting a clock frequency.
  • the clock control bus 2 is constituted by wired-OR buses obtained by connecting two signals, e.g., the HOLD signal and the DOWN signal to each other by an open collector.
  • the DOWN signal is a signal representing that a clock frequency must be changed in a predetermined direction, and is, in this embodiment, a signal (first signal) representing that the clock frequency must be decreased.
  • the HOLD signal is a signal (second signal) representing that a clock frequency must be changed in a direction opposing the direction of the DOWN signal or representing that a change in clock frequency is not necessary.
  • the host-PCI bridge 6 is a bridge device for bi-directionally connecting the processor bus 1 and the PCI bus 8 such that a device on one of the processor bus 1 and the PCI bus 8 can access a device on the other bus.
  • a memory controller 60 for performing access control to the main memory 9 is incorporated in the host-PCI bridge 6 .
  • the host-PCI bridge 6 can function as a bus master on the PCI bus 8 .
  • the processors 3 to 5 , the host-PCI bridge 6 , and the other devices 7 connected to the processor bus 1 and the clock control bus 2 are connected to a system monitor LSI (system monitor device) 11 serving as a master of a serial bus 10 via a system monitor bus, e.g., the serial bus 10 having one-bit data line and a clock line like I 2 C Bus (Inter IC Bus) defined by Philips.
  • the system monitor LSI 11 is designed such that the values of frequency setting registers R in the clock generation circuits CG incorporated in the LSIs on the serial bus 10 can be read by issuing a bus transaction onto the serial bus 10 .
  • the system monitor LSI 11 periodically or occasionally reads the values of the frequency setting registers R of the LSIs in response to a request from software such as an OS (operating system) or a request of software operated by the system monitor LSI 11 itself.
  • software such as an OS (operating system) or a request of software operated by the system monitor LSI 11 itself.
  • Each of the LSIs such as processors 3 to 5 or the like, connected to the processor bus 1 and the clock control bus 2 has a function of dynamically changing the frequency of a clock generated by the incorporated clock generation circuit CG by a method in which the frequency can be dynamically changed during an operation of the system and a stable operation can be achieved immediately after the changing operation.
  • each LSI has a clock state determining function for outputting the HOLD signal and the DOWN signal in combinations shown in FIG. 2 depending on a present operation state, preferably, depending on a margin for a clock frequency in the present operation state.
  • ⁇ indicates that a signal is asserted
  • X indicates that a signal is not asserted.
  • a state in which “clock frequency is excessively high”, a state in which “present clock (frequency thereof) is optimum”, and a state in which “clock frequency can be increased” are defined.
  • clock frequency is excessively high
  • the LSI asserts only the DOWN signal.
  • the LSI asserts only the HOLD signal.
  • clock frequency can be increased the LSI does not assert both the HOLD signal and the DOWN signal.
  • the HOLD signals and the DOWN signals from the LSIs are connected to the clock control bus 2 by an open collector. For this reason, when any one of the LSIs asserts a signal (HOLD signal or DOWN signal) of the clock control bus 2 , the logic of the signal is active (true) on the clock control bus 2 . In addition, when all the LSIs deassert signals (HOLD signals or DOWN signals) of the clock control bus 2 , the logic of the signals are inactive (false) on the clock control bus 2 .
  • Each LSI prepares a clock frequency changing operation by a combination of the HOLD signal and the DOWN signal of the clock control bus 2 .
  • the relationship between combinations of the HOLD signal and the DOWN signal and clock changing operation contents (next clock states) of the LSIs is shown in FIG. 3 .
  • the LSI begins to prepare a clock frequency to be decreased (the value of the frequency setting register R is decreased, e.g., ⁇ 1).
  • the LSI does not change the clock frequency.
  • the LSI starts preparation for increasing a clock frequency (the value of the frequency setting register R is increased, e.g., +1).
  • Preparation for changing a clock frequency according to the combination of the HOLD signal and the DOWN signal is started when a state in which the clock frequency determined by the combination of the HOLD signal and the DOWN signal is changed continues for a predetermined number of clock cycles, e.g., 10 or more clock cycles.
  • the clock frequency changing operations in the LSIs are simultaneously executed, i.e., that the clock frequency changing operations in the LSIs are executed in synchronism with each other.
  • a processor serving as a master in booting the system is used as a master for changing the clock frequency.
  • the processor 3 serves as a master processor.
  • the processor 3 serving as the master for clock frequency changing operations issues a bus transaction for synchronously changing clock frequencies to the processor bus 1 when it is determined that the clock frequency should be changed.
  • This transaction may simply represent that the clock frequency should be increased or decreased, or may simply represent that the clock frequency should be changed.
  • the clock generation circuits CG each of which can change the clock frequency are incorporated in the LSIs connected to the processor bus 1 , and the HOLD signal and the DOWN signal is connected to each of the LSIs. Therefore, a direction of a clock frequency changing operation is decided by each LSI itself on the basis of the combination of the HOLD signal and the DOWN signal in FIG. 3 . For this reason, when a bus transaction representing only that the clock frequency should be changed is issued from the master processor 3 to the processor bus 1 , other LSIs can execute a clock frequency changing operation.
  • a dedicated bus command may be used, or access to a specific address (read or write) may be used.
  • the processor 3 serving as a master issues a write transaction to a predetermined address.
  • the clock frequencies are changed simultaneously after a predetermined number of clock cycles, e.g., 100 clock cycles.
  • the second embodiment employs a method using a dedicated bus command and a clock control bus.
  • FIG. 4 is a flow chart for explaining a clock frequency changing operation in the processor 3
  • FIG. 5 is a flow chart for explaining a clock frequency changing operation of a target LSI (in this case, the memory controller 60 of the host-PCI bridge 6 ) serving as a target of a bus transaction performed by the processor 3
  • FIG. 6 is a flow chart for explaining a clock frequency changing operation of another LSI except for the LSI of the processor 3 and the target LSI.
  • FIGS. 7 to 9 are timing charts obtained when clock frequencies are decreased, in which: FIG. 7 shows a case in which retry is not performed to a bus transaction for clock frequency changing; FIG.
  • FIGS. 10 and 11 are timing charts obtained when clock frequencies are increased, in which: FIG. 10 shows a case in which retry is not performed to a bus transaction for clock frequency changing; and FIG. 11 shows a case in which the target LSI (memory controller 60 ) retries.
  • PentiumPro bus used in a PentiumPro processor or the like available from Intel Corporation in the U.S.A.
  • PentiumPro bus protocol requires are and only bus transaction target to each address.
  • memory controller 60 becomes the target device.
  • signals of the PentiumPro bus the following signal groups are known:
  • the HIT signal represents that cache memories are set in a SHARED state (the contents of the cache memories are equal to the information in the main memory 9 ).
  • the HITM signal represents that any one of the cache memories is set in a MODIFIED state (the contents of the cache memories are updated not to equal to the information in the main memory 9 ).
  • the DEFER signal represents that the target is retried or deferred (delayed). The transaction is aborted by the retry, and the transaction is executed again later by the deferring.
  • the bus transaction on the PentiumPro bus has the following phases:
  • the bus agent serving as the target is generally a memory controller or a PCI bus bridge.
  • the bus agent is the memory controller 60 on the host-PCI bridge 6 .
  • the order of descending priorities of the signals used in the snoop phase is given by: HITM ⁇ DEFER ⁇ HIT.
  • a processor serving as a master for a clock frequency changing operation e.g., the master processor 3 determines to decrease the clock frequency regardless of the state of the HOLD signal when a state in which the DOWN signal on the clock control bus 2 is asserted (i.e., a state representing that the clock signal must be decreased) continues by 10 or more clock cycles (FIGS. 7 to 9 ).
  • the master processor 3 determines to increase the clock frequency when a state in which both the HOLD signal and the DOWN signal on the clock control bus 2 are asserted (i.e., a state representing that the clock frequency must be increased) by 10 or more clock cycles (FIGS. 10 and 11 ).
  • step S 1 When the master processor 3 determines that the clock frequency must be changed (step S 1 ), the master processor 3 asserts a “bus request” signal on the processor bus 1 to request the usage right of the processor bus 1 (from a bus arbiter (not shown)) (step S 2 ).
  • the master processor 3 acquires the usage right of the processor bus 1 (YES at step S 3 )
  • the master processor 3 issues a write transaction for a predetermined address “A” to change a clock frequency (at a point of time t 1 in FIGS. 7 to 10 ) (step S 4 ).
  • the target of the bus transaction is the memory controller 60 of the host-PCI bridge 6 .
  • a target LSI (target device), i.e., the memory controller 60 of the host-PCI bridge 6 on the processor bus 1 , as shown in FIG. 5, determines at step S 12 whether the clock frequency changing operation can be performed or not at present when the bus transaction for clock frequency changing to the target LSI itself, i.e., a write transaction for the address “A” is generated (YES at step S 11 ).
  • the memory controller 60 determines at step S 13 whether both the signals, i.e., the HIT signal and the HITM signal on the clock control bus 2 are asserted or not (by another LSI which cannot change the clock frequency at step S 28 (to be described later)), i.e., whether an LSI which cannot change the clock frequency exists or not (step S 13 ).
  • the memory controller 60 determines that an LSI which cannot change the clock frequency does not exist, therefore, that the clock frequency may be changed. In this case, the memory controller 60 executes a bus transaction, from the master processor 3 , for changing a clock frequency, and returns a “normal” response to the master processor 3 by a response signal in the response phase as in states 70 b and 100 b in FIGS. 7 and 10 to complete the bus transaction (step S 14 ).
  • the memory controller 60 waits until a predetermined number of clock cycles, e.g., 100 cycles elapse from a point of time t 2 at which a bus transaction (write transaction) is completed (i.e., reaches a point of time t 3 in FIGS. 7 and 10 )(YES at step S 15 ), and changes a value “N” of the frequency setting register R in its own clock generation circuit CG by only 1 (decreased by only 1 in the example in FIG. 7 and increased by only 1 in the example in FIG. 10 ). In this manner, the moment the clock frequency is changed by a predetermined amount, the memory controller 60 deasserts the DOWN signal and asserts the HOLD signal (step S 16 ). It is determined at step S 17 that a clock frequency changing operation is synchronized with the changes of the DOWN signal and the HOLD signal. If it is not determined, an alarm or the like is generated.
  • a predetermined number of clock cycles e.g., 100 cycles elapse from a point of time t
  • step S 18 asserts the DEFER signal in snoop phases 90 b and 110 b after two clock cycles (step S 18 ), returns a retry response to the master processor 3 in response phases 90 c and 10 c (step S 19 ), and waits at step S 11 until a bus transaction for clock frequency changing is reissued from the master processor 3 .
  • the memory controller 60 When the memory controller 60 cannot change the clock frequency because the memory controller 60 accesses the main memory 9 (NO at step S 12 ), as in the example in FIG. 8, the DEFER signal is asserted in a snoop phase 80 a (step S 18 ), a retry response is returned in the response phases 80 b (step S 19 ), and thereafter, the memory controller 60 returns to step S 11 .
  • an LSI in this case, the processors 4 and 5 and the other devices 7 ) except for the target LSI (memory controller 60 ) determines at step S 22 whether or not a clock frequency changing operation can be performed at present when the bus transaction for clock frequency changing is detected as shown in FIG. 6 (step S 21 ).
  • LSIs (to be referred to as non-master/non-target LSIs hereinafter) except for the target LSI (memory controller 60 ) determine at step S 23 whether or not both the signals, i.e., the HIT signal and the HITM signal on the clock control bus 2 are asserted by another LSI if the clock frequency of the LSIs can be changed (step S 23 ).
  • the non-master/non-target LSIs determine that an LSI which can change the clock frequency does not exist, therefore, the clock frequency may be changed.
  • the non-master/non-target LSIs wait until a response signal is returned from the target LSI (memory controller 60 ) to the master processor 3 in the response phase, i.e., wait until the bus transaction is completed.
  • the non-master/non-target LSIs monitor the processor bus 1 and detect that the response signal is returned in the response phase, the non-master/non-target LSIs determine whether the response signal is a “normal” response signal or a retry response signal (step S 24 ).
  • the non-master/non-target LSIs determine that the bus transaction is normally completed, and wait until 100 cycles elapse from a point of time t 2 (i.e., reaches the point of time t 3 in FIGS. 7 and 10) (step S 25 ).
  • Each of the non-master/non-target LSIs changes the value “N” of the frequency setting register R in the clock generation circuit CG by only 1 (decreased by only 1 in the example in FIG. 7, and increased by only 1 in the example in FIG.
  • step S 26 the non-master/non-target LSIs change the clock frequency and, at the same time, deassert the DOWN signal and assert the HOLD signal (step S 26 ).
  • step S 27 the non-master/non-target LSIs determine that the clock frequency changing operation is reliably synchronized with the changes of the DOWN signal and the HOLD signal. If it is not determined at step S 27 , an alarm or the like is generated.
  • the non-master/non-target LSIs determine that an LSI which cannot change the clock frequency exists, therefore, the clock frequency may not be changed. In this case, the non-master/non-target LSIs return to step S 21 to wait until retry of a bus transaction for clock frequency changing is performed.
  • the non-master/non-target LSIs return a retry response from the target LSI (memory controller 60 ) to the master processor 3 as in the state in FIG. 8 (response phase 80 b ) (NO at step S 24 ), the non-master/non-target LSIs return to step S 21 to wait until the retry of the bus transaction for clock frequency changing is performed.
  • both the signals i.e., the HIT signal and the HITM signal are asserted (step S 28 ) as in the examples in FIGS. 9 and 10. Thereafter, the non-master/non-target LSIs return to step S 21 to wait until the bus transaction for clock frequency changing is performed.
  • the master processor 3 which issues the bus transaction for clock frequency changing monitors whether or not a retry response is returned in a response phase, from the target LSI (memory controller 60 ), for the transaction (step S 5 ).
  • step S 6 determines completion of the bus transaction (step S 6 ), and waits until 100 cycles elapse from the point of time t 2 (i.e., reaches the point of time t 3 in FIGS. 7 and 10) (step S 7 ).
  • the master processor 3 changes the value “N” of the frequency setting register R in the clock generation circuit CG of each of the non-master/non-target LSIs by only 1 (decreased by only 1 in the example in FIG. 7, and increased by only 1 in the example in FIG. 10 ), so that the master processor 3 changes the clock frequency and, at the same time, deasserts the DOWN signal and asserts the HOLD signal (step S 8 ).
  • step S 9 the master processor 3 determines that the clock frequency changing operation is reliably synchronized with the changes of the DOWN signal and the HOLD signal. If it is not determined, an alarm or the like is generated.
  • the master processor 3 executes steps S 1 to S 4 again, and issues a bus transaction for clock frequency changing to the processor bus 1 again. If all the target LSI (memory controller 60 ) and the non-master/non-target LSIs can change the clock frequencies in the reissue of the bus transaction, i.e., retry, as in the examples in FIGS.
  • a “normal” response is returned from the target LSI (memory controller 60 ) at the point of time t 2 , the master processor 3 waits until 100 cycles elapse from the point of time t 2 (i.e., reaches the point of time t 3 in FIGS. 8, 9 , and 11 ) to change the value “N” of the frequency setting register R in the clock generation circuit CG of the master processor 3 by only 1 (decreased by only 1 in the example in FIGS. 8 and 9, and increased by only 1 in the example in FIG. 11 ), so that the master processor 3 also changes the clock frequency.
  • the master processor 3 retries the bus transaction.
  • the mechanism of the retry will be orderly described below.
  • step S 18 When the memory controller 60 (target LSI) cannot change the clock frequency (NO at step S 12 ), the memory controller 60 asserts a DEFER in a snoop phase (step S 18 ), and retries in a response phase (step S 19 ).
  • step S 28 Even though the memory controller 60 (target LSI) can change the clock frequency, when other LSIs (non-master/non-target LSIs) cannot change the clock frequency, the non-master/non-target LSIs simultaneously assert the HIT signals and the HITM signals in the snoop phase (step S 28 ). For this reason, this is monitored by the memory controller 60 itself (YES at step S 13 ), the DEFER signal is asserted in a snoop phase after two clock cycles (step S 18 ), and retry is performed in the response phase (step S 19 ).
  • step S 21 When a bus transaction for clock frequency changing is issued from the master processor 3 to the memory controller 60 (target LSI) (step S 21 ), if the non-master/non-target LSIs cannot change the clock frequency (NO at step S 22 ), the non-master/non-target LSIs assert the HIT signal as well as the HITM signal in the snoop phase in order to make the memory controller 60 (target LSI) retry the bus transaction for clock frequency changing (step S 28 ). In this case, the memory controller 60 (target LSI) asserts the DEFER signal by the mechanism shown in item (b) in the snoop phase after two clock cycles, and retries the transaction in the response phase.
  • each of the LSIs changes the clock frequencies simultaneously when 100 clock cycles elapse after the transaction is completed, and, at the same time, deasserts the DOWN signal and asserts the HOLD signal to complete the clock frequency changing operation (steps S 8 , S 16 , and S 26 ).
  • steps S 9 , S 17 , and S 27 it is determined at steps S 9 , S 17 , and S 27 whether or not the clock frequency changing operations are reliably synchronized with the changes of the DOWN signals and the HOLD signals. If NO at steps S 9 , S 17 , and S 27 , alarms or the like generated.
  • the retry mechanism for a bus transaction for clock frequency changing is arranged.
  • the retry mechanism is not necessarily required.
  • the system monitor LSI 11 serving as the master of the serial bus 10 can periodically or occasionally issue a bus transaction onto the serial bus 10 , and can read the values of the frequency setting registers R of the LSIs 3 to 7 .
  • the serial bus 10 compares the values of the frequency setting registers R of the LSIs 3 to 7 with each other (for example, the set value of the master processor 3 is compared with the set values of the other LSIs). If some value is different from the other values, abnormality is detected. In this manner, it is secured that the clock frequency setting states in the LSIs 3 to 7 are matched with each other in the entire system.
  • a clock frequency changing transaction issued from the master processor 3 onto the processor bus 1 , for the target LSI (memory controller 60 ), i.e., a write transaction, for an address “A”, for performing clock frequency changing operations of the LSIs in synchronism with each other does not designate directions of the frequency changing operations.
  • the LSIs determine the frequency changing directions on the basis of the combinations of the HOLD signal and the DOWN signal on the clock control bus 2 .
  • the present invention is not limited to the embodiment.
  • two types of bus transactions i.e., a write transaction for the address “A” and a write transaction for an address “A′” may be prepared.
  • One transaction may apparently designate a decrease of the clock frequency, and the other transaction may apparently designate an increase of the clock frequency.
  • Write transactions for addresses B and B are added in dependently of the write transactions for the addresses A and A′ to designate different amounts of clock frequency changing. For example, one transaction may change the values of the frequency setting registers R by only 1, and the other transaction may change the values of the frequency setting registers R by only 2.
  • an UP signal representing an increase of the clock signal can be prepared.
  • the structure of the clock control bus 2 is slightly complex, it can be apparently designated by only the UP signal that the clock frequency must be increased. For this reason, control is easily performed.
  • the characteristic feature of this embodiment is as follows. That is, a master for changing a clock frequency does not exist, and respective LSIs change the clock frequency according to the same algorithm.
  • clocks used in the LSIs 3 to 7 have speeds lower than the speed of the clock control bus 2 , or the speed of the clock control bus 2 is sufficiently higher than that of each clock.
  • the clock frequency can be changed at a timing at which a signal on the clock control bus 2 is deasserted.
  • the signals on the clock control bus 2 are the same as those in the first embodiment, and are two types of signals, i.e., the HOLD signal and the DOWN signal.
  • present clock states in addition to three types of states, i.e., “clock frequency is excessively high”, “present clock is optimum”, and “clock frequency can be increased”, a state “clock frequency changing is prohibited” is newly defined.
  • FIG. 12 shows the relationship between present clock states applied in the second embodiment and combination output contents of the HOLD signal and the DOWN signal.
  • the second embodiment is different from the first embodiment in that, in a state “clock frequency changing is prohibited”, each of the LSIs (the processors 3 to 5 , the host-PCI bridge 6 , and the other devices 7 ) asserts the HOLD signal and the DOWN signal.
  • the LSIs prepare to change the clock frequency by the combinations of the HOLD signal and the DOWN signal.
  • the relationship between the combinations of the HOLD signal and the DOWN signal and the clock changing operation contents (next clock states) of the LSIs is shown in FIG. 13 .
  • FIG. 13 is different from FIG. 3 in the first embodiment in that a state in which both the HOLD signal and the DOWN signal are asserted is not defined as a state in which preparation for “clock frequency is decreased” is started, but is redefined as a state “completion of preparation for clock frequency changing”.
  • a clock frequency changing operation is performed once 200 clock cycles at most.
  • FIGS. 14 to 18 are flow charts for explaining clock frequency changing operations in the LSIs.
  • FIGS. 19 and 20 are timing charts showing a decrease of the clock frequency, in which FIG. 19 shows a case in which a clock frequency changing operation is performed at a timing which is not delayed; and FIG. 20 shows a case in which a clock frequency changing operation is performed at a timing which is delayed.
  • FIGS. 21 to 23 are timing charts showing an increase of the clock frequency, in which FIG. 21 shows a case in which a clock frequency changing operation is performed at a timing which is not delayed;
  • FIG. 22 shows a case in which a clock frequency changing operation is performed at a timing which is delayed; and
  • FIG. 23 shows a case in which a clock frequency changing operation is stopped.
  • FIGS. 14 and 15 An operation performed when a clock frequency is decreased is as shown in FIGS. 14 and 15.
  • the LSIs (to be referred to as LSIs 3 to 7 hereinafter) of the processors 3 to 5 , the host-PCI bridge 6 , and the other devices 7 which are connected to the clock control bus 2 deassert the HOLD signal (YES at step S 32 and step S 33 ) to start preparation for decreasing the clock frequency (step S 34 ).
  • preparation for decreasing a clock frequency is to wait for completion of an operation (process) which may be erroneous by changing the clock frequency and not to newly start such an operation.
  • the LSIs 3 to 7 determine whether preparation for decreasing the clock frequency is completed or not (step S 36 ). If the LSIs 3 to 7 includes an LSI which does not complete the preparation (NO at step S 36 ), the LSI asserts the HOLD signal at time t 1 in FIG. 20 (step S 36 a ) to prevent a clock frequency changing operation from being performed, and returns to step S 31 to the process of changing the clock frequency again.
  • the LSIs 3 to 7 determine whether or not the HOLD signal is asserted by the other LSIs, i.e., whether or not an LSI which does not complete the preparation exists (step S 37 ). If the HOLD signal is asserted (YES at step S 37 ), the LSIs return to step S 31 to perform the process of changing the clock frequency again.
  • the LSIs 3 to 7 complete the preparations for decreasing clock frequencies.
  • the LSIs 3 to 7 detect that the DOWN signal on the clock control bus 2 is deasserted (YES at step S 40 )
  • the LSIs 3 to 7 assert the HOLD signals simultaneously when predetermined number of clock cycles, e.g., 7 clock cycles elapse (time t 2 in FIG. 19) (steps 41 to 43 in FIG. 15 ).
  • the HOLD signal is asserted by another LSI before 7 clock cycles elapse (YES at step S 41 in FIG. 15 )
  • the clock changing operations may not be synchronized with each other between the LSIs 3 to 7 . For this reason, the clock frequency changing operations are aborted, and the processes are ended (step S 44 ).
  • step S 43 When the LSIs 3 to 7 can assert the HOLD signals simultaneously (step S 43 ), i.e., can confirm that synchronization between the LSIs 3 to 7 is established, the LSIs 3 to 7 deassert the DOWN signals simultaneously after a predetermined number of clock cycles, e.g., 8 clock cycles elapse (step S 45 ). In this manner, the HOLD signal on the clock control bus 2 is deasserted at the time t 3 in FIG. 19 . However, when the HOLD signal is kept asserted (YES at step S 46 ), an LSI which deasserts the HOLD signal at a delayed timing exists and the clock frequency changing operations may not be synchronized with each other. For this reason, the clock frequency changing operation is aborted, and the processes are ended (step S 44 ).
  • a predetermined number of clock cycles e.g. 8 clock cycles elapse
  • the LSIs 3 to 7 can deassert the HOLD signals simultaneously, when the LSIs 3 to 7 detect that the HOLD signal on the clock control bus 2 is deasserted (NO at step S 46 ), i.e., when it is confirmed that the synchronization between the LSIs 3 to 7 is established, the LSIs 3 to 7 decrease the values N of the frequency setting registers R in the clock generation circuits CG of the LSIs 3 to 7 by 1 at time t 4 in FIG. 19 after a predetermined number of clock cycles, e.g., 85 clock cycles elapse (step S 47 ) to change the clock frequencies by predetermined amounts in a descending direction (step S 48 ).
  • a predetermined number of clock cycles e.g. 85 clock cycles elapse
  • the LSIs 3 to 7 assert the HOLD signals simultaneously when a predetermined number of clock cycles, e.g., 5 clock cycles elapse at time t 5 in FIG. 19 after the clock frequencies are changed (YES at step S 49 ), and end the process (step S 50 ). At this time, the LSIs 3 to 7 monitor the HOLD signal on the clock control bus 2 until 5 clock cycles elapse (step S 51 ). If the HOLD signal are asserted before 5 clock cycles elapse (YES at step S 51 ), the LSIs 3 to 7 consider that clock synchronization is not established and that the clock frequency changing operations are failed, the LSIs 3 to 7 notify, e.g., the OS of errors (step S 52 ). Note that the process at step S 51 , i.e., the process of confirming clock synchronization after the clock frequency changing operations are completed is not necessarily required.
  • each of the LSIs 3 to 7 changes the clock frequency 100 clock cycles after it is detected that the DOWN signal is deasserted (time t 1 in the example in FIG. 19) while confirming that the clock frequency changing operations are synchronized with each other at a predetermined timing.
  • FIG. 20 shows an example in which, because preparation for decreasing the clock frequency is not completed at least one of the LSIs 3 to 7 , the HOLD signals are asserted at time t 1 to perform the processes for changing the clock frequencies again.
  • Times t 1 ′, t 2 ′, and t 4 ′ in FIG. 20 correspond to time t 1 , t 2 , and t 4 in FIG. 19, respectively.
  • an operation obtained when a clock frequency is increased is as shown in FIGS. 16 to 18 .
  • the LSIs 3 to 7 detects that the DOWN signal and the HOLD signal on the clock control bus 2 are not asserted (YES at step S 53 in FIG. 16 )
  • the LSIs 3 to 7 start preparation for increasing the clock frequency (step S 54 ).
  • the preparation for increasing the clock frequency is to wait for completion of an operation (process) which may be erroneous by changing the clock frequency and not to newly start such an operation.
  • step S 54 a , S 55 the LSIs 3 to 7 determine whether preparation for increasing the clock frequency is completed or not (step S 56 ).
  • the LSIs 3 to 7 includes an LSI which does not complete the preparation for increasing the clock frequency (NO at step S 56 ), the LSI determines whether the clock frequency changing operation is aborted or delayed (step S 57 ). In this determination, conditions for determining whether a prediction period of time required to complete the preparation is longer than a predetermined period of time can be used.
  • an LSI which wants to delay a clock frequency changing operation asserts the HOLD signal and the DOWN signal for a delay period longer than the predetermined number of clock cycles T, e.g., 8 clock cycles as in a period from time t 1 to time t 2 in FIG. 22 (step S 59 ). Thereafter (i.e., after the HOLD signal and the DOWN signal is deasserted), the LSI returns to step S 31 to perform the process of changing the clock frequency again.
  • an LSI which completes preparation for increasing the clock frequency asserts the HOLD signal for the period T, e.g., 8 clock cycles as in a period from time t 1 to time t 2 in FIG. 21 (steps S 60 to S 63 ). More specifically, in the example in FIG. 21, the HOLD signal is asserted at time t 1 (step S 60 ), and is deasserted at time t 2 after 8 clock cycles (steps S 62 and S 63 ). In the meantime, the LSI which completes the preparation determines whether or not the DOWN signal is asserted by the LSI which completes the preparation (step S 61 ).
  • the LSI which completes the preparation determines whether both the HOLD signal and the DOWN signal are asserted for the period of 8 clock cycles, or a period longer than 8 clock cycles (step S 64 ). As in the example (times t 1 to t 2 ) in FIG. 23, both the HOLD signal and the DOWN signal are asserted for the period of 8 clock cycles (8 cycles of step S 65 ), it is considered that the LSI which does not complete the preparation requests a clock frequency changing operation to be aborted, and the process ends.
  • the LSIs 3 to 7 detect that the HOLD signal on the clock control bus 2 is deasserted (NO at step S 66 ), the LSIs 3 to 7 assert the DOWN signals simultaneously after a predetermined number of clock cycles, e.g., 80 clock cycles elapse (YES at step S 68 ) at time t 3 in FIG. 21 (step S 69 ).
  • a predetermined number of clock cycles e.g. 80 clock cycles elapse
  • the DOWN signal is asserted before the predetermined number of clock cycles elapse (i.e., before 80 clock cycles elapse) (step S 70 )
  • an LSI which early asserts the DOWN signal exists, and the clock frequency changing operations may not be synchronized with each other. For this reason, the clock frequency changing operation is aborted to end the operation (step S 67 ).
  • step S 69 When the LSIs 3 to 7 assert the DOWN signals simultaneously (step S 69 ), the LSIs 3 to 7 deassert the DOWN signals simultaneously after a predetermined number of clock cycles, e.g., 5 cycles at time t 4 in FIG. 21 (steps S 71 and S 73 ), and increase the values N of the frequency setting registers R in the clock generation circuits CG in the LSIs 3 to 7 by only 1 to change the clock frequency in such a direction that the clock frequency is increased by a predetermined amount (step S 74 ).
  • a predetermined number of clock cycles e.g., 5 cycles at time t 4 in FIG. 21
  • the LSIs 3 to 7 After the LSIs 3 to 7 change the clock frequency, the LSIs 3 to 7 assert the HOLD signals simultaneously after a predetermined number of clock cycles, e.g., 5 clock cycles elapse (YES at step S 76 in FIG. 18) to end the operation (step S 77 ). At this time, the LSIs 3 to 7 monitor the HOLD signal on the clock control bus 2 until 5 clock cycles elapse (step S 78 ). If the HOLD signal is asserted before 5 clock cycles elapse, the LSIs 3 to 7 consider that clock synchronization is not established and that the clock frequency changing operation is failed, the LSIs 3 to 7 notify the OS of an error to end the operation (step S 79 ). Note that the process at step S 78 , i.e., the process of confirming clock synchronization after the clock frequency changing operation is completed is not necessarily required.
  • the LSIs 3 to 7 change the clock frequency 85 clock cycles (time t 4 in the example in FIG. 21) after it is detected that the HOLD signal is deasserted (time t 2 in the example in FIG. 21) while confirming that the clock frequency changing operations are synchronized with each other at a predetermined timing.
  • FIG. 22 shows an example in which, because preparation for decreasing the clock frequency is not completed at least one of the LSIs 3 to 7 , the HOLD signal and the DOWN signal are asserted for a period which is longer than 8 clock cycles from time t 1 to time t 2 , and the process for changing the clock frequency is performed again after the period.
  • Times t 1 ′ to t 5 ′ in FIG. 22 correspond to times t 1 to t 5 in FIG. 21, respectively.
  • the LSIs 3 to 7 monitor the assert and deassert timings of the HOLD signal and the DOWN signal on the clock control bus 2 . If an LSI detects that the HOLD signal and the DOWN signal are asserted and deasserted at a timing different from that of own LSI, the LSI determines that the clock frequency changing operation is failed, and notifies of an error.
  • the second embodiment described above explains the case in which two types of signals, i.e., the HOLD signal and the DOWN signal on the clock control bus 2 are used.
  • an UP signal representing that a clock frequency must be increased may also be added.
  • the structure of the clock control bus 2 is complex to some extent, it can be apparently designated by only the UP signal that a clock signal must be increased. For this reason, control becomes simple.
  • the frequency of a clock generated by its own LSI can be dynamically changed by using at least a clock control bus in synchronism with another LSI.

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