US6552951B1 - Dual-port memory location - Google Patents

Dual-port memory location Download PDF

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Publication number
US6552951B1
US6552951B1 US09/806,299 US80629901A US6552951B1 US 6552951 B1 US6552951 B1 US 6552951B1 US 80629901 A US80629901 A US 80629901A US 6552951 B1 US6552951 B1 US 6552951B1
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United States
Prior art keywords
dual
memory cell
port memory
capacitive element
port
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Expired - Lifetime
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US09/806,299
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English (en)
Inventor
Kumar Jain Raj
Herbert Ehrentraut
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Infineon Technologies AG
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Infineon Technologies AG
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Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: RAJ, KUMAR JAIN, EHRENTRAUT, HERBERT
Priority to US10/065,212 priority Critical patent/US7333388B2/en
Priority to US10/065,213 priority patent/US6621752B2/en
Priority to US10/065,220 priority patent/US6853597B2/en
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Publication of US6552951B1 publication Critical patent/US6552951B1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Definitions

  • the invention relates to a dual-port memory cell in accordance with the preamble of claim 1, as disclosed in U.S. Pat. No. 5,010,519 or in U.S. Pat. No. 4,292,677.
  • the invention likewise relates to a DRAM semiconductor memory having dual-port memory cells.
  • Dual-port memory cells is a term designating all memory cells which have precisely two data lines
  • a dual-port memory cell designed as a static memory cell typically contains eight transistors, in each case four selection transistors (transfer gates) and four memory transistors (inverters). These transistors are each connected to two word lines (selection lines) and to two bit lines (data lines).
  • Dynamic dual-port memory cells dynamic random access memory; DRAM have not been known heretofore.
  • a further very important boundary condition which plays a very important part in particular for the semiconductor memory containing the memory cells, results from the requirement of the shortest possible access time to the individual memory cells of the semiconductor memory.
  • Shortening the effective access time is very important in particular in the case of the fundamentally very slow dynamic memories (DRAMs), access time to the individual memory cells of the semiconductor memory.
  • Shortening the effective access time is very important in particular in the case of the fundamentally very slow dynamic memories (DRAMs), in order not to give rise to an excessively large difference with regard to the clock rates of the processors used as standard nowadays.
  • the access time in a semiconductor memory essentially results from the propagation time of the data signals on the word lines and from the charge reversal of the storage capacitances.
  • the present invention is therefore based on the object of specifying a dynamic dual-port memory cell with a space-sating design.
  • the dual-port memory cell according to the invention in each case has a capacitive element designed as a memory transistor and two selection transistors, whose load paths are connected in series and this series circuit is arranged between two data lines.
  • This arrangement makes it possible for a dual-port memory cell to be read from and written to in parallel by two date processing units.
  • DRAM memory cells in particular on account of their comparatively small capacitances and short respective line lengths, are particularly advantageous in dynamic semiconductor memories since here the corresponding memory cells can be given very small dimensions.
  • each of the load path terminals of the CMOS transistor can be short-circuited with a respective load path terminal of the selection transistors. It is particularly advantageous here when the terminal nodes of the CMOS transistors coincide with the terminal nodes of the selection transistors.
  • the dual-port memory cell according to the invention manages with a very small area requirement, as a result of which dual-port DRAM memory cells can thus be fabricated particularly cost-effectively.
  • the saving of terminal nodes can also advantageously be realized with capacitive elements designed as capacitors.
  • both output paths of the capacitive element have a defined potential of approximately the same magnitude.
  • the memory cell according to the invention is, moreover, highly insensitive to noise.
  • the memory cell therefore exhibits a distinctly improved signal-to-noise ratio (SNR) in comparison with convention dual-port memory cells.
  • the smaller number of transistors and the short effective interconnect lengths additionally bring about very short access times.
  • the access time is additionally improved on account of in the reduced parasitic capacitances and resistances in the critical line path. As a result, it is possible to provide memory systems which have a higher performance for the same clock frequency.
  • the invention is particularly advantageously suitable for “multi-port semiconductor memories” having a multiplicity of dual-port DRAM memory cells according to the invention.
  • FIG. 1 shows the circuit diagram of a first exemplary embodiment of a dual-port memory cell according to the invention
  • FIG. 2 shows the circuit diagram of a second exemplary embodiment of a dual-port memory cell according to the invention
  • FIG. 3 shows an advantageous exemplary embodiment of a DRAM semiconductor memory having dual-port memory cells according to the invention.
  • FIG. 1 shows the circuit diagram of a first exemplary embodiment of a dual-port DRAM memory cell DPS according to the invention.
  • the memory cell DPS has two selection transistors AT 1 , AT 2 and also a capacitive element KE.
  • the capacitive element KE is designed as a CMOS memory transistor ST, whose gate terminal G is connected to a supply potential VDD.
  • the drain terminal D of the memory transistor ST is connected to a first data line B 1 via the load path of the first selection transistor AT 1 .
  • the source terminal S of the memory transistor ST is connected to a second data line B 2 via the load path of the second selection transistor AT 2 .
  • the load paths of the selection transistors AT 1 , AT 2 and of the memory transistor ST are thus connected in series and arranged between the first data line B 1 and the second data line B 2 .
  • the control terminals of the selection transistors AT 1 , AT 2 are connected to a respective word line WL 1 , WL 2 .
  • the corresponding selection transistors AT 1 , AT 2 are isolated and can be driven independently.
  • the memory cell DPS is connected via the data lines B 1 , B 2 to two data processing units connected downstream. These data processing units may be designed for example as a microcomputer, processor, logic circuit, bus, etc. Typically, but not necessarily, the data processing units are operated with different clock frequencies. Data can be written to and read from the, memory cell DPS, i.e. the memory transistor ST, bidirectionally and independently of one another via the data lines B 1 , B 2 . The corresponding selection transistors AT 1 , AT 2 car be controlled into the on state and into an off state via the word lines WL 1 , WL 2 .
  • FIG. 2 shows the circuit diagram of a second exemplary embodiment of a dual-port memory cell according to the invention.
  • the capacitive element KE has been realized by means of two storage capacitors SK 1 , SK 2 arranged in parallel.
  • the storage capacitors SK 1 , SK 2 are designed as DRAM capacitors whose first capacitor terminals (capacitor plates) are in each case connected to one another and in each case to a load path terminal of the selection transistors AT 1 , AT 2 .
  • a supply potential VREF is applied to the respective second capacitor terminals (in a “floating” manner). It is particularly advantageous if the first capacitor terminals coincide with the respective load path terminals of the assigned selection transistors AT 1 , AT 2 in order to ensure an area-optimized design.
  • a logic circuit or a state machine may be provided, which regularly recharges the stored data content of the memory cell DPS.
  • a logic circuit or state machine is referred to as a refresh circuit RS in the technical jargon.
  • this refresh circuit RS contains the second selection transistor AT 2 .
  • such a refresh circuit RS is provided only between the positive element KE and the second data line B 2 . It would also be conceivable, of course, additionally or alternatively to provide a (further) refresh circuit between the first data line B 1 and the capacitive element KE.
  • the refresh circuit RS can be formed by two sense amplifiers and a precharge circuit in a known manner. These two sense amplifiers and the precharge circuit could be part of the bit line decoder of the semiconductor memory.
  • an “autorefresh circuit” RS is provided, in the case of which the recharging of the memory cell DPS is automated.
  • the individual addresses of the different memory cells can be continually generated in ascending or descending order by means of a simple clocked ring counter, which memory cells are then recharged in the corresponding time intervals by the precharge circuit or by a reference voltage source.
  • FIG. 3 uses a simplified circuit diagram to show an advantageous exemplary embodiment of a DRAM semiconductor memory having dual-port memory cells according to the invention.
  • a selection transistor is in each case connected to a storage capacitor.
  • the particular advantage in the case of the memory cell according to the invention is that in each case two capacitors of the memory array SF, for example SK 0 , SK 1 , are internally short-circuited together. This produces dual-port memory cells DPS in a dual-port DRAM semiconductor memory.
  • the two ports are totally independent of one another in this case. It is particularly advantageous if the two ports are separated into a read/write port and a refresh port, which is only responsible for the refresh or recharging of the memory array SF.
  • the decoders for the read/write ports D RW-B , D RW-WL may be connected to the odd-numbered data/selection lines, while the decoders for the refresh ports D R-B , D R-WL may be connected to the even-numbered data/selection lines.
  • a dual-port DRAM semiconductor memory according to the invention which is configured in this way can even replace a medium-sized conventional SRAM semiconductor memory on a chip with embedded DRAM memory cells.
  • both the significantly higher storage density of a semiconductor memory configured as a DRAM in comparison with a 6-transistor memory cell of an SRAM semiconductor memory and the associated lower power loss are particularly advantageous.
  • the first selection transistor AT 1 is controlled into the on state.
  • the capacitive element K is thereby charged with the potential VDD ⁇ Vth if a digital “1” is to be written to the corresponding memory cell DPS, or is discharged to the potential VSS if, for example, a digital “0” is to be written to the corresponding memory cell DPS.
  • a dual-port memory cell DPS typically, at most one of the connected data processing units should be write-authorized during a write operation.
  • a simple logic circuit can be used to prevent the respective other data processing unit from being able to write simultaneously to the same memory cell DPS, Conversely, it is advantageously possible, however, that both data processing units connected to the dual-port memory cell can read data from this memory cell DPS.
  • the invention is particularly suitable in the case of memory cells fabricated using CMOS technology.
  • the memory, cells are not restricted to a specific transistor technology, but rather can be realized by any type of field-effect-controlled, normally on or normally off transistors, typically fabricated using MOS technology.
  • memory cells of bipolar design would also be conceivable.
  • FIG. 3 shows an advantageous exemplary embodiment of a dual-port semiconductor memory having dual-port memory cells according to the invention.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
US09/806,299 1998-09-30 1999-09-30 Dual-port memory location Expired - Lifetime US6552951B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/065,212 US7333388B2 (en) 2001-10-03 2002-09-26 Multi-port memory cells
US10/065,213 US6621752B2 (en) 2001-10-03 2002-09-26 Refreshing scheme for memory cells a memory array to increase performance of integrated circuits
US10/065,220 US6853597B2 (en) 2001-10-03 2002-09-26 Integrated circuits with parallel self-testing

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19845053 1998-09-30
DE19845053 1998-09-30
PCT/DE1999/003151 WO2000019437A2 (fr) 1998-09-30 1999-09-30 Cellule memoire a double acces

Related Parent Applications (3)

Application Number Title Priority Date Filing Date
US09/806,395 Continuation-In-Part US6560136B1 (en) 1998-09-30 1999-09-29 Single-port memory cell
PCT/DE1999/003151 Continuation-In-Part WO2000019437A2 (fr) 1998-09-30 1999-09-30 Cellule memoire a double acces
US09/615,987 Continuation-In-Part US6304478B1 (en) 1998-09-30 2000-07-14 Layout for a semiconductor memory

Related Child Applications (8)

Application Number Title Priority Date Filing Date
US09/855,163 Continuation-In-Part US6549451B2 (en) 1998-09-30 2001-05-14 Memory cell having reduced leakage current
US09/855,166 Continuation-In-Part US6510075B2 (en) 1998-09-30 2001-05-14 Memory cell with increased capacitance
US09/855,164 Continuation-In-Part US6545905B2 (en) 2000-07-14 2001-05-14 Multi-port memory cell with refresh port
US09/855,167 Continuation-In-Part US6469925B1 (en) 2000-07-14 2001-05-14 Memory cell with improved retention time
US10/131,364 Continuation-In-Part US6628541B2 (en) 2001-05-14 2002-04-24 Memory architecture with refresh and sense amplifiers
US10/065,220 Continuation-In-Part US6853597B2 (en) 2001-10-03 2002-09-26 Integrated circuits with parallel self-testing
US10/065,212 Continuation-In-Part US7333388B2 (en) 2001-10-03 2002-09-26 Multi-port memory cells
US10/065,213 Continuation-In-Part US6621752B2 (en) 2001-10-03 2002-09-26 Refreshing scheme for memory cells a memory array to increase performance of integrated circuits

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US6552951B1 true US6552951B1 (en) 2003-04-22

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US09/806,299 Expired - Lifetime US6552951B1 (en) 1998-09-30 1999-09-30 Dual-port memory location

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US (1) US6552951B1 (fr)
EP (1) EP1119859B1 (fr)
KR (1) KR100420827B1 (fr)
DE (1) DE59903684D1 (fr)
WO (1) WO2000019437A2 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030063515A1 (en) * 2001-10-03 2003-04-03 Raj Kumar Jain Multi-port memory cells
US20040174733A1 (en) * 2003-03-05 2004-09-09 International Business Machines Corporation Structure and System-on-Chip Integration of a Two-Transistor and Two-Capacitor Memory Cell for Trench Technology
US20050047254A1 (en) * 2003-08-27 2005-03-03 Ramnath Venkatraman Design and use of a spacer cell to support reconfigurable memories
US20050047238A1 (en) * 2003-09-03 2005-03-03 Ruggero Castagnetti Reconfigurable memory arrays
US20050102590A1 (en) * 2003-11-06 2005-05-12 International Business Machines Corporation Method for performing a burn-in test
US7002867B2 (en) 2002-09-25 2006-02-21 Infineon Technologies Aktiengesellschaft Refresh control circuit for ICs with a memory array
US20070159894A1 (en) * 2005-06-27 2007-07-12 Infineon Technologies Ag Memory cell, read device for memory cell, memory assembly, and corresponding method
US20170186750A1 (en) * 2015-12-29 2017-06-29 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device with reduced-resistance interconnect

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7120761B2 (en) 2000-12-20 2006-10-10 Fujitsu Limited Multi-port memory based on DRAM core
EP1564748B1 (fr) * 2000-12-20 2008-01-09 Fujitsu Limited Mémoire multiportes basée sur une DRAM
US7485525B2 (en) * 2006-01-10 2009-02-03 International Business Machines Corporation Method of manufacturing a multiple port memory having a plurality of parallel connected trench capacitors in a cell

Citations (8)

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US5007022A (en) 1987-12-21 1991-04-09 Texas Instruments Incorporated Two-port two-transistor DRAM
US5010519A (en) 1987-11-17 1991-04-23 Mitsubishi Denki Kabushiki Kaisha Dynamic semiconductor memory device formed by 2-transistor cells
US5327375A (en) 1988-07-08 1994-07-05 Eliyahou Harari DRAM cell utilizing novel capacitor
US5923593A (en) 1996-12-17 1999-07-13 Monolithic Systems, Inc. Multi-port DRAM cell and memory system using same
US6115019A (en) * 1998-02-25 2000-09-05 Agilent Technologies Register pixel for liquid crystal displays
US6246386B1 (en) * 1998-06-18 2001-06-12 Agilent Technologies, Inc. Integrated micro-display system
US6304478B1 (en) * 1998-09-30 2001-10-16 Infineon Technologies Ag Layout for a semiconductor memory
US20020006050A1 (en) * 2000-07-14 2002-01-17 Jain Raj Kumar Memory architecture with refresh and sense amplifiers

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JPH0369092A (ja) * 1989-05-16 1991-03-25 Mitsubishi Electric Corp ダイナミックｒａｍ用メモリセル回路
JPH0485798A (ja) * 1990-07-27 1992-03-18 Hitachi Ltd 半導体記憶装置
JPH04238193A (ja) * 1991-01-23 1992-08-26 Hitachi Ltd 半導体記憶装置
KR100198662B1 (ko) * 1996-05-16 1999-06-15 구본준 디램 셀, 디램 및 그의 제조 방법

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US5010519A (en) 1987-11-17 1991-04-23 Mitsubishi Denki Kabushiki Kaisha Dynamic semiconductor memory device formed by 2-transistor cells
US5007022A (en) 1987-12-21 1991-04-09 Texas Instruments Incorporated Two-port two-transistor DRAM
US5327375A (en) 1988-07-08 1994-07-05 Eliyahou Harari DRAM cell utilizing novel capacitor
US5327375B1 (en) 1988-07-08 1999-03-16 Eliyahou Harari Dram cellutilizing novel capacitor
US5923593A (en) 1996-12-17 1999-07-13 Monolithic Systems, Inc. Multi-port DRAM cell and memory system using same
US6115019A (en) * 1998-02-25 2000-09-05 Agilent Technologies Register pixel for liquid crystal displays
US6246386B1 (en) * 1998-06-18 2001-06-12 Agilent Technologies, Inc. Integrated micro-display system
US6304478B1 (en) * 1998-09-30 2001-10-16 Infineon Technologies Ag Layout for a semiconductor memory
US20020006050A1 (en) * 2000-07-14 2002-01-17 Jain Raj Kumar Memory architecture with refresh and sense amplifiers

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030063515A1 (en) * 2001-10-03 2003-04-03 Raj Kumar Jain Multi-port memory cells
US7333388B2 (en) 2001-10-03 2008-02-19 Infineon Technologies Aktiengesellschaft Multi-port memory cells
US7002867B2 (en) 2002-09-25 2006-02-21 Infineon Technologies Aktiengesellschaft Refresh control circuit for ICs with a memory array
US20040174733A1 (en) * 2003-03-05 2004-09-09 International Business Machines Corporation Structure and System-on-Chip Integration of a Two-Transistor and Two-Capacitor Memory Cell for Trench Technology
US6845033B2 (en) * 2003-03-05 2005-01-18 International Business Machines Corporation Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology
US20050047254A1 (en) * 2003-08-27 2005-03-03 Ramnath Venkatraman Design and use of a spacer cell to support reconfigurable memories
US7006369B2 (en) * 2003-08-27 2006-02-28 Lsi Logic Corporation Design and use of a spacer cell to support reconfigurable memories
US20050047238A1 (en) * 2003-09-03 2005-03-03 Ruggero Castagnetti Reconfigurable memory arrays
US6934174B2 (en) 2003-09-03 2005-08-23 Lsi Logic Corporation Reconfigurable memory arrays
US7243276B2 (en) * 2003-11-06 2007-07-10 International Business Machines Corporation Method for performing a burn-in test
US20050102590A1 (en) * 2003-11-06 2005-05-12 International Business Machines Corporation Method for performing a burn-in test
US7463548B2 (en) 2003-11-06 2008-12-09 International Business Machines Corporation Method for performing a burn-in test
US20070159894A1 (en) * 2005-06-27 2007-07-12 Infineon Technologies Ag Memory cell, read device for memory cell, memory assembly, and corresponding method
US7606107B2 (en) * 2005-06-27 2009-10-20 Infineon Technologies Ag Memory cell, read device for memory cell, memory assembly, and corresponding method
US20170186750A1 (en) * 2015-12-29 2017-06-29 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device with reduced-resistance interconnect
US10134737B2 (en) * 2015-12-29 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device with reduced-resistance interconnect
US10535658B2 (en) 2015-12-29 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device with reduced-resistance interconnect
US11145655B2 (en) 2015-12-29 2021-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device with reduced-resistance interconnect

Also Published As

Publication number Publication date
KR100420827B1 (ko) 2004-03-02
EP1119859B1 (fr) 2002-12-04
EP1119859A2 (fr) 2001-08-01
DE59903684D1 (de) 2003-01-16
WO2000019437A2 (fr) 2000-04-06
WO2000019437A3 (fr) 2000-05-25
KR20010099662A (ko) 2001-11-09

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