US6414959B1 - ATM network system - Google Patents

ATM network system Download PDF

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Publication number
US6414959B1
US6414959B1 US09/152,176 US15217698A US6414959B1 US 6414959 B1 US6414959 B1 US 6414959B1 US 15217698 A US15217698 A US 15217698A US 6414959 B1 US6414959 B1 US 6414959B1
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route
clock
nodes
failure
node
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Katsuhito Asano
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5619—Network Node Interface, e.g. tandem connections, transit switching
    • H04L2012/562—Routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5625—Operations, administration and maintenance [OAM]
    • H04L2012/5627—Fault tolerance and recovery
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5671—Support of voice
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H04L2012/5674—Synchronisation, timing recovery or alignment

Definitions

  • the present invention relates to an ATM (Asynchronous Transfer Mode) network system capable of determining a clock synchronization topology (clock supply route) required to transfer audio data and video data through an ATM network.
  • ATM Asynchronous Transfer Mode
  • ATM networks have been developed and are available in the market as transfer media of multimedia applications.
  • the various utilization needs are made of ATM networks.
  • LAN data are transferred via ATM networks, typically known as the Internet, but also the ATM network are used in application software of synchronization systems for audio data and video (picture) data.
  • clock synchronization must be established between terminals so as to transmit/receive data.
  • an ATM network is employed in order to repeat data in a synchronization system
  • this ATM network is required to establish a clock synchronization.
  • clock synchronization topology within the ATM network should be established, which can be hardly influenced by external factors such as a failure, or a defect.
  • this designer when an ATM network designer tries to design an ATM network, this designer sets a clock synchronization network of ATM switching units (i.e., nodes, will be referred to as “switching units” hereinafter) within this ATM network, and switching units clock synchronization sources every switching unit.
  • the ATM network designer presets such a switching unit that constitutes the clock synchronization source, and also determines a clock extracting port (namely, port used to receive clocks from other switching units) of the other respective switching units in such a manner that the clock synchronization topology may own exclusive intention.
  • the ATM network designer also presets clock extracting ports subsequent to a second priority order, assuming that a failure may occur in the clock supply routes of the respective switching units.
  • the clock may be extracted from another clock extracting port having a priority order subsequent to that of this clock extracting port under use.
  • the conventional ATM networks own the following problems. That is, as previously explained, the switching process operations of the clock extracting ports are carried out in the respective switching units. At this time, in such a case that a switching unit for executing the switching process operation is located in an upper stream of other switching units, the adverse influence is given to other switching units existing in a down stream.
  • FIG. 13 is an explanatory diagram for indicating the problem as to the clock synchronization network in the conventional ATM network.
  • this ATM network has the switching units (nodes) 1 to 6 .
  • the clock supply route (clock synchronization topology) having the first priority order, which is directed from the switching unit 1 to the switching unit 4 is set, whereas the clock supply route having the first priority order, which is directed from the switching unit 1 to the switching unit 5 , is set.
  • the clock supply route having the second priority order which is directed from the switching unit 4 to the switching unit 6
  • the clock supply route having the second priority order which is directed from the switching unit 5 to the switching unit 2 , is set.
  • the switching unit 3 While the clock supply route having the first priority order is used in this ATM network, when a failure happens to occur in the clock supply path connected between the switching unit 2 and the switching unit 3 , the switching unit 3 cannot receive the clock supplied from the switching unit 2 . As a result, the switching unit 3 switches the clock extracting port in accordance with the conditions set to the own switching unit 3 , so that the clock supply route is switched to the clock supply route having the second priority order, through which the clock is received from the switching unit 4 .
  • the switching unit 3 has no structure capable of transferring to the switching unit 4 and the switching unit 5 such a fact that the failure occurs in the clock supply path. As a consequence, even after the switching unit 3 is brought into such a condition that the clock is received from the switching unit 4 , this switching unit 4 maintains such a condition for receiving the clock from the switching unit 3 . On the other hand, since the switching unit 5 maintains the setting conditions before the failure happens to occur, the clock received from the switching unit 6 is not supplied to the switching unit 4 .
  • the clock loop is produced between the switching unit 3 and the switching unit 4 , and thus both the switching units 3 and 4 are disconnected from the clock synchronization network, so that these switching units 3 and 4 cannot be synchronized with other switching units 1 , 2 , 5 , and 6 .
  • An object of the present invention is to provide an ATM network system capable of avoiding such a problem that when a failure happens to occur in a clock supply route, a switching unit disconnected from a clock synchronization network will occur.
  • a first aspect of the present invention is featured by such an ATM network system having a clock synchronization source and a plurality of nodes synchronized with the clock synchronization source, and set a plurality of routes for supplying a clock from said synchronization source to each of said nodes.
  • each of the nodes when detecting a failure occurred in a presently used route, gives a failure signal to an other node to be supplied a clock from the node through a failure-detected route, and changes the failure-detected route into an other route.
  • Each of said nodes when received a failure signal from an other node, changes the failure-detected route into an other route in accordance with the failure signal.
  • this node when the node which has detected the failure of the clock supply route changes the route used by the node, this node supplies the failure signal to another node located in the down stream of the node in such a node where the failure occurs. Then, another node changes the route used by the node based upon the failure signal. As a result, even when the node which has detected the failure is brought into such a condition that since the route is changed by this node and no clock is supplied to another node, another node can receive the clock by changing the node. As a consequence, it can be prevent another node from being deviated from the clock synchronization network.
  • the node for instance, ATM transfer units such as an ATM switching unit, ATM-HUB, and an ATM router may be employed, which constitute an ATM network.
  • the clock synchronization source a node having a clock generating source, or a node for receiving a clock from a user terminal unit may be employed.
  • a second aspect of the present invention is featured by such a clock supply route determining method in an ATM network system in which said ATM network is constructed based on the private network-to-network interface specification (PNNI).
  • PNNI private network-to-network interface specification
  • a plurality of nodes for constituting the ATM network forms a pier group.
  • Each of nodes within the pier group owns data of shortest routes defined from the own node to each of other nodes. Any of the nodes within the pier group is set as a pier group leader, and this pier group leader is set as a clock synchronization source.
  • the pier group leader determines shortest routes defined from the pier group leader to other nodes based upon the data of the shortest routes as a clock supply route, and the respective nodes other than the pier group leader determine as clock supply routes, shortest routes defined from the nodes to the pier group leader based on the data of the shortest route.
  • the respective nodes belonging to the pier group acquire the topology data of the pier group, and then calculate the shortest routes based on this topology data. Since the clock supply routes are determined by the data of the shortest routes, the clock supply routes in the ATM network may be automatically determined.
  • FIG. 1 is a diagram showing an ATM network according to a embodiment 1 of the present invention
  • FIG. 2 is a table for indicating priority orders of clock supply routes of the respective switching units shown in FIG. 1;
  • FIG. 3 is a diagram showing the switching unit shown in FIG. 1;
  • FIG. 4 is a flow chart for describing a clock extracting port change process operation of the ATM network according to the embodiment 1;
  • FIG. 5 is a flow chart for describing a clock extracting port change process operation of the ATM network according to the embodiment 1;
  • FIG. 6 is a diagram showing a portion of an ATM network according to a embodiment 2 of the present invention.
  • FIG. 7 is a diagram showing the switching unit shown in FIG. 6;
  • FIG. 8 is a flow chart for describing a clock extracting port change process operation of the ATM network according to the embodiment 2;
  • FIG. 9 is a flow chart for describing a clock extracting port change process operation of the ATM network according to the embodiment 2;
  • FIG. 10 is a diagram showing an ATM network according to a embodiment 3 of the present invention.
  • FIG. 11 is a diagram showing a clock supply route determining method of the present invention.
  • FIG. 12 is a diagram showing a clock supply route determining method of the present invention.
  • FIG. 13 is an diagram showing the conventional ATM network.
  • FIG. 1 is a diagram showing an ATM network according to a embodiment 1 of the present invention.
  • the ATM network is equipped with 7 sets of ATM switching units (nodes) 11 to 17 .
  • Each of the switching units 11 to 17 is connected through a communication line to more than one set of user terminal unit (not shown in detail) containing a LAN (Local Area Network).
  • the ATM network may function as a repeating network of audio/video data communicated among terminals.
  • Each of the switching units 11 to 17 may function as a node (switching point) of a cell for storing thereinto audio/video data.
  • the respective switching units 11 to 17 transfer data at CBR (Constant Bit Rate).
  • CBR Constant Bit Rate
  • the respective switching units 11 to 17 are connected through paths 31 to 41 for supplying clocks with other switching units adjacent to the own switching unit. Then, 6 sets of clock supply routes (clock synchronization topology) “A” to “F” are set to the ATM network, while the switching unit 11 is used as a clock synchronization source. Also, connections 42 to 47 for identifying clock synchronization are set to this ATM network in correspondence with the respective clock supply routes “A” to “F”.
  • connection 42 passing through the clock supply route “A” defined from the switching unit 11 through the switching unit 12 and the switching unit 14 to the switching unit 16 is set, and the connection 43 passing through the clock supply route “B” defined from the switching unit 11 through the switching unit 13 , the switching unit 14 and the switching unit 16 to the switching unit 17 is set.
  • connection 44 passing through the clock supply route “C” defined from the switching unit 11 through the switching unit 13 to the switching unit 15 is set, and the connection 45 passing through the clock supply route “D” defined from the switching unit 11 through the switching unit 13 to the switching unit 15 is set.
  • connection 46 passing through the clock supply route “E” defined from the switching unit 11 through the switching unit 12 , the switching unit 14 , the switching unit 13 , and the switching unit 15 to the switching unit 16 is set, and the connection 47 passing through the clock supply route “F” defined from the switching unit 11 through the switching unit 12 to the switching unit 17 is set.
  • FIG. 2 is a memory table for representing priority orders of the clock supply routes “A” to “F” set to the respective switching unit 12 to 17 .
  • the respective switching units 12 to 17 change the clock supply routes “A” to “F” in accordance with the content of this table shown in FIG. 2 .
  • FIG. 3 is a diagram showing a example of the respective switching units 11 to 17 . It should be noted that since each of these switching units 11 to 17 owns the same structure, the switching unit 11 is represented as an example in FIG. 3 .
  • the switching unit 11 includes a control unit 20 , an input line managing unit 21 connected to the control unit 20 , an ATM-SW 22 , and an output line managing unit 23 .
  • a cell for storing audio/video data thereinto is inputted to the input line managing unit 21 .
  • the input line managing unit 21 terminates a connection; monitors a flow rate of a cell; converts a header of a cell; monitors performance; and assembles/disassembles a cell.
  • an OAM cell Operaation And Maintenance Cell
  • a storage content of this OAM cell is supplied to the control unit 20 by the input line managing unit 21 .
  • the ATM-SW 22 routes a cell entered from the input line managing unit 21 .
  • the output line managing unit 23 sends out the cell received from the ATM-SW 22 to a predetermined connection. Also, the output line managing unit 23 monitors the performance in response to an instruction issued from the control unit 20 to produce an OAM cell, if required, and then supplies this produced OAM cell to the connections 41 to 46 .
  • the switching unit 11 contains a memory table 24 for determining a clock extracting port, which is connected to the control unit 20 .
  • the table 24 is hold in a storage unit such as a semiconductor memory, a magnetic disk, and a magnetic optical disk.
  • the tale 24 stores thereinto connections for detecting OAM cells, and numbers of input ports and output ports after port change process operations have been performed in connection to these connections. This table 24 also stores flags as to failure conditions of the respective connections 42 to 47 .
  • the switching unit 11 contains a clock extracting port setting unit (will be referred to as a “port setting unit” hereinafter) 25 connected to the control unit 20 , and also a clock generating source 26 connected to the port setting unit 25 .
  • This port setting unit 25 is connected to a plurality of clock extracting ports (simply referred to as “ports” hereinafter) 27 .
  • the respective ports 27 are connected to paths 31 and 32 .
  • the port setting unit 25 sets any one of “input port for clock (clock extracting port)”, “output port for clock”, and “unused” with respect to each of the ports 27 .
  • the port setting unit 25 supplies a clock outputted from either the clock generating source 26 or the terminal (user terminal unit) T to respective structural unit of the switching unit, to output the clock from the output port. It should also be noted that since the switching units 12 to 17 are set to receive clocks from other switching units, the port setting unit 25 of the respective switching units 12 to 17 receives the clock entered from the input port and then supplies the received clock to the respective structural units employed in the switching units, and further outputs the clock from the output port toward other switching units.
  • the control unit 20 is mainly arranged by a CPU (central processing unit) and a memory, and controls the respective structural unit of the switching unit by executing a control program stored in this memory. For example, the control unit 20 monitors a failure occurred in a path connected to such a switching unit existing in an upper stream, and executes a clock extracting port changing process operation (will be discussed later), if necessary, in accordance with an OAM protocol.
  • the switching unit 11 outputs the clock which has received from either the clock generating source 26 or the terminal “T” from the respective ports 27 to the paths 31 and 32 .
  • the respective switching units 12 to 17 receive the clocks through the routes A, C, D and F, and then establish synchronization with each other so as to be operated.
  • the control unit 20 of the switching unit 13 specifies the routes where the failure happens to occur (in this case, routes B, C, and D)(S 2 ).
  • the control unit 20 of the switching unit 13 issues such an instruction that an OAM cell containing an AIS (Alarm Indication Signal) is sent out to the respective connections corresponding to the specified routes, and sets flags of the corresponding connections in the table 24 to “1” (S 3 ).
  • the output line managing unit 23 produces an OAM cell containing an AIS signal, and sends out the OAM cell to the respective connections 43 , 44 , and 45 corresponding to the routes B, C, and D.
  • the control unit 20 reads from the table 24 , the number of the clock extracting port corresponding to the relevant connection (S 4 ). At this time, the control unit 20 reads the number corresponding to the connection of the route where no failure happens to occur, namely the flag being “0” in accordance with the priority order shown in FIG. 2 . In this case, the number of the port 27 for storing the path 35 is read. Thereafter, the control unit 20 supplies a clock extracting port change instruction to the port setting unit 25 (S 5 ). As a result, the port setting unit 25 changes the clock extracting port from the port 27 for storing the path 32 into the port 27 for storing the path 35 .
  • the control unit 20 of each of the switching units 14 to 16 executes the clock extracting port change process operation shown in FIG. 5 .
  • the control unit 20 detects the AIS signal from the OAM cell entered into the input line managing unit 21 (S 01 )
  • the control unit 20 sets the flag of the table 24 to “1” as to the connection to which the OAM cell has been transferred, and thereafter reads out, from the table 24 , the port number corresponding to the connection to which this OAM cell has been transferred in a manner similar to that of the previous step S 4 (S 02 ).
  • control unit 20 supplies the read port number as a clock extracting port change instruction to the port setting unit 25 (S 03 ), and accomplishes the clock extracting port changing process operation. Thereafter, the port setting unit 25 changes the setting conditions of the respective ports 27 in accordance with the port number received from the control unit 20 .
  • the switching unit 14 sets the ports 27 for storing the respective paths 34 and 37 as the output ports
  • the switching unit 15 sets the port 27 for storing the path 39 as the output ports
  • the switching unit 16 changes the input port from the port 27 for storing the path 36 to the port 27 for storing the path 37 .
  • the following conditions are set. That is, the respective switching units 12 to 16 receive the clocks through the clock supply route E, and the switching unit 17 receives the clock through the clock supply route F.
  • the respective switching units 15 to 17 produce another OAM cell containing RDI (Remote Defect Indication) corresponding to AIS (Alarm Indication Signal), and transmit this OAM cell to the switching unit 11 .
  • RDI Remote Defect Indication
  • AIS Alarm Indication Signal
  • the present invention can prevent the switching unit from being disconnected from the clock synchronization network, which is caused when the clock loop occurs as in the conventional ATM network.
  • FIG. 6 is a diagram showing a portion of an ATM network according to an embodiment 2 of the present invention.
  • a switching unit 48 and another switching unit 49 which constitute a portion of the ATM network, are connected through a path for supplying a clock.
  • Two clock supply routes where the switching unit 48 is set in an upper stream are set to the respective switching units 48 and 49 , and connections A 1 and B 1 for identifying clock synchronizations of these routes are set thereto.
  • two clock supply routes where the switching unit 49 is set in an upper stream are set to the respective switching units 48 and 49 , and connections C 1 and D 1 for identifying clock synchronization of these routes are set thereto.
  • the switching unit 48 receives an AIS signal from the connection A 1 in such a case that the switching unit 48 receives a clock from another switching unit (not shown) through the route along the connection A 1 , and the switching unit 49 receives a clock from another switching unit (not shown) through the route along the connection D 1 .
  • the switching unit 48 is brought into such a condition that the clock is received through the route along the connection C 1 in accordance with a priority order given to the own switching unit 48 .
  • the switching unit 48 changes the clock extracting port in such a manner that the switching unit 48 extracts the clock from the switching unit 49 .
  • the switching unit 49 receives an AIS signal from the connection D 1 and is brought into such a condition that this switching unit 49 receives the clock through the route along the connection B 1 in accordance with the priority order given thereto, namely when the switching unit 49 changes the clock extracting port in such a way that the clock derived from the switching unit 48 is extracted, a clock loop is produced between the switching unit 48 and the switching unit 49 .
  • both the switching unit 48 and the switching unit 49 are deviated from the clock synchronization network.
  • a table 24 a for managing same directional connections is provided in each of the switching units 48 and 49 in addition to the arrangement as explained in the embodiment 1.
  • the table 24 a contains the number of connections as addresses and the number of same-directional connections as data, and further holds a flag as to whether or not a failure happens to occur in a connection (clock supply path).
  • the switching unit 48 receives an OAM cell containing an AIS signal from the connection A 1 in such a case that the switching unit 48 receives a clock from another switching unit (not shown) through the route along the connection A 1 , and the switching unit 49 receives a clock from another switching unit (not shown) through the route along the connection D 1 .
  • the control unit 20 of the switching unit 48 executes clock extracting port changing process operations indicated in FIG. 8 and FIG. 9 .
  • the control unit 20 detects the AIS signal from the OAM cell entered into the input line managing unit 21 (S 21 )
  • the control unit 20 reads the same-directional connection corresponding to such a connection (in this case, connection A 1 ) for transferring the OAM cell from the table 24 a based upon this AIS signal (S 22 ).
  • connection A 1 such a connection for transferring the OAM cell from the table 24 a based upon this AIS signal (S 22 ).
  • the same-directional connection of the connection A 1 the number of the connection B 1 is read out.
  • the control unit 20 refers to the flag in the table 24 a (S 23 ).
  • the control unit 20 sets the flag of the connection (connection A 1 ) from which the AIS signal is detected to “1” (S 201 ).
  • the control unit 20 judges as to whether or not all of the flags of the connections (in this case, connections C 1 and D 1 ) along the direction opposite to that of the above connection from which the AIS signal is detected are set to “1” (S 202 ).
  • step 202 when all of the flags are not equal to “1” (step 202 ; NO), the control unit 20 sets the flag of the connection (namely, connection B 1 ) in the same direction to that of the connection from which the AIS signal is detected to “1” (S 203 ), and the process operation is returned to the main routine shown in FIG. 8 .
  • the process operation is returned to the main routine of FIG. 8 .
  • control unit 20 executes the judgment defined at the step 202 , it is assumed that no failure occurs in the route of the clock supply paths in accordance with the connections C 1 and D 1 . In this case, since the flags of the connections C 1 and D 1 are equal to “1”, the control unit 20 sets the flag of the connection B 1 to “1”.
  • the control unit 20 issues to the output line managing unit 23 , such an instruction that the OAM cell containing the AIS signal is sent to the connection whose flag is set to “1” (S 24 ).
  • the output line managing unit 23 sends out the OAM cell to the relevant connection.
  • such a conditions are made that the OAM cell is transmitted to the connections A 1 and B 1 , and the quasi-failure happens to occur in the route of the clock supply path along the connection B 1 .
  • control unit 20 reads a port number corresponding to the connection A 1 from the table 24 (S 25 ). Subsequently, the control unit 20 supplies the read port number as the clock extracting port change instruction to the port setting unit 25 (S 26 ). As a result, the port setting unit 25 changes the clock extracting port in order to receive the clock through the route defined by the connection C 1 in accordance with the port number received from the control unit 20 . As a consequence, the switching unit 48 is brought into such a condition that this switching unit 48 receives the clock from the switching unit 49 .
  • the flags of the respective connections A 1 and B 1 in the table 24 a are set to “1”, and the setting condition of the respective ports 27 are changed in such a manner that the clock is given to the switching unit 48 through the route along the connection C 1 .
  • the control unit 20 of the switching unit 49 executes the clock extracting port change process operations shown in FIG. 8 and FIG. 9 . It should be understood that the control unit 20 of the switching unit 49 does not set the flag of the connection C 1 to “1” in a process operation defined at step S 202 shown in FIG. 9, taking account of such a fact that the flags of the respective connections A 1 and B 1 in the table 24 a are set to) “1”.
  • the operation condition thereof is transferred to such a condition that the clock is received through the route along the connection C 1 without being transferred to such a condition that the clock is received from the route along the connection D 1 to the route along the connection B 1 .
  • the switching unit 48 when the switching unit 48 receives the OAM cell containing the AIS signal from the connection A 1 , since the OAM cell is also sent to the connection B 1 which is the same-directional connection as the connection A 1 , the switching unit 49 recognizes that the failure also occurs in the route along the connection B 1 . Therefore, the switching unit 49 is brought into such a condition that the clock is detected through the route along the connection B 1 in response to the failure occurred in the route along the connection D 1 . Thus, it is possible to prevent the clock loop from being produced between the switching unit 48 and the switching unit 49 .
  • FIG. 10 is a diagram showing an ATM network according to an embodiment 3 of the present invention.
  • This ATM network corresponds to a private ATM network which is formed by using the PNNI (Private Network-to-Network Interface) specification defined in the ATM forum.
  • PNNI Primary Network-to-Network Interface
  • the ATM network according to the embodiment 3 is arranged based upon the recommendation by “The ATM Committee” Private Network-to-Network Specification Interface vol. 0” Mar. 1996”.
  • the ATM network is arranged by 5 sets of switching units 51 to 55 .
  • the respective switching units 51 to 55 are connected with the switching units adjacent to each other through any one of clock supply paths L 1 to L 7 .
  • Each of these paths L 1 to L 7 owns a metric (cost) caused by using its path.
  • Reference numerals indicated on the paths L 1 to L 7 of FIG. 10 represent metrics of the paths.
  • the switching units 51 to 55 constitute a group called as a “pier group”.
  • the “pier group” is equal to a group of nodes which contain the same topology databases, and exchange complete information related to link conditions with each other.
  • Each of the switching units 51 to 55 constitutes a so-called “lowest level node”.
  • any one of switching units belonging to a group is set as a pier group leader.
  • the switching unit 51 is set as the pier group leader, and the respective switching units 52 to 55 are set as group members. Then, the switching unit 51 constituting the pier group leader functions as a clock synchronization source, and supplies a clock to other switching units 52 to 55 .
  • the respective switching units 51 to 55 determines a clock supply route as follows: That is, the respective switching units 51 to 55 exchange a “PNNI HELLO” packet between the own switching unit and the switching unit adjacent to the own switching unit. As a result, the respective switching units 51 to 55 exchange the clock supply path for connecting the own switching unit with the switching unit adjacent to the own switching unit, namely exchange the information of the link (involving metric (cost) of the link).
  • each of switching units 51 to 55 transmits a message of “PTSE (PNNI Topology State Element)” containing all of the link information connected with the own switching unit to all of such switching units located adjacent to the own switching unit.
  • PTSE PNNI Topology State Element
  • the respective switching units 51 to 55 may finally acquire the link information related to all of the switching units belonging to the pier group. Then, each of these switching units 51 to 55 owns this link information as the topology database. As a consequence, the respective switching units 51 to 55 may grasp the topology of the ATM network.
  • the respective switching units 51 to 55 calculate routes (namely, the shortest routes) where the metrics on the links between the own switching units and other switching units by using the link information saved in the topology databases, and then stores thereinto the calculated shortest routes.
  • This shortest route calculation is performed for all of other switching units.
  • the switching units 51 sets such a clock supply route in accordance with the shortest route between the own switching unit and each of other switching units 52 to 56 .
  • the switching unit 51 may have a view (clock tree) indicated in FIG. 11 (A).
  • the switching unit 51 sets as a clock supply route “a”, such a route defined from the switching unit 51 through the switching unit 52 to the switching unit 54 , and also sets as another clock supply route “b”, such a route defined from the switching unit 51 through the switching unit 53 to the switching unit 55 .
  • the respective switching units 52 to 56 set the port of the shortest routes to the switching unit 51 as the clock extracting ports based upon the results of the shortest route calculating process operation.
  • the switching unit 55 may have a view shown in FIG. 11 (B), and sets a port for storing a path L 6 connected with the switching unit 53 as a clock extracting port, while using the switching unit 53 as the clock synchronization source.
  • the clock tree is automatically formed while setting the pier group leader as the clock synchronization source, and the clock extracting ports (namely, clock input ports) are set in such a manner that the respective group members can receive the clocks supplied from the pier group leader through the shortest routes.
  • PNNI recommends the manner for setting any one of the group members as another pier group leader in the case that a failure happens to occur in the present pier group leader.
  • the switching unit 55 may become the pier group leader, instead of the previous switching unit 51 .
  • the setting process operation in order that the switching unit 55 newly becomes the pier group leader is automatically carried out.
  • other switching units automatically perform the setting process operation in order that the switching unit 55 is handled as the pier group leader.
  • the switching unit 55 may newly become the clock synchronization source instead of the switching machine 51 .
  • the switching unit 55 sets the shortest routes to other switching machines as the clock supply route by using the result of the shortest route calculating process operation. That is, as shown in FIG. 12, the route defined from the switching unit 55 through the switching unit 53 to the switching unit 52 is set as a clock supply route “c”, whereas the route defined from the switching unit 55 to the switching unit 54 is set as a clock supplying route “d”.
  • the respective switching units 52 to 54 receive such a message that the failure occurs in the switching unit 51 , the setting conditions of the ports are changed in such a way that the ports of the shortest routes to the switching unit 55 become the clock extracting ports.
  • the clock supply route (namely, clock synchronization topology) within the pier group can be automatically set based upon the results of the shortest route determining process operations executed in the respective switching units 51 to 55 within the pier group.

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