US6215362B1 - Phase-locked loop (PLL) for radio-frequency (RF) signals - Google Patents

Phase-locked loop (PLL) for radio-frequency (RF) signals Download PDF

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Publication number
US6215362B1
US6215362B1 US09/327,011 US32701199A US6215362B1 US 6215362 B1 US6215362 B1 US 6215362B1 US 32701199 A US32701199 A US 32701199A US 6215362 B1 US6215362 B1 US 6215362B1
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Prior art keywords
phase
voltage
precharging
charge pump
locked loop
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Expired - Lifetime
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US09/327,011
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Shen Feng
Edmund Götz
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Siemens AG
Intel Corp
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Siemens AG
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Assigned to Intel Mobile Communications Technology GmbH reassignment Intel Mobile Communications Technology GmbH ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INFINEON TECHNOLOGIES AG
Assigned to Intel Mobile Communications GmbH reassignment Intel Mobile Communications GmbH ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: Intel Mobile Communications Technology GmbH
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Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTEL DEUTSCHLAND GMBH
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop

Definitions

  • phase-locked loops of this type generally have a voltage-controlled oscillator outputting a signal received by a loop mixer.
  • the loop mixer in turn outputs a signal received by a phase frequency detector (PFD).
  • PFD also receives a further input signal and outputs signals received by a charge pump.
  • the charge pump outputs signals controlling the voltage-controlled oscillator.
  • TDMA Time Division Multiple Access
  • GSM Global System for Mobile communications
  • PCN Time Division Multiple Access
  • PLL phase-locked loop
  • a phase-locked loop for radio-frequency signals including:
  • a loop mixer receiving and mixing the output signal from the voltage controlled oscillator with a local oscillator signal and outputting a mixed signal
  • phase-frequency detector receiving a reference signal and the mixed signal, and outputting charge pump signals
  • a charge pump circuit generating a control voltage and containing a charge pump receiving the charge pump signals from the phase-frequency detector and a precharge pump supplementing the charge pump, the precharge pump receiving and driven by logic control signals including a first logic control signal and a second logic control signal, the first logic control signal ensuring during precharging that the phase-locked loop is in a standby mode and that only the precharge pump is in an active mode, and, conversely, after the precharging the phase-locked loop is in an active mode and the precharge pump is in a standby mode, and the second logic control signal ensuring that the precharge pump applies the control voltage required for setting an initial state of the voltage-controlled oscillator to allow a fast lock-in of the voltage-controlled oscillator during a settling phase; and
  • a passive loop low-pass filter receiving the control voltage and outputting a filtered control voltage received by and controlling the voltage-control oscillator.
  • the PLLs configured according to the invention are advantageously constructed using integrated circuit (IC) technology.
  • FIG. 1 is a diagrammatic, block circuit diagram of a known PLL frequency synthesizer with a loop mixer (MPLL);
  • FIG. 2 is a block circuit diagram of a prior art upconversion modulation loop transmitter (UML-TX);
  • FIG. 3 is a graph of a timing diagram for software precharging in the case of the known circuits according to FIGS. 1 and 2;
  • FIG. 4 is a circuit block diagram of the PLL frequency synthesizer with the loop mixer (MPLL) and a precharge pump according to the invention
  • FIG. 5 is a graph of a timing diagram for the precharge pump of the circuit according to FIG. 4.
  • FIG. 6 is a circuit block diagram of the PLL frequency synthesizer with the loop mixer (MPLL) and the precharging configured in accordance with a variant of the invention.
  • FIGS. 1 and 2 there are shown two examples of known RF circuits.
  • the example shown in FIG. 1 is a PLL frequency synthesizer with a loop mixer (MPLL) 1
  • MPLL loop mixer
  • UML-TX upconversion modulation loop transmitter
  • the loop mixer 1 serves in both examples for downward mixing of an output frequency of a voltage-controlled oscillator (VCO) 2 . Undesired mixing products of the loop mixer 1 are suppressed by a passive low-pass filter 3 .
  • VCO voltage-controlled oscillator
  • the phase-locked loop has a phase-frequency detector (PFD) 4 which is fed, as one of two input signals, the reference signal having a frequency f R that is received by a frequency divider 5 with a divider ratio R/1.
  • PFD phase-frequency detector
  • VCO voltage-controlled oscillator
  • FX transmission frequency f TX
  • the output signal of the VCO 2 and is subjected to mixing in the loop mixer 1 with a frequency synthesizer signal or a local oscillator signal f LO and, in the case of FIG. 2, also to modulation in a quadrature modulator 7 and filtering in a passive bandpass filter 8 and has a frequency f IF (before frequency division).
  • the output signals, present at two outputs, of the phase-frequency detector 4 are fed to two inputs of a charge pump 9 .
  • the charge pump 9 has two current sources (source and sink) and from whose output there is supplied a control voltage V cp which is provided for controlling the voltage-controlled oscillator 2 and is further fed through a passive loop low-pass filter 10 .
  • the known PLLs of such type are mostly programmed with the aid of a bus, for example with a 3-line bus in their standby mode (only bus active). After programming, the control loops are switched from the standby mode into active mode. During the settling phase after being switched on, the PLL compels the voltage-controlled oscillator (VCO) 2 to follow the reference signal f R so that the phase angles and frequency positions of the two input signals at the phase-frequency detector 4 remain equal after lock-in is performed.
  • VCO voltage-controlled oscillator
  • VCO voltage-controlled oscillator
  • the initial condition mentioned above for a quick lock-in of the PLL can be fulfilled in the case of known PLL configurations by switching over a polarity of the phase-frequency detector (PFD) 4 .
  • Switching over the polarity is performed by software programming, for example by a 3-line bus.
  • the current source “source” in the charge pump 9 is switched on if a FN signal is in phase or in frequency with respect to a FR signal. With a negative polarity, the current source “sink” on the charge pump 9 is switched on. In order to fulfill the initial condition, the PLLs must be controlled as stated below.
  • VCO voltage-controlled oscillator
  • Vcc represents the DC supply voltage
  • Vcp the control voltage for the voltage-controlled oscillator (VCO)
  • gnd the ground potential
  • the PLL frequency synthesizer with the loop mixer (MPLL) 1 is again shown in FIG. 4 to represent a new precharging concept according to the invention for such PLLs.
  • the PLL corresponds in large measure to that shown in FIG. 1, so that it is possible at this juncture to dispense with an explanation of the corresponding parts.
  • FIG. 5 shows a simplified timing diagram of the precharge pump 12 without and with band changing (single-band and dual-band applications, respectively).
  • the control signals pcp and pd can be programmed with the aid of hardware or software. Owing to the elimination of the two separate programming operations with software, which are required in the case of the prior art solutions, the timing is not critical in this case for precharging.
  • the period t pcp is denoted as a precharging time.
  • Vcc represents the DC supply voltage
  • Vcp the control voltage for the voltage-controlled oscillator (VCO) 2
  • gnd the frame potential.
  • the precharging period can be shortened by optimizing the precharge pump 12 and the passive loop low-pass filter 10 . Since precharging takes place in the standby mode of the PLL, and can be implemented with simple circuits, the power consumption during precharging is substantially reduced.
  • the output voltage Vcp can be fixed after precharging, or the precharging polarity can be fixed after initialization (first programming after power-on), that is to say no additional programming of precharging is required before the active mode. It is thereby possible to reduce the on-time of the PLLs. However, it is necessary for the precharging current I PCP to be reduced so that the entire power consumption in standby mode is acceptable.
  • the precharging function can also be implemented with the available charge pump 9 of the PLLs, as is shown in the block diagram of FIG. 6 .
  • the alternatively configured, novel precharging concept according to the invention is likewise shown in FIG. 6 with the aid of a PLL frequency synthesizer with the loop mixer 1 (MPLL) for such PLLs.
  • MPLL loop mixer 1
  • the PLL corresponds in large measure to that represented in FIG. 1, with the result that it is possible at this juncture also to dispense with an explanation of the corresponding parts.
  • a specially configured charge pump device 14 with precharging function use is made of two 2:1 multiplexers (Mux) 15 and 16 upstream of the charge pump 9 so that the outputs of the phase-frequency detector (PFD) 4 are connected to the control signal pcp or to an inverted control signal pcp, which is inverted by inverter 17 , so that the charge pump 9 with the precharging function can remain in active mode in the standby mode of the PLLs.
  • Mux 2:1 multiplexers
  • the charge pump 9 of the PLLs is normally configured with more accurate and faster circuit techniques than the precharge pump 12 according to FIG. 4, the power consumption of the alternative concept according to FIG. 6 is higher during precharging than in the case of precharging according to the first-described configuration in accordance with FIG. 4 .

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
US09/327,011 1998-06-05 1999-06-07 Phase-locked loop (PLL) for radio-frequency (RF) signals Expired - Lifetime US6215362B1 (en)

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DE19825215 1998-06-05

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Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6411820B1 (en) * 1999-04-20 2002-06-25 Conexant Systems, Inc. Switchable phase lock loop for dual mode applications
US20020086652A1 (en) * 2000-12-28 2002-07-04 Taizo Yamawaki PLL circuit and wireless mobile station with that PLL circuit
US6466067B2 (en) * 2000-08-04 2002-10-15 Nec Corporation PLL circuit with shortened lock-up time
US6486650B1 (en) * 2000-09-27 2002-11-26 3Com Corporation Frequency locked loop speed up
WO2003041277A2 (fr) * 2001-11-06 2003-05-15 Renesas Technology Corp. Dispositif de communication a circuit integre a semi-conducteur et systeme de communication sans fil
US20030220087A1 (en) * 2002-05-27 2003-11-27 Nokia Corporation Circuit arrangement for phase locked loop, and phase locked loop based method to be used in cellular network terminals
US6658065B1 (en) * 2000-02-29 2003-12-02 Skyworks Solutions, Inc. System of and method for reducing or eliminating the unwanted sideband in the output of a transmitter comprising a quadrature modulator followed by a translational loop
GB2389255A (en) * 2002-05-31 2003-12-03 Hitachi Ltd Radio telecommunications system and method of building up output power
US20030224740A1 (en) * 2002-05-31 2003-12-04 Ryoichi Takano Transmitter and semiconductor integrated circuit for communication
US6693494B2 (en) * 2001-08-20 2004-02-17 Koninklijke Philips Electronics N.V. Frequency synthesizer with three mode loop filter charging
US6819186B2 (en) * 2000-04-03 2004-11-16 Siemens Aktiengesellschaft Electrical circuit arrangement, phase locked loop and method for operating an oscillator
US20050064828A1 (en) * 2003-07-31 2005-03-24 Noriyuki Kurakami Method of ramping up output level of power amplifier of radio communication system, communication semiconductor integrated circuit, and radio communication system
US7003274B1 (en) 2003-03-05 2006-02-21 Cisco Systems Wireless Networking (Australia) Pty Limited Frequency synthesizer and synthesis method for generating a multiband local oscillator signal
US7082290B2 (en) 2002-05-31 2006-07-25 Renesas Technology Corp. Communication semiconductor integrated circuit, a wireless communication apparatus, and a loop gain calibration method
US7084670B1 (en) * 2004-06-30 2006-08-01 National Semiconductor Corporation Phase-frequency detector with gated reference clock input
US7091759B2 (en) * 2004-06-01 2006-08-15 Skyworks Solutions, Inc. Loop filter integration in phase-locked loops
US20060258441A1 (en) * 2005-04-20 2006-11-16 Vitito Christopher J Vehicle entertainment system incorporated within the armrest/console of a vehicle
US7230997B2 (en) 2002-05-31 2007-06-12 Hitachi, Ltd. Semiconductor integrated circuit for communication, radio-communications apparatus, and transmission starting method
CN108616271A (zh) * 2016-12-12 2018-10-02 中国航空工业集团公司西安航空计算技术研究所 锁相环快速锁定电路

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Publication number Priority date Publication date Assignee Title
GB2361368B (en) * 2000-01-27 2003-09-10 Nec Technologies Frequency synthesiser

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US5164889A (en) 1991-10-10 1992-11-17 Samsung Semiconductor, Inc. Gate multiplexed low noise charge pump
US5220294A (en) 1990-05-21 1993-06-15 Nec Corporation Phase-locked loop circuit

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WO1993005578A1 (fr) * 1991-08-30 1993-03-18 Fujitsu Limited Synthetiseur de frequence
JP3256057B2 (ja) * 1993-12-21 2002-02-12 三菱電機株式会社 位相同期ループ回路装置およびその位相比較器
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US4562411A (en) 1983-12-29 1985-12-31 Rca Corporation Prepositioning circuit for phase lock loop
US5220294A (en) 1990-05-21 1993-06-15 Nec Corporation Phase-locked loop circuit
US5164889A (en) 1991-10-10 1992-11-17 Samsung Semiconductor, Inc. Gate multiplexed low noise charge pump

Cited By (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6411820B1 (en) * 1999-04-20 2002-06-25 Conexant Systems, Inc. Switchable phase lock loop for dual mode applications
US6658065B1 (en) * 2000-02-29 2003-12-02 Skyworks Solutions, Inc. System of and method for reducing or eliminating the unwanted sideband in the output of a transmitter comprising a quadrature modulator followed by a translational loop
US6819186B2 (en) * 2000-04-03 2004-11-16 Siemens Aktiengesellschaft Electrical circuit arrangement, phase locked loop and method for operating an oscillator
US6466067B2 (en) * 2000-08-04 2002-10-15 Nec Corporation PLL circuit with shortened lock-up time
US6486650B1 (en) * 2000-09-27 2002-11-26 3Com Corporation Frequency locked loop speed up
US20020086652A1 (en) * 2000-12-28 2002-07-04 Taizo Yamawaki PLL circuit and wireless mobile station with that PLL circuit
US6912380B2 (en) * 2000-12-28 2005-06-28 Renesas Technology Corp. PLL circuit and wireless mobile station with that PLL circuit
US6608510B2 (en) * 2000-12-28 2003-08-19 Hitachi, Ltd. PLL circuit and wireless mobile station with that PLL circuit
US6693494B2 (en) * 2001-08-20 2004-02-17 Koninklijke Philips Electronics N.V. Frequency synthesizer with three mode loop filter charging
WO2003041277A3 (fr) * 2001-11-06 2003-10-30 Hitachi Ltd Dispositif de communication a circuit integre a semi-conducteur et systeme de communication sans fil
US7386064B2 (en) * 2001-11-06 2008-06-10 Renesas Technology Corp. Communication semiconductor integrated circuit device and a wireless communication system
US20050068074A1 (en) * 2001-11-06 2005-03-31 Koichi Yahagi Communication semiconductor integrated circuit device and a wireless communication system
WO2003041277A2 (fr) * 2001-11-06 2003-05-15 Renesas Technology Corp. Dispositif de communication a circuit integre a semi-conducteur et systeme de communication sans fil
US7283801B2 (en) * 2002-05-27 2007-10-16 Nokia Corporation Circuit arrangement for phase locked loop, and phase locked loop based method to be used in cellular network terminals
US20030220087A1 (en) * 2002-05-27 2003-11-27 Nokia Corporation Circuit arrangement for phase locked loop, and phase locked loop based method to be used in cellular network terminals
US7082290B2 (en) 2002-05-31 2006-07-25 Renesas Technology Corp. Communication semiconductor integrated circuit, a wireless communication apparatus, and a loop gain calibration method
US7433653B2 (en) 2002-05-31 2008-10-07 Renesas Technology Corp. Transmitter and semiconductor integrated circuit for communication
GB2389255B (en) * 2002-05-31 2005-08-31 Hitachi Ltd Apparatus for radio telecommunication system and method of building up output power
US20070249297A1 (en) * 2002-05-31 2007-10-25 Ryoichi Takano Transmitter and semiconductor integrated circuit for communication
US20030224740A1 (en) * 2002-05-31 2003-12-04 Ryoichi Takano Transmitter and semiconductor integrated circuit for communication
US20030224743A1 (en) * 2002-05-31 2003-12-04 Kazuhisa Okada Apparatus for radio telecommunication system and method of building up output power
US7085544B2 (en) 2002-05-31 2006-08-01 Renesas Technology Corp. Transmitter having a phase control loop whose frequency bandwidth is varied in accordance with modulation modes
US20070201580A1 (en) * 2002-05-31 2007-08-30 Renesas Technology Corp., And Tttpcom Limited. Semiconductor integrated circuit for communication, radio-communication apparatus, and transmission starting method
US7480345B2 (en) 2002-05-31 2009-01-20 Renesas Technology Corp. Semiconductor integrated circuit for communication, radio-communication apparatus, and transmission starting method
US7366481B2 (en) 2002-05-31 2008-04-29 Renesas Technology Corporation Apparatus for radio telecommunication system and method of building up output power
US20060217081A1 (en) * 2002-05-31 2006-09-28 Ryoichi Takano Transmitter and semiconductor integrated circuit for communication
GB2389255A (en) * 2002-05-31 2003-12-03 Hitachi Ltd Radio telecommunications system and method of building up output power
US7209717B2 (en) 2002-05-31 2007-04-24 Renesas Technology Corporation Apparatus for radio telecommunication system and method of building up output power
US7230997B2 (en) 2002-05-31 2007-06-12 Hitachi, Ltd. Semiconductor integrated circuit for communication, radio-communications apparatus, and transmission starting method
US7248842B2 (en) 2002-05-31 2007-07-24 Renesas Technology Corp. Wireless communication apparatus having a phase control loop shared by first and second modulation modes and an amplitude control loop
US7515931B2 (en) 2003-03-05 2009-04-07 Cisco Technology, Inc. Frequency synthesizer and synthesis method for generating a multiband local oscillator signal
US20060094374A1 (en) * 2003-03-05 2006-05-04 Olip John A P Frequency synthesizer and synthesis method for generating a multiband local oscillator signal
US7003274B1 (en) 2003-03-05 2006-02-21 Cisco Systems Wireless Networking (Australia) Pty Limited Frequency synthesizer and synthesis method for generating a multiband local oscillator signal
US7324787B2 (en) * 2003-07-31 2008-01-29 Renesas Technology Corporation Method of ramping up output level of power amplifier of radio communication system, communication semiconductor integrated circuit, and radio communication system
US20050064828A1 (en) * 2003-07-31 2005-03-24 Noriyuki Kurakami Method of ramping up output level of power amplifier of radio communication system, communication semiconductor integrated circuit, and radio communication system
US7355463B2 (en) 2004-06-01 2008-04-08 Skyworks Solutions, Inc. Loop filter integration in phase-locked loops
US20060208778A1 (en) * 2004-06-01 2006-09-21 Tirdad Sowlati Loop filter integration in phase-locked loops
US7091759B2 (en) * 2004-06-01 2006-08-15 Skyworks Solutions, Inc. Loop filter integration in phase-locked loops
US7084670B1 (en) * 2004-06-30 2006-08-01 National Semiconductor Corporation Phase-frequency detector with gated reference clock input
US20060258441A1 (en) * 2005-04-20 2006-11-16 Vitito Christopher J Vehicle entertainment system incorporated within the armrest/console of a vehicle
CN108616271A (zh) * 2016-12-12 2018-10-02 中国航空工业集团公司西安航空计算技术研究所 锁相环快速锁定电路

Also Published As

Publication number Publication date
GB2338127B (en) 2001-11-21
GB9913096D0 (en) 1999-08-04
FR2787259A1 (fr) 2000-06-16
GB2338127A (en) 1999-12-08
FR2787259B1 (fr) 2004-07-09

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