US6169457B1 - Frequency synthesizer with a switched capacitor compensation circuit - Google Patents

Frequency synthesizer with a switched capacitor compensation circuit Download PDF

Info

Publication number
US6169457B1
US6169457B1 US09/170,458 US17045898A US6169457B1 US 6169457 B1 US6169457 B1 US 6169457B1 US 17045898 A US17045898 A US 17045898A US 6169457 B1 US6169457 B1 US 6169457B1
Authority
US
United States
Prior art keywords
frequency
signal
oscillator
aforementioned
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US09/170,458
Other languages
English (en)
Inventor
Kouzou Ichimaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ICHIMARU, KOUZOU
Application granted granted Critical
Publication of US6169457B1 publication Critical patent/US6169457B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Definitions

  • the invention pertains to the technical field of frequency synthesizers.
  • the invention pertains to a technology for ripple component compensation when the counter frequency division value is changed periodically.
  • the cellular phone is of the frequency multi-channel access type.
  • a frequency synthesizer which can lock on an available channel at high speed.
  • 101 represents an example of the frequency synthesizer of the prior art using the PLL circuit technology of the fractional frequency division method. It is arranged inside the semiconductor device that forms a transceiver of the cellular phone.
  • This frequency synthesizer 101 contains the following parts: oscillator 131 , frequency divider 132 , reference clock signal generator 133 , phase comparator 134 , charge pump circuit 135 , and low-pass filter 136 .
  • Said oscillator 131 has a configuration that outputs external signal OUT to the other circuit in the semiconductor device having frequency divider 132 and frequency synthesizer 101 .
  • Frequency divider 132 divides input external output signal OUT and generates a comparative signal.
  • a comparative signal from frequency divider 132 and a reference clock signal output from reference clock generator 133 are input to phase comparator 134 ; the phase of the signals is read. The result is used as a control signal which is output through charge pump circuit 135 and low-pass filter 136 to oscillator 131 .
  • the frequency of external output signal OUT is changed such that the comparative signal and the reference clock signal are in phase.
  • the frequency of external output signal OUT becomes a value equal to the frequency of the reference clock signal times the division value of frequency divider 132 .
  • the inter-channel distance is 25 kHz, 12.5 kHz, etc. Consequently, it is necessary to form external output signal OUT with narrow channel intervals, such as 800.025 MHz, 800.050 MHz, etc.
  • the reference clock signal in order to increase the response speed, the reference clock signal must be a high frequency signal. Consequently, the frequency division value of frequency divider 132 is changed periodically, an average frequency division value having a fraction value is generated, and the high-frequency reference clock signal is multiplied by the average frequency division value, so that external output signal OUT having the desired frequency is obtained.
  • phase comparator 134 a control signal indicating the phase difference between the comparative signal and the reference clock signal becomes a ripple current and is output through a charge pump circuit.
  • (a) represents the waveform of the comparative signal output from frequency divider 132 in the case of frequency division of external output signal OUT to frequency division value N and frequency division value N+1.
  • (b) represents the reference clock signal. Since it is not in agreement with the phase of comparative signal (a), ripple current c is superimposed-on the control signal output from charge pump circuit 135 .
  • Such ripple current c not only degrades the receiving characteristics of the cellular phone or other communication device, but also acts as an interference component in transmission. Consequently, it becomes a serious problem.
  • compensation circuit 140 made up of a charge pump circuit is arranged in frequency synthesizer 102 shown in FIG. 8 .
  • compensation current having a polarity opposite to ripple current c is generated, ripple current c is cancelled by compensation current d, and the phase of external output signal OUT is locked. In this state, the signal that changes the frequency of external output signal OUT is not input to oscillator 131 .
  • compensation current d is output with a certain delay with respect to ripple current c. Also, the output time of compensation current d becomes longer than the output time of ripple current c. This is a disadvantage. For example, while the duration of output of ripple current c is as short as several hundred psec, the duration of compensation time d is several hundred nsec. Consequently, when ripple current c has a current value of a few mA, in order to provide the same charge amount but with opposite polarity, the current value of compensation current d becomes as small as a few ⁇ A, and it is impossible to perform the cancellation correctly. Consequently, it is difficult to eliminate the influence of ripple current c on conventional compensation circuit 140 .
  • FIG. 9 is a graph illustrating the relationship between the frequency component and optical intensity of output signal OUT of said frequency synthesizer 102 .
  • the abscissa represents intensity, and the ordinate frequency.
  • the reference clock signal has a frequency of 240 kHz, and the average frequency division value is 4,000+1 ⁇ 8.
  • a spurious component is observed at a prescribed frequency interval. Such spurious components cause deterioration in the transceiving characteristics, and it is preferred that such spurious components be eliminated.
  • the purpose of the invention is to solve the aforementioned problems of the conventional technology by providing a type of frequency synthesizer which has no spurious components in the output signal, and which has excellent characteristics.
  • the invention described in claim 1 provides a type of frequency synthesizer that contains an oscillator which outputs an output signal to the outside, a frequency divider which divides the external output signal output from the aforementioned oscillator so that its frequency division value is in periodic variation to generate a comparative signal, a phase comparator which compares the phase of the aforementioned comparative signal with the phase of a reference clock signal, and controls the aforementioned oscillator such that the aforementioned external output signal has a frequency that equals the frequency of the aforementioned reference clock signal times the average frequency division value of the aforementioned frequency division values, a capacitor with one end connected to the transmission path of the signal that controls the aforementioned oscillator, and a voltage controller connected to the other end of the aforementioned capacitor.
  • the aforementioned voltage controller can apply 2 or more voltages to the other end of each of the aforementioned capacitors.
  • the aforementioned voltage controller of the frequency synthesizer described in claim 2 has two or more power sources and plural switch circuits that output different voltages; the aforementioned capacitors are connected to two or more of the aforementioned power sources through the aforementioned switching circuits, respectively; and, by operating the aforementioned switching circuits, it is possible to switch the power source connected to the desired capacitor.
  • the aforementioned voltage controller is made up of a digital/analog converter so conFIG.d that the desired voltage can be applied to the aforementioned capacitor.
  • the frequency synthesizer of the invention having the aforementioned configuration has an oscillator, a frequency divider, and a phase comparator.
  • the frequency divider makes the frequency division value change periodically, and divides the external output signal output from the oscillator to generate a comparative signal.
  • the phase comparator compares the phase of the comparative signal with the phase of the reference clock signal, and it controls the oscillator such that the external output signal has a frequency equal to the frequency of the reference clock signal times the average frequency division value.
  • a capacitor and a voltage controller are used in this frequency synthesizer.
  • One end of the capacitor is connected to the transmission path of the signal that controls the oscillator, and the other end is connected to the voltage controller.
  • the charge amount of the ripple current is an integral multiple of the minimum charge amount. Consequently, plural capacitors are set, and, by means of a voltage controller, at least two voltages can be applied to the other end of each capacitor by means of the voltage controller. By switching the voltage of each capacitor, it is possible to generate the compensation current with the minimum charge amount. In this way, it is possible to cancel the ripple current correctly with a charge amount an integral multiple of the minimum charge amount.
  • two or more power sources that can output different voltages and plural switch circuits are arranged in the voltage control circuit.
  • the capacitors are connected through the switching circuits to two more more respective power sources.
  • the voltage controller is made up of a digital/analog converter, and it can apply the desired voltage to the capacitor.
  • the amount of change to the output voltage of the digital/analog converter it is possible to generate the compensating current having the desired charge amount.
  • one capacitor may be sufficient for the operation.
  • FIG. 1 is a block diagram illustrating an example of the frequency synthesizer of the invention.
  • FIG. 2 is a diagram illustrating the compensation circuit of the frequency synthesizer.
  • FIG. 3 is a block diagram illustrating a portion of another example of the frequency synthesizer of the invention.
  • FIG. 4 is a graph illustrating the operation of the compensation circuit of the frequency synthesizer.
  • FIG. 5 is a timing diagram illustrating the ripple current and the compensation current in the frequency synthesizer of the invention.
  • FIG. 6 is a block diagram illustrating the frequency synthesizer of the prior art.
  • FIG. 7 is a timing diagram illustrating the operation of phase comparator of the frequency synthesizer.
  • FIG. 8 is a block diagram illustrating a frequency sythesizer of the prior art having a compensation circuit.
  • FIG. 9 is a graph illustrating the relationship between the frequency component and the output intensity of the frequency sythesizer.
  • 2 represents an example of the frequency synthesizer of the invention. It is installed inside a semiconductor device.
  • Said frequency synthesizer 2 has oscillator 31 , frequency divider 32 , reference clock signal 33 , phase comparator 34 , charge pump circuit 35 , low-pass filter 36 , controller 38 , and compensation circuit 10 .
  • the external output signal OUT output from oscillator 31 is sent to the other circuits in the semiconductor circuit, and it is also output to frequency divider 32 .
  • Said frequency divider 32 has a configuration which enables control by controller 38 and has the frequency division value change periodically. External output signal OUT that is input is divided by the frequency division value to generate a comparative signal at a lower frequency.
  • Reference clock signal generator 33 generates the reference clock signal at the prescribed frequency, and the reference clock signal and the comparative signal are input to phase comparator 34 .
  • Phase comparator 34 compares the phases of the two signals, and outputs the comparison result as a control signal to charge pump circuit 35 .
  • Charge pump circuit 35 converts the control signal input from phase comparator 34 to a current (charge), and outputs it through low-pass filter 36 to oscillator 31 .
  • Oscillator 31 follows the input control signal to change the frequency of external output signal OUT. As a result, the frequency of external output signal OUT is locked to the value equal to frequency of the reference clock signal times the average frequency division value.
  • the frequency division value of frequency divider 32 has an average frequency division value of N+1 ⁇ 8.
  • the reference clock signal is 200 kHz and said N is 5,000, external output signal OUT becomes a frequency of 1,000,025 kHz.
  • the ripple current is contained in the control signal output from phase comparator 34 .
  • the output stage of said charge pump circuit 35 is made up of switch 44 and two constant-current circuits 41 and 42 .
  • Switch 44 is controlled by the control signal input from phase comparator 34 .
  • the charge calculated by multiplying the phase difference of the output current of constant-current circuits 41 and 42 (phase difference x constant current) is supplied or removed, so that the control signal is converted into charge. Consequently, the control signal input to oscillator 31 contains the charge ripple (current).
  • low-pass filter 36 is made up of two capacitors and one resistor, and the capacitance of capacitor 361 is less than the capacitance of capacitor 362 .
  • the ripple charge generated becomes a charge amount in the range from a minimum value of ⁇ tilde over (n) ⁇ 0.5 times Qr 0.5 Qr) to a maximum value of ⁇ tilde over (n) ⁇ 3.5 times Qr (3.5 Qr) with interval of (1.0 Qr).
  • the generation period is identical to the frequency of the reference clock signal, and it is repeatedly generated in the following order:
  • compensation circuit 10 is connected to the output terminal side of charge pump circuit 35 .
  • controller 38 the capacitor in compensating circuit 10 charges/discharges, so that a compensation current having charge polarity opposite to that of the ripple current and having charge amount equal to that of the ripple current is generated.
  • Said compensation circuit 10 has plural capacitors 11 (here, three capacitors 111 - 113 are shown) and voltage controller 12 .
  • switch circuits 13 in equal number to the capacitors (here, three switch circuits 131 - 133 are shown) and two power sources 14 and 15 that output different voltages are arranged. One end of each capacitor 11 is connected to the output terminal of charge pump circuit 35 , and the other end is connected through switch circuit 13 to power source 14 or 15 .
  • each capacitor 11 is connected to one of two power sources 14 and 15 beforehand.
  • the connection state can be switched for the desired switch circuits, so that connection is switched to the other power source of said two power sources 14 and 15 .
  • the compensation charge for each capacitor 11 is ⁇ C 0 ⁇ V d .
  • 16 capacitors 11 are used. First all capacitors 11 are connected to power source 15 . For generation of ripple charge of +3.5 Q r , +2.5 Q r , +1.5 Q r , +0.5 Q r connection of 7, 5, 3, and 1 capacitor 11 is switched to power source 14 synchrononsly, so that a negative compensating charge is generated to cancel the positive ripple charge.
  • connection of 1, 3, 5, and 7 capacitor 11 is switched from power source 14 to power source 15 synchrononsly, so that a positive compensation charge is generated to cancel the negative ripple charge.
  • the switching number of capacitors 11 can be represented as
  • 3 represents the frequency synthesizer in an example of the invention.
  • Compensation circuit 10 of said frequency synthesizer 2 is changed to a different compensation circuit 20 .
  • the other structural features of said frequency synthesizer 3 are identical to those of said frequency synthesizer 2 . Consequently, explanation of the overall operation is omitted.
  • Compensation circuit 20 in. FIG. 3 functions together with low-pass filter 36 .
  • D/A converter 24 and two resistors 22 and 23 are added.
  • One end of capacitor 361 of low-pass filter 36 is connected to the output terminal of charge pump circuit 35 , and the other end is connected through resistor 22 to the output terminal of D/A comparator 24 .
  • D/A converter 24 is controlled by controller 38 .
  • the digital signal input from controller 38 is converted into an analog voltage signal, and the voltage is applied to capacitor 361 via resistor 22 .
  • resistor 23 which has one end grounded, is connected to the node between capacitor 361 and resistor 22 .
  • capacitor 361 is C 1 and the resistances of resistors 22 and 23 are R 22 and R 23 , respectively, when the output voltage of D/A converter 24 is changed by V e , a compensation current with charge of
  • C 1 , R 22 , R 23 , and V e are set such that
  • the output voltage of D/A comparator 24 is changed in the order of ⁇ 7 V e , ⁇ 5 V e , ⁇ 3 V e , ⁇ 1 V e , +1 V e , +3 V e , +5 V e , +7 V e .
  • compensation circuit 20 it is also possible to connect the output of DIA comparator 24 directly to the output stage of charge pump circuit 35 through capacitor 361 without using resistors 22 and 23 .
  • compensation current D with the same charge amount and the opposite polarity can be generated and overlapped on the control signal output from charge pump circuit 35 .

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
US09/170,458 1997-10-16 1998-10-13 Frequency synthesizer with a switched capacitor compensation circuit Expired - Lifetime US6169457B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP29948297A JP3923150B2 (ja) 1997-10-16 1997-10-16 周波数シンセサイザ
JP9-299482 1997-10-16

Publications (1)

Publication Number Publication Date
US6169457B1 true US6169457B1 (en) 2001-01-02

Family

ID=17873150

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/170,458 Expired - Lifetime US6169457B1 (en) 1997-10-16 1998-10-13 Frequency synthesizer with a switched capacitor compensation circuit

Country Status (3)

Country Link
US (1) US6169457B1 (ja)
EP (1) EP0910171A1 (ja)
JP (1) JP3923150B2 (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278331B1 (en) * 1999-03-30 2001-08-21 Infineon Technologies Ag System and method for compensating wafer parameters
US6593783B2 (en) 2000-02-02 2003-07-15 Texas Instruments Incorporated Compensation circuit for fractional-N frequency PLL synthesizer
US6891412B1 (en) * 2002-12-16 2005-05-10 Analog Devices, Inc. Low noise filter
US7174143B1 (en) * 2003-01-21 2007-02-06 Analog Devices, Inc. Receiver circuit with transmission loss compensation
US8193845B2 (en) 2010-07-06 2012-06-05 Microchip Technology Incorporated Binary-weighted delta-sigma fractional-N frequency synthesizer with digital-to-analog differentiators canceling quantization noise
WO2015039079A3 (en) * 2013-09-16 2015-05-21 Arctic Sand Technologies, Inc. Partial adiabatic conversion
US11901817B2 (en) 2013-03-15 2024-02-13 Psemi Corporation Protection of switched capacitor power converter

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4392949B2 (ja) 2000-04-05 2010-01-06 日本テキサス・インスツルメンツ株式会社 周波数シンセサイザ
GB0129717D0 (en) * 2001-12-12 2002-01-30 Marconi Comm Ltd A method and an apparatus for signal transmission

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB429217A (en) 1934-03-21 1935-05-27 Gen Electric Co Ltd Improvements in or relating to radio receiving sets
US4204174A (en) 1978-07-22 1980-05-20 Racal Communications Equipment Limited Phase locked loop variable frequency generator
US5021749A (en) * 1988-05-11 1991-06-04 Seiko Epson Corporation Switchable capacitor loop filter for phase locked loop
US5166642A (en) 1992-02-18 1992-11-24 Motorola, Inc. Multiple accumulator fractional N synthesis with series recombination
US5343169A (en) * 1992-03-31 1994-08-30 Sgs-Thomson Microelectronics S.A. Frequency locked loop
US5495206A (en) 1993-10-29 1996-02-27 Motorola, Inc. Fractional N frequency synthesis with residual error correction and method thereof
US5793257A (en) * 1996-06-28 1998-08-11 Fujitsu Limited Oscillator having switching capacitors and phase-locked loop employing same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2238434B (en) * 1989-11-22 1994-03-16 Stc Plc Frequency synthesiser

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB429217A (en) 1934-03-21 1935-05-27 Gen Electric Co Ltd Improvements in or relating to radio receiving sets
US4204174A (en) 1978-07-22 1980-05-20 Racal Communications Equipment Limited Phase locked loop variable frequency generator
US5021749A (en) * 1988-05-11 1991-06-04 Seiko Epson Corporation Switchable capacitor loop filter for phase locked loop
US5166642A (en) 1992-02-18 1992-11-24 Motorola, Inc. Multiple accumulator fractional N synthesis with series recombination
US5343169A (en) * 1992-03-31 1994-08-30 Sgs-Thomson Microelectronics S.A. Frequency locked loop
US5495206A (en) 1993-10-29 1996-02-27 Motorola, Inc. Fractional N frequency synthesis with residual error correction and method thereof
US5793257A (en) * 1996-06-28 1998-08-11 Fujitsu Limited Oscillator having switching capacitors and phase-locked loop employing same

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278331B1 (en) * 1999-03-30 2001-08-21 Infineon Technologies Ag System and method for compensating wafer parameters
US6632687B2 (en) 1999-03-30 2003-10-14 Infineon Technologies Ag Methods of compensating for wafer parameters
US6593783B2 (en) 2000-02-02 2003-07-15 Texas Instruments Incorporated Compensation circuit for fractional-N frequency PLL synthesizer
US6891412B1 (en) * 2002-12-16 2005-05-10 Analog Devices, Inc. Low noise filter
US7174143B1 (en) * 2003-01-21 2007-02-06 Analog Devices, Inc. Receiver circuit with transmission loss compensation
US8193845B2 (en) 2010-07-06 2012-06-05 Microchip Technology Incorporated Binary-weighted delta-sigma fractional-N frequency synthesizer with digital-to-analog differentiators canceling quantization noise
US11901817B2 (en) 2013-03-15 2024-02-13 Psemi Corporation Protection of switched capacitor power converter
CN105723599A (zh) * 2013-09-16 2016-06-29 北极砂技术有限公司 局部绝热转换
US9041459B2 (en) 2013-09-16 2015-05-26 Arctic Sand Technologies, Inc. Partial adiabatic conversion
GB2534716A (en) * 2013-09-16 2016-08-03 Arctic Sand Technologies Inc Partial adiabatic conversion
US9658635B2 (en) 2013-09-16 2017-05-23 Arctic Sand Technologies, Inc. Charge pump with temporally-varying adiabaticity
US10162376B2 (en) 2013-09-16 2018-12-25 Psemi Corporation Charge pump with temporally-varying adiabaticity
CN105723599B (zh) * 2013-09-16 2019-12-10 北极砂技术有限公司 局部绝热转换
GB2534716B (en) * 2013-09-16 2021-07-07 Arctic Sand Technologies Inc Partial adiabatic conversion
USRE49449E1 (en) 2013-09-16 2023-03-07 Psemi Corporation Charge pump with temporally-varying adiabaticity
WO2015039079A3 (en) * 2013-09-16 2015-05-21 Arctic Sand Technologies, Inc. Partial adiabatic conversion

Also Published As

Publication number Publication date
EP0910171A1 (en) 1999-04-21
JP3923150B2 (ja) 2007-05-30
JPH11122106A (ja) 1999-04-30

Similar Documents

Publication Publication Date Title
EP0360442B1 (en) Frequency sythesizer
KR100361855B1 (ko) 주파수합성기
KR101077745B1 (ko) 스펙트럼 확산 클록 발생 회로, 지터 발생 회로 및 반도체장치
EP1689088B1 (en) Spread spectrum clock generation circuit and a method of controlling thereof
GB2431531A (en) Triangle waveform generator for a PWM amplifier
CN1253673A (zh) 带有抖动补偿的分数n分频的频率综合器
US11128256B2 (en) Oscillator circuit
US6169457B1 (en) Frequency synthesizer with a switched capacitor compensation circuit
US7498888B2 (en) Method and arrangement for interference compensation in a voltage-controlled frequency generator
EP0461358A1 (en) Frequency synthesizer
US6593783B2 (en) Compensation circuit for fractional-N frequency PLL synthesizer
KR20040007473A (ko) 분수 보상방법을 갖는 분수분주 주파수 합성기
JP4357674B2 (ja) 周波数シンセサイザ
US6766154B2 (en) Fast settling fine stepping phase locked loops
JP3895028B2 (ja) 周波数シンセサイザ
KR20050007821A (ko) 적응적 가변 대역폭을 갖는 위상 동기 루프 회로
US20030076177A1 (en) Phase locked loop with charge injection cancellation
KR100343078B1 (ko) 주파수신세사이저
JP2001292061A (ja) 周波数シンセサイザ
AU705852B2 (en) Clock and data regenerator for gigabit signals
JP3901810B2 (ja) 補正回路付き周波数シンセサイザ
JPS5926124B2 (ja) 位相同期回路
KR0136944B1 (ko) 카운터를 이용한 자동 필터 튜닝 시스템
JPH0267822A (ja) 周波数シンセサイザ
JP4198833B2 (ja) 周波数シンセサイザ、リップルを補償する方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ICHIMARU, KOUZOU;REEL/FRAME:009687/0841

Effective date: 19981208

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12