US5933452A - Timing interpolator in digital demodulator - Google Patents

Timing interpolator in digital demodulator Download PDF

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Publication number
US5933452A
US5933452A US08/916,203 US91620397A US5933452A US 5933452 A US5933452 A US 5933452A US 91620397 A US91620397 A US 91620397A US 5933452 A US5933452 A US 5933452A
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tap
coefficients
coefficient
filter
sine function
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Myung-Su Eun
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Quarterhill Inc
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Daewoo Electronics Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0628—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing the input and output signals being derived from two separate clocks, i.e. asynchronous sample rate conversion

Definitions

  • the present invention relates to a timing recovery circuit in a digital demodulator for demodulating received modulated signal by a digital method, and more particularly, to a timing interpolator for directly calculating tap-coefficients by reading sine function values at each clock after storing M number of sine function values in a memory instead of (L+1) ⁇ M number of tap-coefficients, when (L+1) number of filter tap and M number of phase value are used in the demodulating process.
  • a receiver samples transmitted analog signal in a predetermined sampling clock converting it into a digital signal.
  • a carrier signal having frequency and phase corresponding to modulators used in a transmitter is recovered from the digital signal, and a demodulation is performed by using the recovered carrier signal to recover an original information signal.
  • an exact sampling clock which affects the efficiency of the receiver, is determined.
  • a feedback loop for controlling the sampling clock by adjusting the phase of local clock or a feedforward loop utilizing regenerated timing wave from the received modulation signal is used, as in an analog modem.
  • the sampling is not synchronized with the data symbol, namely if the sampling clock is not related to the symbol timing the timing is controlled by an interpolation.
  • an exact strobe values in the modem are generated, similar to the strobe values generated when the sampling is synchronized with the symbol.
  • FIG. 1 shows a block diagram of a conventional digital timing recovery unit, that performs the timing recovery using a feedback loop.
  • the digital timing recovery unit comprises a sampling clock generator 11, a first sampler 12, an interpolator 13, a data filter 14, a timing error detector 15, a loop filter 16, and a controller 17.
  • the sampling clock generator 11 generates a sampling clock in period Ts, in which alising does not occur.
  • the first sampler 12 generates signal X(mTs), which samples a band limited input signal X(t) according to the sampling clock, and outputs it.
  • the interpolator 13 generates and outputs an interpolant y(kTi) for interpolating the signal X(mTs) in interpolation interval Ti.
  • the data filter 14 filters the interpolant y(kTi) to output the final strobe data.
  • the timing error detector 15 detects a timing error from the strobe data.
  • the loop filter 16 removes a noise component of the detected timing error.
  • the controller 17 controls an operation of the interpolator 13 by using the filtered timing error to perform the exact timing recovery.
  • FIG. 2 shows a block diagram for explaining an operation of the interpolator 13 in FIG. 1.
  • the interpolator 13 comprises a digital/analog (D/A) converter 21, an interpolating filter 22, and a second sampler 23.
  • D/A digital/analog
  • a sampled signal X(mTs) from a first sampler 12 shown in FIG. 1 is converted into an analog signal x(t) by the D/A converter 21.
  • the converted analog signal x(t) is filtered by the interpolating filter 22 to generate an interpolator signal y(t).
  • the interpolator signal y(t) is resampled by the second sampler 23 to be outputted as an interpolant y(kTi).
  • the sampling interval of the second sampler 23, namely the interval between the interpolants Ti is provided from the controller 17 in FIG. 1.
  • An output y(t) from the interpolating filter 22 is expressed by the following expression 1, when an impulse response of the interpolating filter 22 is h 1 (t).
  • the original signal x(t) does not coincide with the filtered signal y(t).
  • the interpolant can be calculated digitally from the above expression 2.
  • int z! refers to the largest integer not exceeding z, where 0 ⁇ ⁇ k ⁇ 1.
  • the fractional interval ⁇ k is very important for adjusting the resampling interval of the interpolator 13, and it is calculated in the controller 17 to be provided to the second sampler 23.
  • the variations in the fractional interval ⁇ k in respect to the relationship between the intervals Ts and Ti of the first sampler 11 and second sampler 23, respectively, are examined.
  • the expression 2 can be alternatively expressed into the following expression 4 through the substitution by the variables from the expression 3.
  • a digital interpolation in a modem can be achieved by the above expression 4.
  • the impulse response value h I (i+ ⁇ k )Ts! of the interpolating filter 22 is a filter tap-coefficient.
  • the interpolator 13 can be comprised of a Finite Impulse Response (FIR) having a delay shift register, a multiplier, and an adder.
  • FIR Finite Impulse Response
  • the interpolator of the system operating in a high speed stores a calculated filter tap-coefficient in a separate memory; for example, a ROM, and reads filter tap-coefficients in time units, namely the clock units, to perform the interpolation.
  • the tap-coefficients of the interpolation are obtained by a polynomial filter or a polyphase filter.
  • the number of tap-coefficients stored in the memory is (L+1) ⁇ M, when the filter index i is a variable in the impulse response, the number of tap is (L+1), and the number of fractional interval ⁇ k is M.
  • the number of tap in the interpolating filter is related to the transmission speed of a signal or to the operating speed of a system, the number of calculated filter tap coefficients increases when the system is operated in high speed. Accordingly, there is a need to increase the memory capacity for storing the tap-coefficients.
  • the present invention provides a timing interpolator in a digital demodulator, comprising:
  • an address generator for inputting M number of fractional intervals between 0 to 1 at each clock, and generating addresses from the fractional intervals;
  • a memory for storing M number of sine function values corresponding to the M number of fractional intervals, and outputting sine function values corresponding to the addresses from the address generator;
  • a tap-coefficient calculator for receiving the filter index, the fractional intervals, and the sine function values to calculate tap-coefficients
  • a digital filter for having L+1 number of taps to filter the input signal by using the calculated tap-coefficients obtained in said tap-coefficient calculator, and outputting the filtered signal.
  • the timing interpolator having the above structure stores M number of sine function values according to the variation of the fractional interval instead of (L+1) ⁇ M number of tap-coefficients, according to the variation of the filter index and the fractional interval such that the interpolator's memory decreases by as much as 1/(L+1) by using the stored sine function values to directly calculate the tap-coefficients.
  • FIG. 1 is a block diagram of a conventional timing recovery circuit in a digital demodulator
  • FIG. 2 is a block diagram illustrating an interpolator of FIG. 1;
  • FIG. 3 is a block diagram illustrating a timing interpolator according to the present invention.
  • FIG. 4 is a detailed block diagram of the timing interpolator illustrated in FIG. 3.
  • FIG. 3 shows a block diagram of a timing interpolator according to the preferred embodiment of the present invention.
  • the timing interpolator comprises an address generator 32, a memory 34; for example a ROM, a tap coefficient calculator 36, and a digital filter 39; for example a FIR filter.
  • the address generator 32 receives fractional intervals ⁇ k 31 at each clock to generate an address signal 33.
  • the memory 34 stores M number of sine function values according to values of the fractional intervals ⁇ k , and outputs the sine function value 35 corresponding to the memory address 33.
  • the tap-coefficient calculator 36 receives sine function values 35 outputted from the memory 34, the fractional intervals ⁇ k , and the filter index i, and calculates and outputs tap-coefficients 38.
  • the digital filter 39 filters the input signals 30 according to the received tap-coefficients 38 and address signals 33. and outputs interpolants 40.
  • FIG. 4 is a detailed block diagram of the timing interpolator illustrated in FIG. 3, and particularly it shows the memory 34, the tap-coefficient calculator 36, and the digital filter 39.
  • the tap-coefficient calculator 36 comprises a sine buffer 36-1 for temporally latching outputs from the memory 34, an adder 36-2 for adding the fractional interval ⁇ k 31 to the filter index i; 37, a multiplier 36-4 for multiplying a value outputted from the adder 36-2 by ⁇ value stored in a memory, for example a ROM 36-3, a divider 36-5 for outputting an absolute value 38-1 of the tap-coefficient by dividing the sine function value 35 outputted from the sine buffer 36-1 into a value outputted from the multiplier 36-4, and a sign decision unit 36-6 for receiving the filter index i 37 and deciding a sign 38-2 of the tap-coefficient.
  • the digital filter 39 comprises a basic-filtering unit 39-1, an auxiliary filtering unit 39-2, an adder 39-3, for adding values from each multiplier 3, 3-1, to 3-L, and for outputting an interpolant 40 (a filtered input signal 30).
  • the basic-filtering unit 39-1 comprises a tap-coefficient buffer 2 for receiving an absolute value 38-1 of tap-coefficient, the sign 38-2 of tap-coefficient, and the address signal 33, and outputs the tap-coefficient 38.
  • the basic-filtering unit 39-1 also comprises a multiplier 3 for multiplying the input signal by the tap-coefficient from the tap-coefficient buffer 2.
  • the auxiliary filtering unit 39-2 comprises a plurality of groups, the groups being connected in parallel.
  • Each group comprises: a first delay latch unit 1-1 for delaying the input signal 30 as much as one clock; a first tap-coefficient register unit 2-1 for inputting the absolute value 38-1 of tap-coefficient, the sign 38-2 of tap-coefficient, and the address signal 33 to output the tap-coefficient 38; and a first multiplier 3-1 for multiplying an output value from the first delay latch unit 1-1 by an output value from the first tap-coefficient register unit 2-1.
  • the interpolation filter 22 of FIG. 2, having an impulse response, ##EQU5## can be constructed with a FIR digital filter having an impulse response, ##EQU6##
  • the filter index i is a positive integer or a negative integer, and it is determined by the number of taps in the FIR filter (here, assume that the number of taps is L+1).
  • the fractional interval ⁇ k is a fraction between 0 to 1 to re-control the sampling intervals outputted from the controller 17. For example, if the filter indices i are -4, -3, -2, -1, 0, 1, 2, 3 and the fractional interval is the same, the following relationships 1 and 2 are derived, since the sine function is an even function.
  • the present invention provides the result of calculated impulse response (the absolute value of the tap-coefficient) by using the sine function value read from the memory 34, and signs of the corresponding absolute value to the digital filter 39.
  • the address generator 32 receives the fractional intervals having M number of fractional values between 0 to 1 at each clock, and quantizes them to be outputted as an address signal 33.
  • the fractional intervals 31 is used to define filter coefficient sample values.
  • the memory 34 stores M number of sine function values SIN(1) through SIN(M) according to the fractional interval values, and outputs the sine function value 35 corresponding to the address signal 33 outputted from the address generator 32.
  • the sine function value read from the memory 34 is outputted to the sine buffer 36-1 of the tap-coefficient calculator 36.
  • the tap-coefficient calculator 36 receives the sine function value 35, the fractional interval ⁇ k , and the filter index i from the memory 34, calculates and outputs the tap-coefficient.
  • the adder 36-2 receives the fractional interval 31 and the filter index, adds and outputs the result to the multiplier 36-4.
  • the multiplier 36-4 reads the ⁇ value stored in the ROM 36-3, multiplies it by the value outputted from the adder 36-2, and outputs the result to divider 36-5.
  • the divider 36-5 divides the value outputted from the sine buffer 36-1 into the value outputted from the multiplier 36-4, and outputs the result as an absolute value of the tap-coefficient.
  • the sign decision unit 36-6 receives the filter index value i 37 to decide the sign 38-2 of the tap-coefficient.
  • the tap-coefficient corresponds to a sinc function, the value obtained by dividing the sine function value sin(i+ ⁇ k ) ⁇ into (i+ ⁇ k ) ⁇ .
  • the tap-coefficient has an opposite sign to the sign of the corresponding sine function value when the filter index value is a positive number, whereas it has the same sign as the sign of the corresponding sine function value when the filter index value is a negative number.
  • the conditions for determining the sign are as follows: “+” is outputted when the filter index value is 0; “+” is outputted when the filter index is also a positive and even number; “-” is outputted when the filter index is a positive and odd number; “-” is outputted when the filter index is also a negative and even number; and “+” is also outputted when the filter index is a negative and odd number
  • the digital filter 39 receives both the tap-coefficient 38 from the tap-coefficient calculator 36 and the address signal 33. In respect to these inputs, it generates and outputs the interpolant 40, a result of the filtered input signal 30.
  • the interpolant 40 is used to calculate the strobe data necessary for the data and timing recovery in the data filter 14 of FIG. 1.
  • the tap-coefficient buffer 2 receives the absolute value 38-1 of the tap-coefficient, the sign 38-2 of the tap-coefficient, and the address signal 33. With respect to these inputs it generates the tap-coefficient 38.
  • the multiplier 3 multiplies the input signal 30 by the tap-coefficient 38 from the tap-coefficient buffer 2, and outputs the result to the adder 39-3.
  • L number of delay latch units 1-1 to 1-L are directly connected for outputting each input signal 30, after delaying it from 1 to L number of clock.
  • L number of tap-coefficient registers 2-1 to 2-L receive the absolute value 38-1 of the tap-coefficient, the sign 38-2 of the tap-coefficient, and the address signal 33 for generating and storing the tap-coefficients.
  • L number of multipliers 3-1 to 3-L multiplies the L number of outputs from the delay latch unit 1-1 to 1-L by the L number of outputs from the tap-coefficient registers 2-1 to 2-L, and provides the L number of multiplied values to the adder 39-3.
  • the first multiplier 3-1 multiplies the delayed signal (the input signal X(mTs); 30 delayed as much as one clock in the first delay latch unit 1-1) by the tap-coefficient outputted from the first tap-coefficient register 2-1, and outputs the multiplied value to the adder 39-3.
  • the L number of multipliers multiply the delayed signal (the input signal X(mTs); 30 delayed as much as L number of clock in the L th delay latch unit 1-L) by the tap-coefficient outputted from the L th tap-coefficient register 2-L, and outputs the multiplied value to the adder 39-3.
  • the adder 39-3 adds outputs from each multiplier 3, 3-1, to 3-L, and outputs the added values as the interpolants y(kTi); 40.
  • the timing interpolator of the present invention stores M number of sine function values according to fractional intervals inputted at each clock in the memory, and directly calculates, (L+1) number of tap-coefficients.
  • the interpolator's memory decreases by as much as 1/(L+1) times by using the stored sine function values to directly calculate the tap-coefficients.

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US6286021B1 (en) * 1997-10-22 2001-09-04 Texas Instruments Incorporated Apparatus and method for a reduced complexity tap leakage unit in a fast adaptive filter circuit
US6307900B1 (en) * 1997-06-30 2001-10-23 Daewoo Electronics Co., Ltd. Method and apparatus for recovering digital data by employing asynchronous data sampling techniques
US20020012390A1 (en) * 2000-06-22 2002-01-31 Kim Sang Yeon Filter coefficient generator
US20030154224A1 (en) * 2001-10-30 2003-08-14 Zhongnong Jiang Efficient real-time computation of FIR filter coefficients
US6744835B1 (en) * 2000-06-02 2004-06-01 Conexant Systems, Inc. Methods and apparatus for implementing an interpolation finite impulse response (FIR) filter for use in timing recovery
US20050249320A1 (en) * 2002-08-30 2005-11-10 Infineon Technologies Ag Method and device for digital filtering of interpolated values
US20080177264A1 (en) * 2006-10-19 2008-07-24 Simpirica Spine, Inc. Methods and systems for laterally stabilized constraint of spinous processes
US20080319487A1 (en) * 2007-06-22 2008-12-25 Simpirica Spine, Inc. Methods and Devices for Controlled Flexion Restriction of Spinal Segments
US20090082820A1 (en) * 2004-03-09 2009-03-26 Louie Fielding Spinal implant and method for restricting spinal flexion
US20090264929A1 (en) * 2006-10-19 2009-10-22 Simpirica Spine, Inc. Structures and methods for constraining spinal processes with single connector
US20090261994A1 (en) * 2006-09-26 2009-10-22 Micronas Gmbh Device and method for polyphase resampling
US20100004701A1 (en) * 2008-06-06 2010-01-07 Simpirica Spine, Inc. Methods and apparatus for deploying spinous process constraints
US20100023060A1 (en) * 2008-06-06 2010-01-28 Simpirica Spine, Inc. Methods and apparatus for locking a band
US20100036424A1 (en) * 2007-06-22 2010-02-11 Simpirica Spine, Inc. Methods and systems for increasing the bending stiffness and constraining the spreading of a spinal segment
US20100234894A1 (en) * 2009-03-10 2010-09-16 Simpirica Spine, Inc. Surgical tether apparatus and methods of use
US8162982B2 (en) 2006-10-19 2012-04-24 Simpirica Spine, Inc. Methods and systems for constraint of multiple spine segments
CN103178805A (zh) * 2011-12-20 2013-06-26 中兴通讯股份有限公司 插值滤波器输出控制方法、装置及系统
US8523904B2 (en) 2004-03-09 2013-09-03 The Board Of Trustees Of The Leland Stanford Junior University Methods and systems for constraint of spinous processes with attachment
US8562653B2 (en) 2009-03-10 2013-10-22 Simpirica Spine, Inc. Surgical tether apparatus and methods of use
US8668719B2 (en) 2009-03-30 2014-03-11 Simpirica Spine, Inc. Methods and apparatus for improving shear loading capacity of a spinal segment
US9107706B2 (en) 2009-03-10 2015-08-18 Simpirica Spine, Inc. Surgical tether apparatus and methods of use

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Cited By (42)

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US6307900B1 (en) * 1997-06-30 2001-10-23 Daewoo Electronics Co., Ltd. Method and apparatus for recovering digital data by employing asynchronous data sampling techniques
US6286021B1 (en) * 1997-10-22 2001-09-04 Texas Instruments Incorporated Apparatus and method for a reduced complexity tap leakage unit in a fast adaptive filter circuit
US6744835B1 (en) * 2000-06-02 2004-06-01 Conexant Systems, Inc. Methods and apparatus for implementing an interpolation finite impulse response (FIR) filter for use in timing recovery
US20020012390A1 (en) * 2000-06-22 2002-01-31 Kim Sang Yeon Filter coefficient generator
US6898255B2 (en) * 2000-06-22 2005-05-24 Lg Electronics Inc. Filter coefficient generator
US20030154224A1 (en) * 2001-10-30 2003-08-14 Zhongnong Jiang Efficient real-time computation of FIR filter coefficients
US7007052B2 (en) * 2001-10-30 2006-02-28 Texas Instruments Incorporated Efficient real-time computation
US20050249320A1 (en) * 2002-08-30 2005-11-10 Infineon Technologies Ag Method and device for digital filtering of interpolated values
US7305425B2 (en) * 2002-08-30 2007-12-04 Infineon Technologies Ag Method and device for digital filtering of interpolated values
US8486110B2 (en) 2004-03-09 2013-07-16 The Board Of Trustees Of The Leland Stanford Junior University Spinal implant and method for restricting spinal flexion
US8523904B2 (en) 2004-03-09 2013-09-03 The Board Of Trustees Of The Leland Stanford Junior University Methods and systems for constraint of spinous processes with attachment
US20090082820A1 (en) * 2004-03-09 2009-03-26 Louie Fielding Spinal implant and method for restricting spinal flexion
US10080589B2 (en) 2004-03-09 2018-09-25 The Board Of Trustees Of The Leland Stanford Junior University Methods and systems for constraint of spinous processes with attachment
US8216275B2 (en) 2004-03-09 2012-07-10 The Board Of Trustees Of The Leland Stanford Junior University Spinal implant and method for restricting spinal flexion
US9149304B2 (en) 2004-03-09 2015-10-06 The Board Of Trustees Of The Leland Sanford Junior University Methods and systems for constraint of spinous processes with attachment
US8105363B2 (en) 2004-03-09 2012-01-31 The Board Of Trustees Of The Leland Stanford Junior University Spinal implant and method for restricting spinal flexion
US7728743B2 (en) * 2006-09-26 2010-06-01 Trident Microsystems (Far East) Ltd. Device and method for polyphase resampling
US20090261994A1 (en) * 2006-09-26 2009-10-22 Micronas Gmbh Device and method for polyphase resampling
US8790372B2 (en) 2006-10-19 2014-07-29 Simpirica Spine, Inc. Methods and systems for constraint of multiple spine segments
US8454660B2 (en) 2006-10-19 2013-06-04 Simpirica Spine, Inc. Methods and systems for laterally stabilized constraint of spinous processes
US8029541B2 (en) 2006-10-19 2011-10-04 Simpirica Spine, Inc. Methods and systems for laterally stabilized constraint of spinous processes
US9295499B2 (en) 2006-10-19 2016-03-29 Empirical Spine, Inc. Methods and systems for laterally stabilized constraint of spinous processes
US8162982B2 (en) 2006-10-19 2012-04-24 Simpirica Spine, Inc. Methods and systems for constraint of multiple spine segments
US20080177264A1 (en) * 2006-10-19 2008-07-24 Simpirica Spine, Inc. Methods and systems for laterally stabilized constraint of spinous processes
US8187307B2 (en) 2006-10-19 2012-05-29 Simpirica Spine, Inc. Structures and methods for constraining spinal processes with single connector
US20090264929A1 (en) * 2006-10-19 2009-10-22 Simpirica Spine, Inc. Structures and methods for constraining spinal processes with single connector
US20100036424A1 (en) * 2007-06-22 2010-02-11 Simpirica Spine, Inc. Methods and systems for increasing the bending stiffness and constraining the spreading of a spinal segment
US8403964B2 (en) 2007-06-22 2013-03-26 Simpirica Spine, Inc. Methods and systems for increasing the bending stiffness and constraining the spreading of a spinal segment
US8403961B2 (en) 2007-06-22 2013-03-26 Simpirica Spine, Inc. Methods and devices for controlled flexion restriction of spinal segments
US20080319487A1 (en) * 2007-06-22 2008-12-25 Simpirica Spine, Inc. Methods and Devices for Controlled Flexion Restriction of Spinal Segments
US8308771B2 (en) 2008-06-06 2012-11-13 Simpirica Spine, Inc. Methods and apparatus for locking a band
US8187305B2 (en) 2008-06-06 2012-05-29 Simpirica Spine, Inc. Methods and apparatus for deploying spinous process constraints
US20100023060A1 (en) * 2008-06-06 2010-01-28 Simpirica Spine, Inc. Methods and apparatus for locking a band
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JP3858160B2 (ja) 2006-12-13
KR100189371B1 (ko) 1999-06-01
GB2316586A (en) 1998-02-25
JPH10190759A (ja) 1998-07-21
CN1175145A (zh) 1998-03-04
GB2316586B (en) 2001-03-14
KR19980015796A (ko) 1998-05-25
CN1208922C (zh) 2005-06-29
GB9717806D0 (en) 1997-10-29

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