US5781587A - Clock extraction circuit - Google Patents

Clock extraction circuit Download PDF

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Publication number
US5781587A
US5781587A US08/553,106 US55310695A US5781587A US 5781587 A US5781587 A US 5781587A US 55310695 A US55310695 A US 55310695A US 5781587 A US5781587 A US 5781587A
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stream
binary
retimed
clock
retiming
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US08/553,106
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Paul Bruce
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Hitachi Ltd
Benhov GmbH LLC
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Northern Telecom Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • This invention relates to digital transmission systems and in particular to clock extraction arrangements for such systems.
  • the invention also relates to multiplexers/demultiplexers incorporating such clock extraction arrangements.
  • a key feature of any digital transmission system in which a plurality of signals are multiplexed and demultiplexed is the provision of some means of synchronisation to ensure that the timing of transmission equipment such as a multiplexer/demultiplexer is matched to the signal timing.
  • this ⁇ local ⁇ synchronisation is achieved by extracting timing or clock information from the digital signal itself.
  • phase locked loop provides a substantially jitter-free ⁇ flywheel ⁇ synchronisation with a received digital signal.
  • a typical phase locked loop technique is described in specification GB-A-2,255,480. While this technique provides an effective solution, the circuitry required is complex and is thus relatively costly.
  • the object of the invention is to minimise or to overcome this disadvantage.
  • a clock extraction circuit for a digital transmission system and adapted to extract timing information from a ternary data pulse stream whereby to retime the ternary data stream
  • the circuit including means for deriving first and second binary signal streams corresponding respectively to the positive and negative going pulses of the ternary data stream, means for combining said first and second binary streams to provide a further binary stream, means including a local clock for generating from said further binary stream a reference signal stream, means for retiming said first and second binary data streams to said reference signal stream, and means for recombining said retimed binary data streams whereby to generate a retimed ternary data stream, characterised in that the reference signal stream is generated by retiming the further binary stream to the local clock, delaying the retimed further binary stream by one clock pulse, and combining the delayed binary stream with the further binary stream to provide a twice bit rate clock signal whose rising edges are aligned to the further binary stream and provide a timing reference for retiming said
  • a method of retiming a ternary data signal in a digital transmission system including deriving first and second binary signal streams corresponding respectively to the positive and negative going pulses of the ternary data stream, combining said first and second binary streams to provide a further binary stream, generating from said further binary stream and from a local clock a reference signal stream, retiming said first and second binary data streams to said reference signal stream, and recombining said retimed binary data streams whereby to generate a retimed ternary data stream, characterised in that the reference signal stream is generated by retiming the further binary stream to the local clock, delaying the retimed further binary stream by one clock pulse, and combining the delayed binary stream with the further binary stream to provide a twice bit rate clock signal whose rising edges are aligned to the further binary stream and provide a timing reference for retiming said first and second binary signals.
  • the circuit may be employed for the retiming of ternary data in a digital repeater.
  • FIG. 1 is a schematic diagram of a digital multiplexer/demultiplexer arrangement
  • FIG. 2 shows in schematic form a digital processor for use in the multiplexer/demultiplexer arrangement of FIG. 1;
  • FIG. 3 shows a clock extraction circuit for use in the processor of FIG. 2;
  • FIGS. 4 and 5 illustrate signal wave forms for the circuit of FIG. 3.
  • the multiplexer/demultiplexer arrangement includes a digital processor 11 coupled to a set of tributary inputs 110 and tributary outputs 111.
  • the tributaries comprise wired inputs and outputs and carry data at a rate of 2 Mb/s.
  • the processor 11 is also coupled to a pair of optical line transmission units (OLTU 1 and OLTU 2) which provide an interface to an optical transmission network 12 comprising e.g. a passive optical network. In use, only one of the line transmission units is enabled at any one time, the other unit providing a back-up in case of a system failure.
  • the processor is shown in further detail in FIG. 2 and includes means for regenerating (21) and retiming (22) ternary, e.g. HDB3 encoded data from the tributary input or from the line termination units.
  • the regenerator 21 outputs two binary signal streams DP and DN corresponding respectively to the positive going and negative going pulses of the ternary data stream. These signals are fed to clock extraction circuit 22 via NAND gate 31 and to respective flip-flops 23P and 23N whose clock inputs receive timing information from the retiming means or clock extraction circuit 22.
  • the retimed HDB3 signals are output in parallel to a pair of output buffers 24A and 24B.
  • the processor accepts four tributary input signals from the served equipment and regenerates and retimes the data whereby to provide two identical copies of the input data stream for transmission to the network.
  • Alarms such as loss of input signal, AIS present and HDB3 coding errors are extracted from the input data streams.
  • the processor accepts eight inputs from the receive sides of the optical line termination units. The alarms are collected from these data streams and, optionally the processor may search for frame alignment and for framing errors.
  • the tributary outputs are switched either individually or as a block of four.
  • the clock extraction circuit 22 is shown in FIG. 3 and the associated signal waveforms in FIGS. 4 and 5. To facilitate the understanding of the technique, the time axis of FIG. 5 is compressed relative to that of FIG. 4.
  • the positive going and negative going portions of the HDB3 data stream are used to generate respective data streams DP and DN. These data streams are combined by NAND gate 31 (FIG. 3) to provide a single data stream D (FIG. 4).
  • This data stream D is then retimed (FIG. 5) using the external clock SLCLK to generate a waveforms R1 which is timed to the next positive going clock pulse and a second wave form R2 which is delayed by one clock pulse after R1.
  • waveforms R2 can be generated directly, it is more convenient to generate this wave form indirectly from R1.
  • the waveforms D and R2 are then combined in XOR gate 32 (FIG. 3) producing a twice bit rate clock (FIG. 5) whose rising edges are aligned to the data stream and which can be used to retime the input data stream.
  • the falling edges of the XOR output are aligned to the standby clock so that the clock pulse will have a mark/space ratio within set limits.
  • the falling edges will be subject to jitter as they are not related to the data frequency, but this is no disadvantage as the falling edges are not used in the retiming process.
  • the gapped clock produced at the XOR gate output is used to continually reset the counter 33 (FIG. 3).
  • this clock is not related to the data stream, no jitter is added as the zeros or spaces do not contain any timing information. There is no necessary to decode the retimed data before it is applied to the output buffers 24A and 24B (FIG. 2) to provide a broadcast transmit facility.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

A clock extraction circuit for retiming a ternary data stream derives first and second binary streams corresponding respectively to the positive and negative going portions of the ternary data stream These binary streams are combined to provide a further binary stream which is retimed to a local clock whereby to generate a reference stream for retiming the first and second binary data streams to said reference stream. The retimed binary data streams are combined to generate a retimed ternary data stream.

Description

This invention relates to digital transmission systems and in particular to clock extraction arrangements for such systems. The invention also relates to multiplexers/demultiplexers incorporating such clock extraction arrangements.
BACKGROUND OF THE INVENTION
A key feature of any digital transmission system in which a plurality of signals are multiplexed and demultiplexed is the provision of some means of synchronisation to ensure that the timing of transmission equipment such as a multiplexer/demultiplexer is matched to the signal timing. Conventionally this `local` synchronisation is achieved by extracting timing or clock information from the digital signal itself.
As transmission bit rates are increased to provide a corresponding increase in system capacity, the accuracy of the extracted timing or clock information is becoming more and more crucial. A particular problem with conventional clock extraction techniques when sent at these higher bit rates is that of jitter in the extracted clock signal with consequent loss of precise timing. One approach to this problem has been the development of clock extraction limits in which a phase locked loop provides a substantially jitter-free `flywheel` synchronisation with a received digital signal. A typical phase locked loop technique is described in specification GB-A-2,255,480. While this technique provides an effective solution, the circuitry required is complex and is thus relatively costly.
The object of the invention is to minimise or to overcome this disadvantage.
SUMMARY OF THE INVENTION
According to one aspect of the invention there is provided a clock extraction circuit for a digital transmission system and adapted to extract timing information from a ternary data pulse stream whereby to retime the ternary data stream, the circuit including means for deriving first and second binary signal streams corresponding respectively to the positive and negative going pulses of the ternary data stream, means for combining said first and second binary streams to provide a further binary stream, means including a local clock for generating from said further binary stream a reference signal stream, means for retiming said first and second binary data streams to said reference signal stream, and means for recombining said retimed binary data streams whereby to generate a retimed ternary data stream, characterised in that the reference signal stream is generated by retiming the further binary stream to the local clock, delaying the retimed further binary stream by one clock pulse, and combining the delayed binary stream with the further binary stream to provide a twice bit rate clock signal whose rising edges are aligned to the further binary stream and provide a timing reference for retiming said first and second binary signals.
According to another aspect of the invention there is provided a method of retiming a ternary data signal in a digital transmission system, the method including deriving first and second binary signal streams corresponding respectively to the positive and negative going pulses of the ternary data stream, combining said first and second binary streams to provide a further binary stream, generating from said further binary stream and from a local clock a reference signal stream, retiming said first and second binary data streams to said reference signal stream, and recombining said retimed binary data streams whereby to generate a retimed ternary data stream, characterised in that the reference signal stream is generated by retiming the further binary stream to the local clock, delaying the retimed further binary stream by one clock pulse, and combining the delayed binary stream with the further binary stream to provide a twice bit rate clock signal whose rising edges are aligned to the further binary stream and provide a timing reference for retiming said first and second binary signals.
The circuit may be employed for the retiming of ternary data in a digital repeater.
BRIEF DESCRIPTION OF THE DRAWINGS
An embodiment of the invention will now be described with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a digital multiplexer/demultiplexer arrangement;
FIG. 2 shows in schematic form a digital processor for use in the multiplexer/demultiplexer arrangement of FIG. 1;
FIG. 3 shows a clock extraction circuit for use in the processor of FIG. 2; and
FIGS. 4 and 5 illustrate signal wave forms for the circuit of FIG. 3.
DESCRIPTION OF PREFERRED EMBODIMENT
Referring to FIG. 1, the multiplexer/demultiplexer arrangement includes a digital processor 11 coupled to a set of tributary inputs 110 and tributary outputs 111. Typically the tributaries comprise wired inputs and outputs and carry data at a rate of 2 Mb/s. The processor 11 is also coupled to a pair of optical line transmission units (OLTU 1 and OLTU 2) which provide an interface to an optical transmission network 12 comprising e.g. a passive optical network. In use, only one of the line transmission units is enabled at any one time, the other unit providing a back-up in case of a system failure.
The processor is shown in further detail in FIG. 2 and includes means for regenerating (21) and retiming (22) ternary, e.g. HDB3 encoded data from the tributary input or from the line termination units. The regenerator 21 outputs two binary signal streams DP and DN corresponding respectively to the positive going and negative going pulses of the ternary data stream. These signals are fed to clock extraction circuit 22 via NAND gate 31 and to respective flip- flops 23P and 23N whose clock inputs receive timing information from the retiming means or clock extraction circuit 22. The retimed HDB3 signals are output in parallel to a pair of output buffers 24A and 24B. The processor accepts four tributary input signals from the served equipment and regenerates and retimes the data whereby to provide two identical copies of the input data stream for transmission to the network. Alarms such as loss of input signal, AIS present and HDB3 coding errors are extracted from the input data streams. In the reverse direction, the processor accepts eight inputs from the receive sides of the optical line termination units. The alarms are collected from these data streams and, optionally the processor may search for frame alignment and for framing errors. The tributary outputs are switched either individually or as a block of four.
The clock extraction circuit 22 is shown in FIG. 3 and the associated signal waveforms in FIGS. 4 and 5. To facilitate the understanding of the technique, the time axis of FIG. 5 is compressed relative to that of FIG. 4. The positive going and negative going portions of the HDB3 data stream are used to generate respective data streams DP and DN. These data streams are combined by NAND gate 31 (FIG. 3) to provide a single data stream D (FIG. 4). This data stream D is then retimed (FIG. 5) using the external clock SLCLK to generate a waveforms R1 which is timed to the next positive going clock pulse and a second wave form R2 which is delayed by one clock pulse after R1. It will be understood that although the waveforms R2 can be generated directly, it is more convenient to generate this wave form indirectly from R1. The waveforms D and R2 are then combined in XOR gate 32 (FIG. 3) producing a twice bit rate clock (FIG. 5) whose rising edges are aligned to the data stream and which can be used to retime the input data stream. The falling edges of the XOR output are aligned to the standby clock so that the clock pulse will have a mark/space ratio within set limits. The falling edges will be subject to jitter as they are not related to the data frequency, but this is no disadvantage as the falling edges are not used in the retiming process.
The gapped clock produced at the XOR gate output is used to continually reset the counter 33 (FIG. 3). When a zero or space is encountered in the output signal, the counter is allowed to run until it reaches its termination value where QA=QB=QC=1 under which condition a single clock pulse is generated at the output of the AND gate 34. This clock pulse is used to retime the zero. Although this clock is not related to the data stream, no jitter is added as the zeros or spaces do not contain any timing information. There is no necessary to decode the retimed data before it is applied to the output buffers 24A and 24B (FIG. 2) to provide a broadcast transmit facility.

Claims (6)

I claim:
1. A clock extraction circuit for a digital transmission system and adapted to extract timing information from a ternary data pulse stream whereby to retime the ternary data pulse stream, the circuit including means for combining first and second binary signal streams derived from the positive and negative going pulses of the ternary pulse stream to provide a further binary stream, means including a local clock for generating from said further binary stream a reference signal stream, means for retiming said first and second binary signal streams to said reference signal stream, and means for recombining said retimed binary signal streams whereby to generate a retimed ternary data stream, wherein the reference signal stream is generated by retiming the further binary stream to the local clock, delaying the retimed further binary stream by one clock pulse, and combining the delayed binary stream with the further binary stream to provide a twice bit rate clock signal whose rising edges are aligned to the further binary stream and provide a timing reference for retiming said first and second binary signal streams.
2. A clock extraction circuit as claimed in claim 1, wherein said retimed ternary data pulse stream is generated as two identical signals in parallel.
3. A clock extraction circuit as claimed in claim 2, wherein said ternary signals are HDB3 signals.
4. A method of retiming a ternary data pulse stream in a digital transmission system, the method including deriving first and second binary signal streams corresponding respectively to the positive and negative going pulses of the ternary data pulse stream, combining said first and second binary signal streams to provide a further binary stream, generating from said further binary stream and from a local clock a reference signal stream, retiming said first and second binary signal streams to said reference signal stream, and recombining said retimed binary data streams whereby to generate a retimed ternary data pulse stream, wherein the reference signal stream is generated by retiming the further binary stream to the local clock, delaying the retimed further binary stream by one clock pulse, and combining the delayed binary stream with the further binary stream to provide a twice bit rate clock signal whose rising edges are aligned to the further binary stream and provide a timing reference for retiming said first and second binary signal streams.
5. A method as claimed in claim 4, wherein said retimed ternary data pulse stream is generated as two identical signals in parallel.
6. A method as claimed in claim 5, wherein said ternary signals are HDB3 signals.
US08/553,106 1994-11-03 1995-11-03 Clock extraction circuit Expired - Lifetime US5781587A (en)

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GB9422233A GB2294850B (en) 1994-11-03 1994-11-03 Clock extraction circuit
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6338156B1 (en) * 1997-12-23 2002-01-08 Alcatel Method and device for detecting the loss-of-signal condition at the input of a transmission line interface
US6680988B1 (en) * 1999-08-13 2004-01-20 Oki Electric Industry Co., Ltd. Non-linear extraction circuit and clock extraction circuit
JP2014239363A (en) * 2013-06-10 2014-12-18 株式会社明電舎 Received clock extraction circuit

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2121763C1 (en) * 1995-10-23 1998-11-10 Акционерное общество открытого типа "Информационные телекоммуникационные технологии" Method for transmitting and receiving digital information
DE10005152A1 (en) * 2000-02-07 2001-08-09 Deutsche Telekom Mobil Method for regenerating a clock signal from an HDB3-coded input signal and clock regenerator for performing the method
RU2356088C1 (en) * 2008-03-11 2009-05-20 Общество с ограниченной ответственностью НПЦ "Динамика" - Научно-производственный центр "Диагностика, надежность машин и комплексная автоматизация" Device for remote input-output of discrete signals with galvanic isolation

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US4456890A (en) * 1982-04-05 1984-06-26 Computer Peripherals Inc. Data tracking clock recovery system using digitally controlled oscillator
US5056118A (en) * 1989-05-16 1991-10-08 Rockwell International Corporation Method and apparatus for clock and data recovery with high jitter tolerance
GB2255480A (en) * 1991-04-23 1992-11-04 Motorola Israel Ltd A data demodulator
GB2259632A (en) * 1991-09-13 1993-03-17 Al Sammak Abdul Imam Jassim An encoder/decoder for Manchester code
GB2260883A (en) * 1991-10-24 1993-04-28 Northern Telecom Ltd Clock recovery from a Manchester encoded frame
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GB2271492A (en) * 1992-03-26 1994-04-13 Motorola Inc Apparatus for and method of synchronizing a clock signal
US5455540A (en) * 1994-10-26 1995-10-03 Cypress Semiconductor Corp. Modified bang-bang phase detector with ternary output

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US4284843A (en) * 1979-05-10 1981-08-18 General Electric Company Repeating station for use in digital data communications link
US4696016A (en) * 1986-10-02 1987-09-22 Rockwell International Corporation Digital clock recovery circuit for return to zero data
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US4456890A (en) * 1982-04-05 1984-06-26 Computer Peripherals Inc. Data tracking clock recovery system using digitally controlled oscillator
US5056118A (en) * 1989-05-16 1991-10-08 Rockwell International Corporation Method and apparatus for clock and data recovery with high jitter tolerance
GB2255480A (en) * 1991-04-23 1992-11-04 Motorola Israel Ltd A data demodulator
GB2259632A (en) * 1991-09-13 1993-03-17 Al Sammak Abdul Imam Jassim An encoder/decoder for Manchester code
GB2263609A (en) * 1991-09-30 1993-07-28 Plessey Telecomm Clock extract circuit
GB2260883A (en) * 1991-10-24 1993-04-28 Northern Telecom Ltd Clock recovery from a Manchester encoded frame
GB2271492A (en) * 1992-03-26 1994-04-13 Motorola Inc Apparatus for and method of synchronizing a clock signal
US5455540A (en) * 1994-10-26 1995-10-03 Cypress Semiconductor Corp. Modified bang-bang phase detector with ternary output

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6338156B1 (en) * 1997-12-23 2002-01-08 Alcatel Method and device for detecting the loss-of-signal condition at the input of a transmission line interface
US6680988B1 (en) * 1999-08-13 2004-01-20 Oki Electric Industry Co., Ltd. Non-linear extraction circuit and clock extraction circuit
JP2014239363A (en) * 2013-06-10 2014-12-18 株式会社明電舎 Received clock extraction circuit

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Publication number Publication date
FR2726714A1 (en) 1996-05-10
GB2294850A (en) 1996-05-08
GB2294850B (en) 1999-01-13
DE19541065A1 (en) 1996-05-09
GB9422233D0 (en) 1994-12-21
FR2726714B1 (en) 2000-08-11

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