GB2260883A - Clock recovery from a Manchester encoded frame - Google Patents

Abstract

An arrangement for recovering a clock signal from a Manchester encoded PCM frame includes means for detecting the signal bit transitions of the frame and for deriving a clock signal, wherein the detection means is enabled for a period corresponding to the central or transition part of each Manchester bit. The arrangement inhibits spurious detection of interbit transitions. <IMAGE>

Description

TELECOMMUNICATIONS SYSTEM This invention relates to telecommunications systems in which information is transmitted in a time division multiplex (TDM) manner and in particular to an arrangement for providing clock signal recovery and demultiplexing in such a system. The invention further relates to a method of recovering the clock signal.

United Kingdom Patent No. 2 191 658B (D M Davidson 5-2-2) describes a telecommunication system in which a number of group control units, each serving a number of subscribers, are interconnected e.g. by fibre-optic links. Each link comprises a pair of optical fibres for transmitted and received signals, each of which fibres carries two multiplexed 2.048 Mbit/sec PCM speech channels. These are commonly referred to as the A and B channels.

Within the A and B channels, information is transmitted in the form of frames each comprising e.g. 32 time shots each containing one byte. Manchester coding is employed as, although this effectively doubles the bit rate, it provides a transition in the middle of a bit cell from which a clock may be reconstructed This is necessary to achieve synchronisation. Frame information is encoded into the first transmitted bits of each frame to indicate the start of each frame.

This frame information is detected by the receiving end of the link, i.e.

by the link interface decoder.

Whilst this arrangement has proved generally satisfactory in operation, under some conditions errors in clock recovery have occurred leading to a temporary loss of synchronisation. Specifically it has been found that signal transitions between adjacent bits can result in spurious clock signals.

The object of the present invention is to provide an improved link interface decoder arrangement in which susceptibility to clock error is reduced.

According to the invention there is provided an arrangement for recovering a clock signal from a Manchester encoded PCM frame, the arrangement including means for detecting signal bit transitions of the frame, and for deriving a clock signal therefrom, and means for selectively enabling the detection means for a period corresponding to the central or transition part of each Manchester bit.

According to the invention there is further provided an arrangement for recovering a clock signal from a Manchester encoded PCM frame, the frame including a header portion comprising two binary zeros followed by a Manchester zero, the arrangement including means for detecting signal bit signal transitions within the frame, means for deriving a local clock signal from the detected transitions and means responsive to the Manchester zero within the frame header for selectively enabling the detection means for a period corresponding to the central or transition part of each Manchester bit of the frame whereby to inhibit spurious clock signals corresponding to signal transitions between adjacent signal bits.

An embodiment of the invention will now be described with reference to the accompanying drawings in which: Fig. 1 is a general schematic diagram of a PCM link interface decoder according to the invention; and Fig. 2 is a timing diagram illustrating the operation of the decoder of Fig. 1.

Referring to the drawings, the decoder provides an interface between an incoming fibre optic transmission line 11 and outgoing PCM buses A12 and B12. In use these buses feed a telecommunications group control unit (not shown) e.g. via a FIFO store. The transmission line 11 is coupled to an optical receiver 13 which feeds a corresponding electrical signal to an edge or transition detector 14.

The incoming signal comprises a sequence of PCM frames each of e.g. thirty two time slots. Typically each time slot comprises a byte of eight bits or cells. The first three bits of timeslot one comprise the frame header. The remaining bits of this time slot and the bits of the other time slots of the frame comprise Manchester binary digits. In the first time slot some or all of these Manchester digits may represent supervisory information whilst the remainder represent speed signals corresponding to two multiplexed PCM channels (the A and B channels).

The header portion of the frame comprises a pair of conventional binary zeros followed by a Manchester zero. The subsequent bits of the frame are Manchester bits. The frame header thus comprises two bits during which no signal transition takes place followed by a third bit in which a transition takes place in the middle of that bit. This transition and subsequent transitions are detected by the transition detector 14.

The signal is fed via the transition detector 14 to the CLR input of a 5 bit counter 15. This counter runs from a locally generated 32 MHz clock input and is continuously reset by the output of the transition detector 14. The absence of any transition in the first two bits of the frame inhibits this resetting thus allowing the count to continue and thereby provide an indication of the start of the frame. In Fig. 1 the counter outputs are depicted Q2, Q3, Q4 and Q5. The absence of signal transitions at the start of the frame allows the counter to generate output Q5 which activates a first transition detector 16 whereby to provide timing information for the subsequent signal transition detection process.

As the counter progresses, the second and third bits of the frame are exclusively OR-ed to generate a time window which opens after the start of the next Manchester bit, i.e. the fourth bit, where there may or may not be a signal transition. During this time window the clearing operation of the counter 15 is disabled and the count thus continues. At the end of this time window, i.e. during the central portion of the next bit, when the c counter is reset in response to the signal bit transition, a sampling signal is generated by the counter from signals Q2, Q3 and Q4 which are OR-ed together so as to enable a 32 M clock derived by inverting the 32 M clock to sample the data directly.

The resulting signal is inverted to form the Q decoded A+B data which is input to demultiplexer 16. A decoding clock is obtained by OR-ing the counter outputs Q2, Q3 and Q4. This clock runs at 4MHz. The decoded data is demultiplexed into the A and B channels by the demultiplexor 17. A 2MHz clock, derived from the 4MHz clock is generated to form the RPCM clock and the A and B channels are aligned with this clock.

An RFS generator 17 is provided to ensure that an RFS signal is generated from Q5 at the start of each frame. A signal is generated from Q5 to ensure that the counter 15 is cleared or reset on the first transition of each new frame. This occurs at the middle of the third bit which always comprises a Manchester zero. This also provides a reset signal for the demultiplexer 16 to demultiplex the A and B channels correctly.

The effect of this arrangement is to inhibit signal transition detection except for the transitions which occur at the central portion of each Manchester bit. This effectively overcomes the problem of spurious detection of signal transitions between adjacent bits.

It will be appreciated that, although the clock recovery arrangement has been described above with particular reference to coupling of telecommunications group control units, it is not of course limited to that application.

Claims (9)

1. An arrangement for recovering a clock signal from a Manchester encoded PCM frame, the arrangement including means for detecting signal bit transitions of the frame, and for deriving a clock signal therefrom, and means for selectively enabling the detection means for a period corresponding to the central or transition part of each Manchester bit.

2. An arrangement for recovering a clock signal from a Manchester encoded PCM frame, the frame including a header portion comprising two binary zeros followed by a Manchester zero, the arrangement including means for detecting signal bit signal transitions within the frame, means for deriving a local clock signal from the detected transitions and means responsive to the Manchester zero within the frame header for selectively enabling the detection means for a period corresponding to the central or transition part of each Manchester bit of the frame whereby to inhibit spurious clock signals corresponding to signal transitions between adjacent signal bits.

3. An arrangement as claimed in claim 2, wherein detection of the frame header is effected by a counter having reset means responsive to signal transitions, and means associated with the counter and responsive to a count higher than a predetermined value indicative of the header portion of each said frame.

4. An arrangement as claimed in claim 3, wherein said counter is a five-bit counter.

5. An arrangement as claimed in claim 3 or 4, wherein said detection enabling means is adapted to disable resetting of the counter during said periods between adjacent bits.

6. An arrangement as claimed in any one of claims 1 to 5, and further including means for demultiplexing signals from said frame.

7. A PCM clock recovery arrangement substantially as described herein with reference to and as shown in the accompanying drawings.

8. A PCM telecommunication system incorporating one or more clock recovery arrangements as claimed in any one of claims 1 to 7.

9. A method of clock signal recovery for a Manchester encoded PCM frame which method if substantially as described herein with reference to and as shown in the accompanying drawings.