GB2255480A - A data demodulator - Google Patents

Abstract

This invention relates to data demodulators constructed within modulators/demodulators (modems) and is particularly applicable for demodulators which demodulate 3-level and biphase signals. The data demodulator incorporates a digital phase lock loop arrangement and contains clock generating means, for generating a clock signal, and a phase detector (50), comprising means for detecting a transition of the decoded received signal (DATA'). Furthermore, the data demodulator comprises means for recording a potential advancing/retarding adjustment of the clock in order to correct for a detected phase error and means for determining the next to occur of either a transition in the received signal or the clock signal. In addition, means (51, 52, 55) is provided for applying the potential adjustment to the generated clock signal (RC) as an advancing adjustment or a retarding adjustment depending upon said next determined transition. Synchronization of the generated clock signal (RC) to the received signal (DATA') is therefore achieved through the control and application of the potential advancing/retarding adjustment. <IMAGE>

Description

A Data Demodulator.

Background to the Invention.

This invention relates, in general, to data demodulators constructed within modulators/demodulators (modems) and particularly to data demodulators employing clock recovery and synchronization techniques for biphase and 3-level direct frequency modulated (FM) signals.

Summarv of the Prior Art.

Modem technology is used increasingly within modern, digital electronic equipment. Analog signals are, initially, transposed by a modulator into their digital counterparts. Distinct advantages can be derived from the use of these digital signals; namely that they can be processed by modern electronic circuitry. In addition, the encoded, digital information can be transmitted to remote digital devices through the use of terrestrial communication links such as fibre-optic cables.

Recovery of the initial analog signal in the data demodulator of a modem is dependent upon the synchronization of the received digital signal with a locally generated clock. Moreover, exact synchronization is important for correct modem operation. In order to compensate for phase errors which occur between the received signal and the clock, a synchronizing circuit is utilised within the demodulator circuit of the modem. For optimum modem operation, two criteria must be satisfied: fast synchronization and high stability of the recovered data. However, degradation in the operational performance of modems occurs in the presence of noise.

Prior art modems, such as used with the DarcomTM (trade mark) series of radios manufactured by Motorola Inc., employ 2-level signal modulation techniques and digital phase lock loop circuits. These modems are subject to distortions on the radio link which arise from the DC level of the modulating signal. Typically, these modems have a bit error rate (BER) of 10-6 at -lO2dBm.

Furthermore, high speed data communication in the radio frequency (RF) spectrum, i.e. 800-900 MHz, VHF and UHF regions, is known to incorporate direct frequency modulation (FM) techniques.

These techniques require an operating bandwidth which utilises the frequencies near to the zero threshold of a DC frequency. Therefore, high speed data communication is not feasible on radio links which do not have a sufficient low frequency capability. For example, in the application of repeaters within voice channel radio links, the majority of repeaters require private line signalling. This private line signalling disables the transfer potential of the sub-audio frequencies (0-300Hz). Similarly, Motorola's proprietary trunking radio system, which is mainly designated for the voice channel, also uses sub-audio frequencies for signalling between the central and remote radios. In this latter case, the baud rate for data communication within the system is relatively low (-600 baud in the case of INTRACw products).

In order to up-grade the aforementioned systems to systems capable of handling high speed data communications, modifications are required to either the repeater or the trunking sites. However, these sites are seldom accessible by the user. Furthermore, the modifications costs for the sites which are accessible by the user often prove to be too expensive for the user to implement.

Therefore, it can be appreciated that there is a requirement within the art for a low cost, high performance modem which does not contain a DC level in the modulating signal. Furthermore, it is also desirable that the modem (data demodulator) should have a fast synchronization time and a high stability (especially when noise prevails).

Summarv of the Invention.

This invention addresses at least some of the disadvantages set out in the prior art described above. In accordance with the present invention, there is provided a data demodulator for demodulating a received signal which comprises clock generating means for generating a clock signal and a phase detector comprising means for detecting a transition of the received signal. Furthermore, the data demodulator comprises means for recording a potential advancing/retarding adjustment of the clock in order to correct for a detected phase error and means for determining the next to occur of either a transition in the received signal or a transition in the generated clock signal. In addition, means are provided for applying the potential adjustment to the generated clock signal as an advancing adjustment or a retarding adjustment depending upon said next determined transition.Synchronization of the generated clock signal to the received signal is therefore achieved through the control and application of the potential advancing/retarding adjustment.

In a first preferred embodiment, there is provided a 3-level direct FM modem. In a second preferred embodiment, there is provided a modem which utilises a biphase signal.

A modulated 3-level or biphase encoded signal is received by the data demodulator and is immediately filtered through a low pass or band pass filter respectively. With regard to a 3-level signal, a slicer circuit derives two threshold levels from the peak levels of the received filtered signal. Two comparators, within the slicer circuit, utilise these threshold levels in order to splice the received filtered signal into two, dual level received logic signals. These logic signals are ORed together to produce a received data train. In the case of the biphase signal, the signal is sliced into a logic signal according to the levels of the received filtered signal in relation to a datum.

The digital phase lock loop comprises a phase detector and the clock advancing/retarding mechanism. The clock advancing/retarding mechanism provides the means for synchronizing the locally generated clock signal to the received 3-level or biphase signal. The phase detector compares the phase of the data train with the phase of the clock. [Ideally, the clock should be in exact phase with the data train i.e. no phase error exist therebetween]. In the event that a phase error exists, a pulse, proportional to the registered phase error, is generated from the phase detector.

The clock advancing/retarding mechanism may comprise a programmable K-bit counter, an increment/decrement (I/D) circuit and a divide-by-N counter. N is the ratio of the baud rate of the modem to the operational frequency of the phase detector or the K-bit counter and K is an integer which determines the loop gain.

The output from the phase detector is clocked into the K-bit counter at a rate determined by the frequency of a clock input of the K-bit counter. The operational cycle of the K-bit counter can be summarised in that whenever an input from the phase detector is registered, the counter initiates a count, or continues a count, to a predetermined value of K. At a time when the most significant bit (MSB) of the (binary) K-bit counter registers a high logic level, a phase error correction pulse is output from the K-bit counter. When the predetermined value of K has been reached, the counter resets to zero and the output from the K-bit counter drops to a low logic level i.e. logical "0".A falling edge on the output phase error correction pulse causes a correction to be registered and clocked into the input to the I/D circuit and, therefore, the clock advance/retarding mechanism to be initiated.

The I/D circuit has a clock input frequency which is twice that of the phase detector or K-bit counter. Provided that there is no phase error correction registered between the local clock and the data train, the I/D circuit behaves as a normal divide by two circuit.

Thus, the I/D circuit outputs a pulse train with half the frequency of the clock input (i.e. an identical frequency to that of the phase detector's clock input). If a phase error correction is registered and clocked in, the output from the I/D circuit adds/subtracts a pulse to/from the output. The fluctuation in the number of output pulses actuates the clock advancing/retarding mechanism and therefore synchronizes the data and the local clock.

Preferably, a tone detector is included within the data demodulator therein allowing implementation of the invention within full modem applications.

A modem (data demodulator) so designed and described would therefore produce the novel advantages of a low frequency deviation, high performance modem implemented through digital technology. In particular, there would be an improvement in the stability of the data decoder and a corresponding overall improvement in the noise immunity of the modem. Furthermore, initial synchronization of the data to the local clock would be achieved quickly. The transmission signal properties (the encoding method) of a 3-level signal also give rise to the additional benefit of ensuring a sufficient number of zero insertion data transitions for maintaining synchronization in certain protocols.

A preferred embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings.

Brief Description of the Drawings.

Figure 1, illustrates an encoding and transmission timing diagram for a 3-level direct FM signal.

Figure 2, illustrates a block diagram of a data demodulator of a modem which receives a 3-level direct FM signal in accordance with a first preferred embodiment of the invention.

Figure 3, illustrates a simplified representation of a 3-level slicer utilised within the data demodulator of the first preferred embodiment.

Figure 4, illustrates a waveform and timing diagram for a 3-level direct FM signal relating data retrieval to data reception in the data demodulator of the modem of the first preferred embodiment.

Figure 5, illustrates a digital phase lock loop (DPLL) circuit of the modem of the preferred embodiment which implements the recovery and synchronization of either the 3-level direct FM or biphase signals.

Figure 6, illustrates a timing diagram for the synchronization of a delayed clock pulse signal with the data signal of a 3-level direct FM signal in accordance with the first embodiment.

Figure 7, illustrates a timing diagram for the synchronization of an advanced clock pulse signal with the data signal of a 3-level direct FM signal in accordance with the first embodiment.

Figure 8, illustrates a functional block diagram of a phase detector (50) of figure 5.

Figure 9, illustrates an encoding and transmission timing diagram for a biphase signal.

Figure 10, illustrates a waveform and timing diagram for a biphase signal relating data retrieval to data reception in the data demodulator of a modem of an alternative embodiment of the invention.

Figure 11, illustrates a timing diagram for the synchronization of a delayed clock pulse signal with the data signal of a biphase signal in accordance with the alternative embodiment.

Figure 12, illustrates a timing diagram for the synchronization of an advanced clock pulse signal with the data signal of a biphase signal in accordance with the alternative embodiment.

Detailed Descriptions of Preferred Embodiments of the Invention.

In accordance with a first preferred embodiment of the invention, the construction of a 3-level direct FM modem (which is incorporated within a radio) is described. The modem comprises a modulator and a demodulator and operates at a rate of up to 4800 baud (4800 bits per second). It should be apparent to one skilled in the art that this modem could also be employed in other applications e.g. telecommunication networks.

The modulator comprises a digital encoder and a 3-level generator. The encoder samples the data to be transmitted at the rate set by the frequency of a transmission clock, Tx Clock. Referring to figure 1, it can be seen that the encoder produces two logic signals, Tx i and Tx2. These two logic levels are summed together by the 3-level generator to generate a desired output (Radio Tx) from the modulator. The 3-level generator operates on the principle that a summed output logic level of "1" is taken as a mid-level datum transmission level whilst alternate summed output logic levels of "0" take values of the upper and lower transmission levels. As a consequence of this operation, the modulating signal has no direct current (DC) level thus minimising any distortions which may arise on a radio link.

The square wave transmission signal produced by the modulator does not, in this case, require shaping. The shaping of the transmission signal is accomplished by a limiter and a splatter filter within the radio transmitter, the limited bandwidth of the radio link, and the bandwidth of a low pass filter within the data demodulator.

Furthermore, the bandwidth of the low pass filter is wide enough to preserve the integrity of the transmitted signal but narrow enough to eliminate noise. As a result, the bandwidth of the received signal will be approximately half the baud rate. The signal, therefore, has a close resemblance to the signal shown in figure 4. Although this arrangement is not ideal, there is no degradation in the performance of the radio provided that the splatter filter has only small group delay distortions. Since the size of the group delay distortions is related directly to the baud rate of the transmitted data, control of the distortions is accomplished by limiting the baud rate.If a different bandwidth for the radio link was used, and by assuming that the group delay distortions remained relatively small compared with the baud rate, a waveform containing different periods, T, between data transitions would result. The peaks and zero crossing points of the received signal would also alter and would, instead, appear in the middle of these periods. It will become apparent that the synchronization process is not affected by the bandwidth of the communications link provided that the bandwidth is greater than half the baud rate and that there are only small group delay distortions. Indeed, the Rx clock recovery algorithm ensures that the recovered clock is synchronized to its optimum position.

The demodulator of figure 2, is comprised from a low pass filter 22, a 3-level slicer 23 and a decoder and a clock recovery circuit 24. The decoder and clock recovery circuit further comprises a digital phase lock loop (not shown). A received signal (Rx Radio) is filtered through the low pass filter 22. The received filtered signal is coupled to an input of the 3-level slicer 23. Two outputs from the 3level slicer, Rxl and Rx2, couple the slicer 23 to the inputs 26, 27 of the decoder and clock recovery circuit 24. Two further outputs, the recovered clock (RC) and the recovered data (RxData), emanate from the decoder and clock recovery unit 24. An alternative embodiment would allow a tone detector 21, with an input 28 and an output 29, to be incorporated within the demodulator circuit.In such a case, an additional (third) output from the 3-level slicer would couple the slicer 23 to the input of the tone detector 28. The tone detector would allow the alternative embodiment of the invention to operate in full modem applications and, additionally, would allow the logic within the decoder and clock recovery circuit 24 to be reset periodically. This reset cycle would function during a period when the demodulator was inactive i.e. when no Rx Radio data was being received.

The simplified 3-level slicer circuit of figure 3, comprises a peak detector 301, 302, 303, 304, an inverting, unity gain amplifier 306, 307, 308 and two comparators 310, 312. The negative terminal of an a.c. blocking capacitor 300 is coupled in series with the noninverting input of an amplifier 301 of the peak detector 301, 302, 303, 304. The received filtered signal from the low pass filter of figure 2, is coupled to the other end of the blocking capacitor 300.

The positive terminal of a diode 302 is coupled to the output of amplifier 301. Resistors 303, 305 and 306 are coupled in series with the negative terminal of the diode 302. The end of resistor 306 is coupled to the non-inverting input of the inverting amplifier 308.

The output of inverting amplifier 308 is coupled to a first input 309 of the first comparator 310. In addition, a feedback loop taps the output of inverting amplifier 308. This feedback loop routes a proportion of the output through series resistor 307 and then returns the feedback directly to the inverting input of inverting amplifier 308. Resistors 305, 306 and 307 are all of equal value. A second feedback loop is coupled from circuit node 318 to the inverting input of amplifier 301. The negative terminal of a second blocking capacitor 304 is coupled to circuit node 318; the positive terminal is at ground potential.

The received filtered signal 25 is coupled to both the first input 313 of the second comparator 312 and the second input 311 of the first comparator 310 at circuit node 316. The second input 314 of the second comparator 312 is coupled directly to circuit node 317.

The comparators 310 and 312 have outputs Rxl and Rx2 respectively.

These outputs are coupled to the decoder and clock recovery circuit (24 of figure 2) as previously described. A reference voltage (Vref) is coupled to the non-inverting input of inverting amplifier 308. One end of a resistor 315 is coupled between the non-inverting input of amplifier 301 and circuit node 316; the other end is coupled to the reference voltage Vref.

The 3-level slicer 23 derives two threshold levels from the peak level of the received filtered signal. These two threshold levels are fed into the second input 31 of the first comparator 310 and the first input 313 of the second comparator 312 and act as reference voltages. The comparators 310, 312 compare these threshold levels with the outputs from the two amplifiers 301, 308. As a direct result of the comparison between the threshold levels and the amplifier outputs, 2-level received logic signals Rxl and Rx2 are produced at the outputs of comparators 310 and 312 respectively.

With reference to figure 4, the logic signals Rxl and Rx2 from the 3-level slicer 23 are ORed (or XORed) together in the decoder and clock recovery circuit 24 to produce a decoded DATA' pulse train.

Data retrieval of the initial data transmission is instigated through the synchronization of the DATA' pulse train and a clock pulse (not shown). The clock pulse is generated from a local clock located within the demodulator of the modem. Figure 5, illustrates the digital phase lock loop (DPLL) through which this synchronization is implemented.

The digital phase lock loop comprises a phase detector 50, a programmable K-bit counter 51, an I/D (Increment/Decrement) circuit 52 and a divide-by-N counter 55. The DATA' signal is responsive to a first input of the phase detector 50. In addition, phase detector 50 has two outputs (INC and DCR), a second input and a clock input. Outputs INC and DCR are respectively coupled to a first and a second input of the K-bit counter 51. The first input of the K-bit counter is the up (u) input and the second input is the down (d) input. The K-bit counter has two outputs, INCR and DECR, and a further clock input. The two outputs of K-bit counter 51 are coupled to a first and a second input of the I/D circuit 52. An output from the I/D circuit 52 is coupled to a clock input of the divide-by-N counter.A recovered clock signal, RC, is output from the divide-by N counter 55 and is coupled to the second input of the phase detector 50. A first clock signal (of frequency N x baud rate) is applied to the clock inputs of the phase detector 50 and the K-bit counter 51. A second clock signal (of frequency 2N x baud rate) is applied to a clock input of the I/D circuit 52. N is the ratio of the counter clock to the baud rate. In the description of the first preferred embodiment, this ratio is taken to be 192.

In the application of modems, the synchronization between the DATA' signal and the local clock within the demodulator is significant. Furthermore, in the event that noise is present on the radio or communications link, synchronization becomes increasingly important.

Returning to Figure 4, the illustration of the received filtered signal. For ease of analysis, this received signal is assumed to be composed from fractions of sinusoids. The assumption is made only to simplify the description of the clock recovery mechanism.

Examination of the waveform of Figure 4, reveals that a logic level of "0" have a corresponding sinusoid of period 2T. However, two consecutive logic levels of "0" has a reduced sinusoid period of T. In this case, T is the reciprocal of the baud rate of the modem.

The received filtered signal is input into the 3-level slicer. The slicer generates signals Rxl and Rx2. The threshold levels utilised by the 3-level slicer in order to produce the outputs Rxl and Rx2 are located at half amplitude positions above and below the mid-point datum of the sinusoidal received filtered signal. Therefore, logic levels of "1" are generated alternately on the Rxl and Rx2 outputs at the transition of the sinusoid above the modulus of the threshold levels.In the instance where a (singular) transmitted logic level of "0" occurs, the pulse duration of a Rx output is

However, in the case when two consecutive logic "0"s have been initially transmitted, there is a delay between the first and second data bit of duration

For the described sinusoidal received filtered signal, the optimum position for the recovered clock (RC) with respect to the DATA' pulse train i.e. the ORed Rxl and Rx2 signals, is illustrated in figure 4, The rising edges of the recovered clock (RC) should be, ideally, aligned with the transitions of the DATA'. Conversely, the falling edges of the recovered clock (RC) are aligned with (i) the peaks of the transmitted signal when a logic "0" is received and (ii) with the datum line transition at which point a logic "1" is received.

The exception to this general case occurs when two consecutive logic "0"s are initially transmitted. In this instance, the rising edge of the Rx clock appears in the middle of the data transition. Clearly, it can be appreciated that the lowest probability of error in data decoding occurs at the falling edge of the aligned recovered clock (RC) i.e.

when there is a zero phase error between the DATA' and the recovered clock.

In general, the objective of the phase detector (50 of figure 5) is to extract the phase error between the recovered clock (RC) and the DATA'. Furthermore, the phase detector should produce a signal (i) which carries this information and (ii) upon which the correction algorithm is based. As previously described, the phase detector of the first preferred embodiment has two outputs (INC and DCR).

These outputs are responsible for the transmission of pulses which signify a detected phase error. A correction pulse of duration proportional to the phase error is generated on the INC output when the recovered clock (RC) is delayed relative to DATA'. Similarly, a correction pulse of duration proportional to the phase error is generated on the DCR output when the recovered clock (RC) is advanced relative to DATA'.

The transitions of the received filtered signal offer the only tangible source of information regarding the phase error. These transitions trigger the phase detector mechanism. This mechanism then makes the necessary adjustments to the recovered clock (RC).

Referring to figure 8, the phase detector 50 comprises a control circuit 80 and an up/down counter 81. The control circuit 80 has a first input responsive to the DATA' signal, and a second input responsive to the recovered clock (RC) signal. The control circuit 80 has a first and a second output, INC and DCR respectively; these outputs correspond to the output INC and DCR of the entire phase detector 50. A third and a fourth output couple the control circuit 80 to a first (u/d) and a second (reset) input of the counter 81. A 7-bit data bus 82 couples the counter 81 to the control circuit 80. A third (clock) input is present on the control circuit 80. A third (clock) input is also present on counter 81. Both of the clock inputs of the counter and control circuit are coupled to a clock 83, which operates at a frequency of 192 times the baud rate.The control circuit 80 controls the INC and DCR outputs and the operation of the up/down counter 81. Although the control circuit 80 and the counter 81 were designed specifically for implementation with PLD (Programmable Logic Device) technology, the relatively low number of states within the phase detector allow other types of digital hardware to be used e.g. gate arrays.

The size of the up/down counter 81 depends upon the ratio between the Rx clock and the counter's clock frequency 83. This ratio determines the resolution of the phase detector 50 and the resolution of the clock recovery mechanism in general. In the first preferred embodiment, where the clock frequency of the counter 83 is 192 times the baud rate, a 7-bit counter is required to produce a count of 96 cycles i.e. a half cycle of the recovered clock (RC). It will become apparent that the size of the up/down counter, and hence the duration of the count cycle, depends upon the method chosen to implement the generation of the correction pulses. Theoretically, the count cycle duration could lie anywhere within the range of T -3 < x < 1T where T is the transition period between successive logic levels.A value for the up/down counter 81 of half a recovered clock cycle is preferred. It should be apparent to one skilled in the art that other baud rates and clock frequencies could be employed within the scope of the invention.

In the case when consecutive logic "0"s do not appear in the DATA', the time periods (terd and tera) between the transitions of the DATA' and the rising edges of the recovered clock (RC), represent the phase error (refer to figures 6 and 7). When the recovered clock is delayed relative to the DATA' transition (figure 6), the INC output generates a correction pulse (terd) which commences at any DATA' transition edge and terminates on the recovered clock's rising edge.

When the recovered clock is advanced relative to the DATA' transition, the rising edge of the clock occurs before the data transition. A delay pulse (not shown), generated using the counter 81, commences at the DATA' transition and has a duration of exactly half the recovered clock cycle (RC) and therefore represents the entire high logic period. The time period between the recovered clock's falling edge and the falling edge of the generated delay pulse is proportional to the phase error. Therefore, the DCR output registers a correction pulse (terra) which commences on the falling edge of the recovered clock and terminates on the falling edge of the generated delay pulse.

As an alternative to the preferred method of generating a half clock cycle delay pulse, generation of the delay pulses and the correction pulses can also be accomplished by the use of the up/down feature of the counter 81. If, for example, the counter initiates counting at the rising edge of the recovered clock (RC) and finishes counting at the rising edge of DATA', the count represents the exact time duration for the applied correction pulse on the DCR output. By reversing the count sequence and counting to zero, the counter can be used to time the correction pulse duration and output a pulse on the DCR output.

In the case when consecutive logic "0"s are generated in the received filtered signal, a different correction algorithm is required.

By assuming that the recovered clock's rising edge occurs within T/3 (the delay (transition) period between the first and second logic "0"), the phase error correction is the period between the falling edge of the first logic "0" and the recovered clock's rising edge (tel), less the period between the recovered clock's rising edge and the rising edge of the second logic "0" in the DATA' (te2). The production of two correction pulses are required in order to eliminate the phase error and synchronize the recovered clock RC to the centre of the delay period between the first and second logic "0". N.B. The actual phase error is given by 8t = (tes; te2) 2 where 8t is the actual phase error.

A first correction pulse of duration tel is initially generated on the INC; the algorithm interprets the RC signal to be delayed relative to the DATA'. At the rising edge of the recovered clock (RC), the algorithm initiates a count on counter 81 which corresponds to the case of an advanced recovered clock. Since the time period between consecutive logic "0"s is T/3, a DATA' transition (a rising edge) occurs before the delay pulse has counted half a recovered clock period. In addition, the DATA' transition causes the count to immediately reverse and count down to zero. A DATA' transition occurring before the end of the (half RC period) count signifies that two consecutive logic "0"s have been located and, consequentially, a second correction pulse must be applied in order to synchronize the recovered clock (RC).The second correction pulse is generated on the DCR output at the rising edge of the DATA' transition and has a duration of te2. The duration te2 is timed by the count down sequence initiated by the DATA' transition. Therefore, the generation of these two pulses achieves the desired synchronization (i.e. a zero phase error) and, it should be noted that, this process is true regardless of whether the recovered clock (RC) is delayed or advanced with respect to the rising edge of the DATA'. If the count cycle reaches its specified number (96 in the first preferred embodiment) and a DATA' transition has not occurred, the counter immediately resets to zero and awaits the next clock trigger. A count cycle of a half period of the RC clock is sufficiently long so as to eliminate the chance of error in the interpretation of the received filtered signal. Although, it should be apparent to one skilled in the art that any period within the range T/3sx < 1T, where T is the transition period between successive logic levels, would suffice.

In conclusion, the up/down counter performs three count monitoring functions: (i) an incrementing count from the data transition in the case of an advanced recovered clock (RC); (ii) an incrementing count from the recovered clock's rising edge in the case of a delayed recovered clock; and (iii) a decrementing count when two consecutive logic "0"s are detected. It should be apparent to one skilled in the art that other methods of pulse generation are also possible.

Returning to figure 5, the operation of the digital phase lock loop, and more specifically the operation of the components therewithin, is described. The function of the programmable K-bit counter 51 is to produce a carry signal or a borrow signal on the INCR output or the DECR output respectively. The K-bit counter 51 can be considered as having an up/down binary bit count function with a bit count of K. Initial conditions set the value of this up/down count at zero. When the phase detector 50 detects a phase error, the K-bit counter registers a high logic input on either one of the INC or DCR inputs. Whilst the high logic input persists, the up/down count function of the K-bit counter operates.

In the case of a delayed clock pulse, the INC input will be at a high logic level for a duration proportional to the phase error. A high logic level on the INC input causes the up/down function of the K-bit counter to increment its count towards a predetermined bit value of K. If the INC input drops to a low logic level, indicating that no further phase error has been detected, the value reached by the up/down function is retained and consequentially used as a new start point. If an advanced clock is now detected by the phase detector 50, the DCR input to the K-bit counter 51 rises to a high logic level. This causes the up down count function to decrement the count from the retained start position; this retained start position could be anywhere within the range of -K < x < +K.When the up/down function reaches a threshold level of +K/2, the count function utilises the most significant bit (MSB) of the K-bit counter 51 to initiate a phase correction pulse. At a value of +K/2, the INCR output rises to a high logic level. Conversely, at a value of -K/2, the DECR output rises to a high logic level. The INCR or DECR outputs remain at high logic levels until a value of +K or -K has been reached respectively. This is true regardless of whether the count value has subsequently dropped below the +K/2 threshold. Therefore, in certain scenarios, both outputs can simultaneously be at a high logic levels. When a value of +K has been reached, the K-bit counter 51 resets its count function to zero and drops the output of either the INCR or DECR output to a low logic level (logical "0") accordingly.It should be apparent to one skilled in the art that the threshold levels could lie anywhere within the range of -K < x < +K.

The predetermined value of K and the use of the up/down count function of the K-bit counter 51 ensure economical use of the received phase error data. The up/down count function provides a means for compensating for small, successive variations in the type of phase error registered. Therefore, the advancing or retarding of the recovered clock RC only occurs when synchronization between the DATA' signal and the recovered clock has drifted significantly and a correction is justified. Furthermore, the predetermined value of K must be carefully selected since it is the numeric value of K which determines the loop gain characteristics of the digital phase lock loop. Decreasing the value of K, increases the loop gain which therefore decreases the synchronization time of the recovered clock (RC) with the received DATA'.This action has the consequence of decreasing the stability of the digital phase lock loop and therefore rendering the modem more susceptible to noise. Similarly, increasing the value of K, decreases the loop gain. By decreasing the loop gain, the synchronization of the recovered clock and the received DATA' increases, therein increasing the stability of the phase lock loop.

The I/D circuit 52 has two modes of operation. The first mode is operational when there are no signal inputs on the INCR or DECR inputs. This idle mode restricts the I/D circuit to operating as an ordinary divide by two circuit. The frequency of the applied clock pulse is therefore twice the frequency of the clock pulse applied to the phase detector circuit and the K-bit counter i.e. 2 x 192 x baud rate (1.8432MHz). In the second mode of operation, the addition or subtraction (blocking) of clock cycles occurs at the output of the I/D circuit 52 as a result of a high to low logic transition on either the INCR or DBCR input i.e. the addition or subtraction of a clock cycle is triggered by a falling edge on either input.Each falling edge on the INCR input adds an extra clock cycle to the output, while a falling edge on the DECR input cause the subtraction of a clock cycle from the output. Thus, the recovered clock is advanced or retarded by an calculated amount according to the phase error.

The clock input of the divide-by-N counter 55 receives the corrected phase pulse from the output of the I/D circuit. The divide-by-N function translates the information contained within the frequency and then reproduces the synchronized recovered clock.

The addition or subtraction of every cycle has the result of changing the specified baud rate by 1/192 baud (~0.5%).

In summary, the phase error between the rising edge of the recovered clock and DATA' logic transition is registered by an output, proportional to the phase error, on either the INC or DCR outputs from the phase detector 50. On registering an input on either the INC or DCR inputs, the K-bit counter 51 begins to count to a predetermined value of K. The duration of this count depends upon the duration of the registered phase error. At a threshold level (it/2) an output is generated on the DECR or INCR outputs of the K-bit counter 51. This output remains at a high logic level until the count function within the K-bit counter reaches a value of +K. At this juncture, the INCR or DECR output drops to a low logic level and the count function resets to zero.A falling edge on either the INCR or DECR input to the I/D circuit 52, respectively adds or subtracts (blocks) a clock cycle to or from the output of the I/D circuit. This has the effect of advancing or retarding the recovered clock (RC), thereby synchronizing the DATA'. If no phase error is registered by the phase detector 50, no outputs are registered on the INC or DCR outputs and, consequentially, the I/D circuit 52 behaves as a normal divide by two circuit.

There are two factors which have to be considered when designing the digital phase lock loop: synchronization and stability.

In order to achieve fast synchronization, a synchronizing frame (sync word) is transmitted after the preamble. In the first preferred embodiment, a sync word with a transition every bit e.g. 101010...

has proved to be of greatest benefit in obtaining initial synchronization. However, it should be apparent to one skilled in the art that other sync words e.g. those incorporating series such as the Barker series, could be used. In principle, once the digital phase lock loop has synchronized (locked) on to the sync word, no further adjustments in the received clock pulse are necessary. Thus, a state of high stability is achieved.

The duration of the synchronizing frame depends upon the length of time taken for synchronization to be obtained from an initial condition of total phase misalignment i.e. when the Rx clock is in anti-phase with the received data. The time for synchronization to occur is dependent upon the numeric value for K within the K-bit counter 51. Theoretically, the time for synchronization to occur from a condition of clock anti-phase and with the use of a synchronizing frame (sync word), is shown in Table 1 Table 1.

Synchronization Timet Numeric value Equivalent Time in ms at of K. Rx Clock Cycles. 4800 baud.

4 19 4 8 31 6.5 16 80 17 32 171 35.5 t Synchronization Time is defined as the time period for the Rx clock to adjust itself from a position of anti-phase to a position of zero phase error with a resolution of 0.5%.

Experimentation shows that the stability of the digital phase lock loop contributes to the decoder's overall performance. In fact, stability is also related to the numeric value of K. Table 2, illustrate empirical results, normalised to a value of the RF level at a receiver, for a modem with a bit error rate (BER) of 10-6, given that K=32.

Table 2.

Numeric value RF Level of K. (dB).

4 5 8 2 1 6 0.3 - 1 32 0 The results demonstrate that in order to produce the same BER for a numeric value of K=4, there is an increase in the power consumption of the receiver of 5dB.

By taking these considerations into account, it is desirable to have the programmable K-bit counter 51 initially operating with a low K value e.g. 4, for fast synchronization, and then with a high K value e.g. 32, to achieve high stability and low power consumption.

Furthermore, experiments have shown that when a synchronization sequence is transmitted at any given SNR, better results (lower values) for the BER are obtained for small values of K (e.g. 4) compared with the results obtained for high values of K (e.g. 32) when any other random sequence is transmitted.

Tests have shown that a 3-level modem in accordance with the first preferred embodiment has a bit error rate (BER) of 10-6 at a radio frequency (RF) level of -llOdBm (or, alternatively, a BER of 10-6 at -l07dBm and with a RF carrier deviation of +3kHz) viz 10-6 BER at -102dBm for a (typical) 2-level modem.

The construction of a modem employing encoding and recovery techniques for biphase signals will now be described in accordance with an alternative embodiment of the invention. The modem comprises a modulator and a demodulator and operates in a radio communications link at a rate of up to 2400 baud.

Modulation of a signal occurs in the modulator of the modem.

With reference to figure 9, a sine wave Radio Txb, constructed from sinusoids of varying period, represents a logic (data) train in an encoded transmission format. A clock TxCLKb within the modulator codes the logical "l"s or "0"s into the transmission format by converting a logical "1" to a half sinusoid and a logical "0" to a full sinusoid. Therefore, a logical "1" has a sinusoidal period of 2T whilst a logical "0" has a sinusoidal period of T. [N.B. T is the reciprocal of the frequency of the TxCLKb]. The transition from adjacent bits occurs at the peaks of the sine wave, thus maintaining phase continuity, and is synchronised to, in this case, the falling edges of the TxCLKb. It should be apparent to one skilled in the art that either edge of the TxCLKb would suffice for encoding purposes.

Referring to figure 10, an encoded sinusoidal received signal Radio Rxb is demodulated in a demodulator of the modem. The encoded sinusoidal received signal Radio Rxbis filtered through a band pass filter (not shown) and is sliced into a logic signal DATAb by a slicer (not shown). A datum level, located at the mid-point between the peaks and troughs of the sinusoidal received signal Radio Rxb, determines the logic levels of the logic signal DATAb.

Any value of the Radio Rxb signal above the datum corresponds to a logical "1" whereas any value of the Radio Rxb signal below the datum corresponds to a logical "0". Analysis of the intrinsic qualities of the biphase signal reveals that transmitted logical "l"s can be distinguished from transmitted logical "0"s through the comparison of any two consecutive peaks of the sinusoidal received signal Radio Rxb. There is a change in the peak value of Radio Rxb when logical "l"s are received whereas there is no change in the peak value in the case of received logical "0"s. This is a direct consequence of the different sinusoidal periods of the encoded logic levels.Therefore, a decoded received logic signal RxDb can be obtained by exclusively ORing (XORing) a present value of the DATAb logic signal with its immediately preceding DATAb logic signal (DLast) i.e. a comparison between the decoded DATAb logic signal and the DLast signal.

Sampling of the DATAb and DLast logic signals occurs at a rate determined by the frequency of a locally generated clock RxCLKb.

The sampling (comparison) of the logic signals DATAb and DLast occurs, in this embodiment, at the falling edges of the locally generated clock RxCLKb. It should be apparent to one skilled in the art that sampling could be implemented, alternatively, at the recovered clock's (RxCLKb) rising edge. Furthermore, sampling of the DATAb logic signal coincides with the peaks of the encoded sinusoidal received signal Radio Rxb; this ensures that the probability of an interpretational error of the received data is at a minimum. [N.B. hatched areas 100 indicate initial time or clock periods which cannot be interpreted because of the lack of preceding logic signals on either DATAb and/or DLast].

In accordance with the alternative embodiment of the invention, a clock recovery method is provided which is based upon the digital phase lock loop circuit of figure 5. The operation of the DPLL, and the components contained therewithin, is substantially identical to that which has been previously disclosed. However, the implementation and operation of the phase detector circuit (50 of figure 5) is based upon an algorithm specifically designed for a biphase signal.

Referring again to figure 10, the optimum position of the RxCLKb is shown. The rising edges of the RxCLKb are aligned with the data transitions to a logical "1" with respect to either the Radio Rxb or DATAb signals. In the case of logical "0"s, the rising edges of the of the RxCLKb are aligned at the peaks or troughs of the Radio Rxb signal. Provided that the alignment of the RxCLKb and Radio Rxb or DATAb signals is as stipulated, no phase error is detected by the phase detector circuit (50 of figure 5).

Transitions of the DATAb signal relative to the locally generated clock RxCLKb provide the only source of information pertaining to the phase error. Therefore, it is these transitions which trigger the phase adjustment mechanism of the digital phase lock loop. There are four specific cases of interest relating the phase of the locally generated clock RxCLKb to the relative position of the DATAb signal.With reference to figures 11 and 12, these are: a) a logical "1" has been received and a recovered clock RCb has been delayed relative to the DATAb transition; b) a logical "0" has been received and the recovered clock RCb has been delayed relative to the DATAb transition; c) a logical "1" has been received and the recovered clock RCb has been advanced relative to the DATAb transition; and d) a logical "0" has been received and the recovered clock RCb has been advanced relative to the DATAb transition.

In order that the preferred embodiment of the phase detector circuit (50 of figure 8) can implement the algorithm specifically designed in accordance with the alternative embodiment of the biphase modem (data demodulator), modifications to the control circuit 80 and the up/down counter 81 are required. Inputs DATA' and RC to the control circuit 80 are replaced by inputs DATAb and RCb respectively. Furthermore, outputs INC and DCR are replaced by outputs INCb and DCRb respectively. In addition, the clock input 83 has a reduced operating frequency determined by the ration of the Divide by NCounter's clock frequency to the baud rate of the biphase modem. The second input to the up/down counter (previously the reset input) is replaced by an input representing the Most Significant Bit (MSB) of the data bus.This MSB input is coupled directly to a corresponding output located on the control circuit 80. As in the first preferred embodiment, the control circuit 80 and the counter 81 were designed specifically for implementation with PLD (Programmable Logic Device) technology.

However, the relatively low number of states within the phase detector allow other types of digital hardware to be used e.g. gate arrays. The size of the up/down counter 81 depends upon the ratio between the RxCLKb and the counter's clock frequency 83. This ratio determines the resolution of the phase detector 50 and the resolution of the clock recovery mechanism in general.

Furthermore, the up/down counter 81 has a predetermined maximum count cycle of half the recovered clock (RCb) cycle (i.e.

RCb/2). Moreover, it is the up/down counter 81 which registers the detection of a phase error and initiates the correction process therefor.

Referring to figures 11 and 12, and the specific operation of the phase detector circuit (50 of figure 3). In the instance when a logical "1" has been received and the recovered clock RCb has been delayed relative to the DATAb transition, the up/down counter 81 sequentially counts between the period of the transition of DATAb and the recovered clock's rising edge RCb. At the rising edge of the RCb the count terminates and the count value is retained. This retained count value represents the time error terW between DATAb and the RCb. At the falling edge of the RCb clock pulse, the counter 81 counts down to zero from the retained count value. At the same instant as the counter 81 begins to count down to zero, the INCb output rises to a high logic level.This output remains high for the duration of the count down to zero.

When a logical "0" has been received and the recovered clock RCb has been delayed relative to the DATAb transition, the up/down counter 81 starts a sequential count for a period between the DATAb transition and the rising edge of the RCb. Upon reaching the RCb transition, the count, which is greater than a predetermined datum count value is retained. This datum count value is, for example, half the value of the maximum count. Since in the case of logical "0"s the RCb is to be aligned in the middle of the DATAb signal, the time error between the RCb and DATAb is represented by the count period between the half maximum counter value (the datum count value) and the proceeding RCb transition i.e. tern. At the proceeding DATAb transition, a value of half the maximum count value (datum count value) of the counter 81 is instantaneously subtracted from the retained count value.This subtraction can be implemented by reverting the MSB (Most Significant Bit) of the counter back to zero, although it would be obvious to one skilled in the art that other alternative methods could be applied. Therefore, a new retained value, equivalent to the time error tern, remains. The counter begins to count down to zero from the new retained value.

Simultaneously, the INCb output rises to a high logic level at the beginning of the count down sequence and remains at this level until zero has been reached. A correction pulse proportional to the phase error is consequentially registered by the K-bit counter (51 of figure 5).

In the case when a logical "1" is received and the recovered clock RCb is advanced relative to the DATAb transition, a time error tery exists between the rising edge of the recovered clock RCb and the DATAb transition. The up/down counter 81 initiates a sequential count from the DATAb transition. This count lasts for exactly half a RCb cycle i.e. the counter continues to count to its predetermined maximum value, loops around to zero and then awaits the next DATAb transition. The time error tery is therefore represented by the period between the falling edge of the following RCb and the remaining sequential count required to reach the maximum predetermined count value. On the falling edge of the recovered clock RCb, the DCRb output rises to a high logic level and remains at this level until the counter loops back to zero i.e. for a period of tery.

Finally, in the case when a logical "0" is received and the recovered clock RCb is advanced relative to the DATAb transition, a time error terz exists therebetween. The up/down counter 81 initiates a sequential count on the DATAb transition. This count terminates on the RCb's rising edge and, at this juncture, has a value smaller than the predetermined datum count value. The count value reached during this period is retained for later use. At the next DATAb transition, a value of half the maximum predetermined count value (the datum count value) of the counter 81 is instantaneously added (or subtracted) to the retained value to produce a new combined start value. An addition of exactly half a recovered clock cycle RCb may be obtained by changing the value of the MSB to a logical "1". Simultaneously the DCRb output rises to a high logic level and the counter 81 begins to increment its count from the new combined start value. The magnitude of the count which remains between the new combined start value and the maximum predetermined count value represents the time error terz.

At the instance when the counter 81 reaches its maximum value, the DCRb output drops to zero and the counter loops back to zero to await another DATAb transition.

In principle, the design considerations of synchronization time and stability for the digital phase lock loop remain the same for the biphase signal embodiment. However, inspection of the properties of the biphase signal reveals that in an initial instance when digital phase lock loop is unlocked and when logical "0"s are present in the received signal Radio Rxb, the digital phase lock loop is prone to incorrectly synchronising itself to a 900 phase error. Therefore, a synchronising sequence comprising all logical "l"s can be utilised in order to guarantee synchronization of the phase lock loop. Such a synchronising sequence facilitates synchronization even in the worst possible case i.e. an initial condition of anti-phase between DATAb and the RxCLKb.

In summary, an embodiment of the invention employing a biphase signal makes efficient use the digital hardware by using one up/down counter to extract phase error information in all of the above eventualities. Since the phase detector extracts the exact phase error from the biphase signal, there is a minimal ripple within the recovered clock signal RCb. Furthermore, the algorithm implemented by the demodulator exhibits "clean" behaviour in that each synchronization process commences at a data transition and terminates when the counter reaches zero. Therefore, there is no need for an initialisation and the recovery of illegal states becomes insignificant.

Tests have shown that a biphase modem constructed in accordance with the alternative embodiment has a bit error rate (BER) of 10-6 at a radio frequency (RF) level of -1 I2dBm (or, alternatively, a BER of 10-6 at -l09dBm and with a RF carrier deviation of +3kHz). Moreover, the biphase signal modem efficiently utilises the radio spectrum between above the sub-audio range i.e.

300-3300Hz, and is therefore suitable for operation within a wide range of radio systems. Furthermore, the biphase modem proves to be compatible with the existing trunked radio systems and voice channel radio links. Therefore, a biphase modem constructed in accordance with the alternative embodiment offers the facility of being able to increase the communication rate of existing radio systems at a reduced integration cost.

It can be appreciated that an invention so designed and described would produce the novel advantages of a high performance, low frequency deviation modem implemented through digital technology. In addition, the implementation of the digital phase lock loop through semiconductor technology would lead to a reduction in manufacturing costs for the data demodulator.

Furthermore, the synchronization process, employed by the decoder, is very stable in the presence of noise and channel amplitude distortions and therefore offers improved noise immunity. This beneficial characteristic is derived from the ability to vary the value of K in the K-bit counter and hence the loop gain of the digital phase lock loop. Moreover, the initial synchronization of the data and the local clock is achieved quickly (typically within 4ms of receiving a signal which is in anti-phase with the initially generated clock position). A further benefit arises from the encoding methods used by the modem. The transmission signal properties of a 3-level signal (the encoding method) guarantees a sufficient number of zero insertion data transitions for maintaining synchronization in certain protocols e.g. HDLC protocol. Additionally, the transmission properties of the biphase signal modem enable high speed data communication at 2400 baud to be implemented by existing trunked radio systems or radio links incorporating repeaters without the necessity of extensive system modification.

It will, of course, be understood that the above description has been given by way of example only, and that modifications of detail can be made within the scope of the invention.

Claims (21)

Claims.

1. A data demodulator for demodulating a received signal, comprising: a clock generating means for generating a clock signal (RC, RCb); a phase detector (50) comprising means for detecting a transition of the received signal; means (81) for recording a potential advancing/retarding adjustment of the clock to correct for phase error detected by the phase detector; means for determining the next to occur of a transition in the received signal and a transition in the clock signal; and means for applying the potential adjustment to the generated clock signal (RC, RCb) as an advancing adjustment or a retarding adjustment depending upon the next to occur of said received signal transition and said clock signal transition, thereby to control the clock generating means to synchronize the generated clock signal (RC, RCb) to the received signal (DATA', RxDb).

2. A data demodulator according to Claim 1, wherein the recording means comprises a counter arranged to count from a transition in the received signal to a transition in the clock signal and to store a resulting count value.

3. A data demodulator according to Claim 1 or 2, for demodulating a received biphase signal, characterised in that the demodulator comprises: means for detecting a transition through a zero level of the received signal (24); means for detecting a sign change in the peak level of the received signal (24) between consecutive clock periods of the generated clock signal (RCb); and means for applying the adjustment to the generated clock signal (RCb) as an advancing adjustment or a retarding adjustment depending upon the detection or otherwise of a sign change.

4. A data demodulator according to Claim 1 or 2, for demodulating a received 3-level signal, characterised in that the demodulator comprises: means for detecting a first change in level of the received signal (23, 24); means for detecting a second change in level of the received signal (23, 24); means for determining whether the clock transition is to be synchronized to the first level change or the mid-point between the first and second level changes (80, 81); and means for correcting for the advance/retard adjustment if the the clock transition is to be synchronized to the mid-point (51, 52, 55).

5. A demodulator according to any preceding Claim, wherein the advance/retarding means (51, 52, 55) further comprises a programmable bit counter means (51) operating in a first mode and a second mode and generating an output signal responsive to the detected phase error and a bit counter value of K: means for setting a relatively low value for K in the first mode allowing, initially, fast synchronization of the data; and means for setting a relatively high value for K in the second mode, which stabilises the performance of the data decoder and which is operational immediately after the first mode establishes synchronization of the data.

6. A demodulator according to Claim 5, wherein the programmable (K) bit counter means (51) is characterised in that: an output signal (INCR, DECR) is generated when an input signal (INC, DCR, INCb, DCRb), from the phase detector (50), signifies that a phase error exists between the received signal (DATA', DATAb) and the clock signal (RC, RCb).

7. A demodulator according to any preceding Claim, wherein the DPLL further comprises a dual mode increment/decrement (I/D) circuit means (52) is characterised in that: when no phase error exist, a first output signal has a frequency of half the clock input signal (54); and for every two periods of the clock (54) which have a corresponding phase error registered on a first input (INCR, DECR), a phase correction pulse is added to or subtracted (suppressed) from a second output signal having an initial frequency of half the clock input signal (54).

8. A method of demodulating a received signal comprising the steps of: generating a clock signal (52, 54, 55); detecting a first transition in a received signal; detecting the presence of phase error between the generated clock and said transition; recording a potential advancing/retarding adjustment of the generated clock to correct for phase error; detecting the next to occur of a transition in the received signal or a transition in the generated clock signal; and applying an advancing adjustment or retarding adjustment of the clock signal (51, 52, 55) to correct for phase error depending upon the next to occur of said received signal transition or said generated clock signal transition.

9. A method of demodulating a received 3-level signal according to Claim 8, comprising the steps of: generating a clock signal (51, 52, 55); detecting a first change in level of the received signal (23, 24); making an advancing or retarding adjustment of the clock signal to correct for phase error (51, 52, 55); detecting a second change in level of the received signal (23, 24); determining whether the clock signal transition is to be synchronized to the first level change or the mid-point between the first and second level changes (80, 81); and correcting for the advance/retard adjustment if the the clock signal transition is to be synchronized to the mid-point (51, 52, 55).

10. A method of demodulating a received 3-level signal according to Claim 9, wherein an advance adjustment (terd, tel) is made to the clock signal (RC) whenever a falling transition of the received 3-level signal precedes a clock signal transition, with the adjustment duration calculated as a function of the time period (terd, tel) therebetween.

11. A method of demodulating a received 3-level signal according to Claim 9 or 10, wherein a retarding adjustment or correction (te2) is made to the clock signal (RC) whenever a rising clock signal transition precedes the received signal transition, with the adjustment duration calculated as a function of the time taken for a counter (81) to sequentially count from the rising edge of the advanced clock signal to the signal transition.

12. A method of demodulating a received 3-level signal according to Claim 9, 10 or 11, wherein a counter (81) invokes the generation of a delay pulse, of a predetermined count duration, whenever a clock signal transition precedes the received 3-level signal, and a retarding correction (terra) is made to the advanced clock (RC) in the period between the next transition of the advanced clock signal (RC) and the end of the delay pulse.

13. A method of demodulating a received signal according to Claim 11 or 12, wherein the counter (81) has a predetermined count cycle specified within the range of at least T/3 periods for a logic transition but less than 1T period for the logic transition.

14. A method of demodulating a received 3-level signal according to Claim 13, wherein consecutive and identical logic levels in the received 3level signal are acknowledged by the data demodulator if a logic transition on the 3-level signal is detected before the termination, and consequential reset, of the predetermined count cycle.

15. A method of demodulating a received 3-level signal according to Claim 11, wherein the counter (81) reverses its direction and counts to an initial datum upon reaching the signal transition and a - correction is made during the reverse count.

16. A method of demodulating the received biphase signal according to Claim 8, wherein an advance adjustment (tern, terx) is made to the clock signal (RCb) whenever a transition of the received signal (DATAb) precedes a clock signal (RCb) transition; the adjustment duration being calculated as a function of the time period (tern, tery) therebetween and characterised in that: : a) a counter (81) commences a sequential count, from an initial count value, at a data signal (DATAb) transition; b) the counter (81) terminates the count at a the next clock signal (RCb) transition and temporarily retains the count value; c) an immediately proceeding clock transition re-initiates and reverses the sequential count towards they initial count value and thereby implements the adjustment duration which is proportional to the time period (tern); d) the adjustment duration terminates when the counter returns to said initial value.

17. A method of demodulating the received biphase signal according to Claim 8 or 16, wherein an advance adjustment (tern, tern) is made to the clock signal (RCb) whenever a transition of the received signal (DATAb) precedes a clock signal (RCb) transition; the adjustment duration being calculated as a function of the time period (tern, tern) therebetween and characterised in that: a) a counter (81) commences a sequential count, from an initial count value, at a data signal (DATAb) transition; b) the counter (81) terminates the count at the next clock signal (RCb) transition and temporarily retains the count value; c) the combination of a data signal (DATAb) transition and a retained count value which supersedes a predetermined count value, simultaneously:: generates the production of a new count value through the subtraction of the predetermined count value from the retained count value; implements the adjustment duration proportional to the time period (tern); and reverses and re-initiates the sequential count from said new count value towards the initial count value; d) the adjustment duration terminates when the counter returns to said initial value.

18. A method of demodulating a received biphase signal according to Claim 8, 16 or 17, wherein a retarding adjustment (tery, terz) is made to the clock signal (RCb) whenever a clock signal (RCb) transition precedes the received signal (DATAb) transition; the adjustment duration being calculated as a function of the time period (tern, tern) therebetween and characterised in that:: a) a counter (81) commences a sequential count, from an initial count value, towards a predetermined maximum count value at a data signal (DATAb) transition; b) the next clock signal (RCb) transition initiates the adjustment duration proportional to the time period (tery); c) upon reaching the predetermined maximum count value or said initial count value, the adjustment duration, proportional to the time period (tery, terz), is terminated and the counter is reset to said initial count value.

19. A method of demodulating a received biphase signal according to Claim 8, 15, 16 or 17, wherein a retarding adjustment (tery, tern) is made to the clock signal (RCb) whenever a clock signal (RCb) transition precedes the received signal (DATAb) transition; the adjustment duration being calculated as a function of the time period (tern, tern) therebetween and characterised in that: a) a counter (81) commences a sequential count, from an initial count value, towards a predetermined maximum count value at a data signal (DATAb) transition; b) the combination of a clock signal (RCb) transition and a count value which has not superseded a predetermined count value temporarily halts and retains the count; c) at the next data signal (DATAb) transition: : a new count value is generated by an arithmetic operation. involving the retained count value and the predetermined count value; the adjustment duration, proportional to the time period (tern), is actuated; and, simultaneously, the sequential count is re-initiated from said new count value; c) upon reaching the predetermined maximum count value or said initial count value, the adjustment duration, proportional to the time period (tery, terz), is terminated and the counter is reset to said initial count value.

20. A method of demodulating a received signal according to Claim 18 or 19, wherein a counter (81) has a predetermined count cycle of substantially T/2.

21. A data demodulator substantially as described herein and with reference to figures 1 to 12 of the accompanying drawings.