JP2014239363A - Received clock extraction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extract a received clock by expanding the acceptable range of jitter.SOLUTION: A received clock extraction circuit 1 for extracting a received clock from received data with a serial data structure includes exclusive-OR circuits EX_OR1-EX_OR3 for detecting the change point of data by sampling and sequentially shifting the received data with a reference clock, a counter DPLCNT for clearing the count value when the change point is detected, and repeating the count in the range of a predetermined numeric value when the change point is not detected, a detection circuit BITOVR for detecting whether or not the received data is longer than a normal bit width, and a determination circuit AND for transmitting the received clock when the numeric value of the count becomes a predetermined value, but not transmitting the received clock while a state where the received data is longer than a normal bit width is detected by the detection circuit BITOVR.

Description

  The present invention relates to a reception clock extraction circuit applied to a serial data communication system.

  In serial data communication, a reception clock is extracted from reception data. The reception clock extraction method differs depending on the synchronization method. For example, in the case of asynchronous mode, a start bit is inserted in units of 1 byte (8 bits), so the reception clock extraction circuit is initialized by this start bit, and control is performed so that the rising edge of the reception clock is brought to the center of the bit. doing.

  Further, in the case of a bit synchronous type (BOP) used in HDLC transmission or the like, a DPLL circuit method is employed (for example, Patent Documents 1 to 3). The DPLL circuit uses a frequency clock that is 16 times or 32 times the data transmission speed as a reference clock, and measures the shift (phase difference) between the received data and the received clock at each data change point. The phase is corrected by ± 1 to ± 2 bits of the reference clock.

JP-A-9-83354 Japanese Patent Laid-Open No. 9-2224021 JP 2012-244269 A

  In the asynchronous mode, 1 start bit, 1 stop bit (or 2 bits), and 1 parity bit are added for every 8 bits of data, so that transmission efficiency deteriorates when the amount of data is large.

  In the case of the DPLL circuit system, a reference clock that is about 16 to 32 times the data transmission rate is required, so that there is a limit to increasing the transmission rate. In addition, since the amount of correction of the phase of the reception clock at a time is limited, it takes time to complete the correction and the allowable jitter of the reception data is relatively small at about ± 20%.

  Therefore, the present invention detects whether or not the received data is longer than the normal bit width in the reception clock extraction circuit that corrects the reception clock for each bit change, and controls the extraction of the reception clock. The jitter tolerance is expanded.

  In other words, the reception clock extraction circuit of the present invention is a reception clock extraction circuit that extracts a reception clock from reception data having a serial data configuration, and the change point of data obtained by sampling the reception data with a reference clock and sequentially shifting the received data. An exclusive OR circuit to detect, a counter that clears the count value when the change point is detected, but repeats counting within a predetermined numerical range when the change point is not detected, and the received data is a normal one A detection circuit for detecting whether or not the bit width is longer than a bit width; and when the count value becomes a predetermined value, a reception clock is transmitted, while the reception data is a normal bit width in the detection circuit. And a determination circuit that prevents the reception clock from being transmitted while it is detected that the length is longer.

  According to the above invention, even if the ratio of the reference clock frequency to the data transmission rate is small, it is possible to extract the reception clock by expanding the allowable range of jitter with a simple circuit configuration.

1 is a block configuration diagram of a data communication system to which a reception clock extraction circuit according to an embodiment of the present invention is applied. The circuit diagram of a receiving clock extraction circuit. The operation time chart when there is a jitter close to ± 50% in the reception data RXD

  Embodiments of the present invention will be described below with reference to the drawings.

  When the reception clock extraction circuit 1 in the serial data communication system of the present embodiment illustrated in FIG. 1 receives the reception data RXD from the serial communication counterpart device 2, the reception data SRXD sampled with the reference clock BCLK and the reception data The reception clock SRXC extracted based on the detection of the change point of the data RXD is supplied to the communication controller 3. The communication controller 3 takes in the received data SRXD with the reference clock BCLK when SRXC = 1.

[Specific Configuration of Reception Clock Extraction Circuit 1]
The reception clock extraction circuit 1 illustrated in FIG. 2 receives the reception data RXD from the serial communication counterpart device 2, samples it with the reference clock BCLK, and serially shifts it by the data shift circuits DS0, DSi, DSi + 1. Data RXD_S0 to RXD_Si + 1 are generated (where i = 1, 2, 3,...). Serial data RXD_Si + 1 is supplied from the extraction circuit 1 to the communication controller 3 as received data SRXD.

  The reception clock extraction circuit 1 includes an exclusive OR circuit EX_ORi (where i = 1, 2, 3,...), A counter DPLCNT, a detection circuit BITOVR, a count detection circuit CNTOVR, and a determination circuit AND.

  The exclusive OR circuit EX_ORi generates a change detection signal DETECTi of the serial data RXD_Si from the serial data RXD_Si, RXD_Si + 1.

  Explaining a specific example of the exclusive OR circuit EX_ORi, the exclusive logic circuit EX_OR1 generates a change detection signal DETECT1 of the serial data RXD_S1 from the serial data RXD_S1 and RXD_S2. The exclusive logic circuit EX_OR2 generates a change detection signal DETECT2 of the serial data RXD_S2 from the serial data RXD_S2 and RXD_S3. The exclusive logic circuit EX_OR3 generates a change detection signal DETECT3 of the serial data RXD_S3 from the serial data RXD_S3 and RXD_S4.

  The counter DPLCNT is a counter that counts from 1 to the number obtained by dividing the reference clock BCLK by the data transmission speed. The counter DPLCNT clears the count value when the change point of the serial data RXD_Si is detected by the exclusive OR circuit EX_ORi, and repeats counting within a predetermined numerical range when the change point is not detected.

  For example, according to an operation example described later, the counter DPLCNT counts from 1 to 10 with a data transmission rate of 10 Mbps and a reference clock frequency of 100 MHz which is 10 times the data transmission rate. The counter DPLCNT clears the count value n when there is a change in the reception data SRXD (for example, detection of the change detection signal DETECT3) (reset to “1”), while there is no change in the reception data SRXD. Repeat 1 to 10 counts.

  The detection circuit BITOVR detects whether or not the reception data RXD is longer than the normal bit width. The circuit BIOTVR sets the output signal to “1” when the count value n of the counter DPLCNT reaches the maximum value (for example, 10), and remains “1” when the received data SRXD does not change. And reset to “0” when there is a change in received data SRXD (for example, detection of a change detection signal DETECT3).

  The count detection circuit CNTOVR detects whether or not the count value n of the counter DPLCNT exceeds a predetermined value. The detection circuit CNTOVR sets the output signal to “1” when the count value n exceeds a predetermined value.

  The determination circuit AND transmits the reception clock SRXC when the count detection circuit CNTOVR detects that the count value n of the counter DPLCNT has reached a predetermined value, while the detection circuit BITOVR determines that the reception data RXD is normal. The reception clock SRXC is not transmitted while it is detected that it is longer than the bit width of.

  For example, when the count detection circuit CNTOVR detects that the count value n of the counter DPLCNT has passed a predetermined value “3”, the determination circuit AND sets “1” with the reference clock, and the reception clock Send SRXC. On the other hand, while the detection circuit BITOVR is set to “1”, when the numerical value n of the counter DPLCNT has passed “3” and the change detection signal DETECT1 is “0”, the determination circuit AND is the reference clock. Set to “0” so that the reception clock SRXC is not transmitted.

[Description of Operation Example of Reception Clock Extraction Circuit 1]
An operation example of the reception clock extraction circuit 1 will be described with reference to FIGS. Here, an exclusive OR circuit EX_ORi (i = 1, 2, 3) is provided in the circuit 1, the data transmission rate is 10 Mbps, the reference clock is 10 times the data transmission rate, and the received data RXD is ± 50. An example of operation in the case where there is% distortion will be described.

  The serial data RXD_S0 to RXD_S4 obtained by sampling the reception data RXD has a width of 0 for 15 × reference clock and a width of 1 for 5 × reference clock.

  In the present embodiment, when the count detection circuit CNTOVR detects that the count value n of the counter DPLCNT is “n = 3”, the determination circuit AND sets the reception clock SRXC to “1” and externally (communication) Pulse output to controller 3).

  Next, when it is detected by the detection circuit BITOVR that the count value n of the counter DPLCNT is “n = 10”, the count value n of the counter DPLCNT is set to “n = 1” and the count is continued. The

  Thereafter, when the count detection circuit CNTOVR detects that the count value n becomes “n = 3”, the determination circuit AND sets the reception clock SRXC to “1” and outputs a pulse to the outside.

  In this example, when the reception data RXD becomes longer than the normal bit width, the detection circuit BITOVR is set to “1” when the counter value n of the counter DPLCNT exceeds “n = 10”.

  While the output signal of the detection circuit BITOVR is set to “1”, even if the count value n of the counter DPLCNT is detected as “n = 3”, DETECT1 is “1”. The AND does not output the reception clock SRXC.

  Next, when DETECT3 is detected, the counter value n of the counter DPLCNT is cleared, the counter value n is calculated from “n = 1”, and the output signal of the detection circuit BITOVR is reset to “0”.

  Thereafter, when the count detection circuit CNTOVR detects that the count value n has reached “n = 3”, the determination circuit AND is set to “1” at the next rising edge of the reference clock BCLK and received. The clock SRXC is output as a pulse.

  In this embodiment, when the detection circuit BITOVR described above is not applied to the setting condition of the reception clock SRXC, when the bit width becomes long, the count value n of the second counter DPLCNT has passed “n = 3”. The reception clock SRXC is set at the rising edge of the reference clock, and the same reception data is fetched twice. Specifically, when the detection circuit BITOVR is not applied, the allowable jitter is ± 40% when the width of “0” of the received data RXD_S0 to RXD_S4 is limited to 14 × reference clock.

  As is clear from the operation example described above. The reception clock extraction circuit 1 of the present embodiment includes the detection circuit BITOVR, so that even if the ratio of the reference clock frequency to the data transmission speed is small, the allowable range of jitter is larger than the conventional one with a relatively simple circuit configuration. The received clock can be extracted within a range close to ± 50%.

DESCRIPTION OF SYMBOLS 1 ... Serial communication other apparatus 2 ... Receive clock extraction circuit 3 ... Communication controller EX_ORi (i = 1, 2, 3, ...) ... Exclusive OR circuit DPLCNT ... Counter BITOVR ... Detection circuit AND ... Determination circuit

Claims (1)

A reception clock extraction circuit that extracts a reception clock from reception data in a serial data configuration,
An exclusive OR circuit that samples received data with a reference clock and sequentially shifts to detect a data change point;
A counter that repeats counting in a range of a predetermined numerical value while clearing the count value when the change point is detected and not detecting the change point;
A detection circuit for detecting whether or not the received data is longer than a regular bit width;
While the reception clock is transmitted when the count value reaches a predetermined value, the reception clock is received while the detection circuit detects that the reception data is longer than a normal bit width. And a determination circuit for preventing transmission of a received clock.

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