JP2018152643A - Data receiving circuit of start-stop synchronization serial data communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data receiving circuit of a start-stop synchronization serial data communication device capable of determining a baud rate with high reliability by using a particular synchronization pattern code.SOLUTION: A data receiving circuit includes: a change point detection unit 1 for detecting a change point of received serial data; and a measuring timer unit 2 for measuring a time between change points detected by the change point detection unit 1. The data receiving circuit uses a synchronization pattern in which a length of a low section is equal to that of a high section for a synchronization pattern code, sets each of the low and high sections of the synchronization pattern code as a baud rate measuring object, and determines that a baud rate meeting the most in a measurement result of each section is an optimal baud rate.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a data receiving circuit of an asynchronous serial data communication device that receives serial data composed of a start bit, a data bit, and a stop bit, and particularly for determining a reliable transmission rate. .

  In general, asynchronous serial data communication requires the transmission side and the reception side to match the transmission speed (hereinafter referred to as the baud rate) before starting communication, but the baud rate is automatically determined between devices. Has been proposed (see, for example, Patent Document 1). The proposed baud rate identification method automatically recognizes the baud rate of a series of serial data by measuring only the bit width of the start bit of a specific character located at the beginning of the series of serial data using the reception clock. It is.

JP 2001-168853 A

  In the above-described conventional baud rate identification method, the baud rate is determined only by the bit width of the start bit of the specific character located at the beginning of a series of serial data. If the bit width of the start bit is short, the reliability of the specified baud rate may be lowered.

  The present invention has been made to solve the above-described problems in the prior art, and data reception of an asynchronous serial data communication device capable of determining a reliable baud rate by using a specific synchronization pattern code. It aims to provide a circuit.

  The data receiving circuit of the asynchronous serial data communication apparatus according to the present invention is received by the data receiving circuit of the asynchronous serial data communication apparatus that receives serial data composed of start bits, data bits, and stop bits. A change point detection unit that detects a change point of serial data, and a measurement timer unit that measures a time between change points detected by the change point detection unit.

  According to the present invention, using a synchronization pattern in which the length of the Low and High sections are equal, measuring the time width of each of the Low and High sections of the synchronization pattern code, and determining the optimum baud rate from the measurement result, There is an effect of improving the reliability of the determination result.

It is a block diagram which shows the data receiving circuit of the asynchronous serial data communication apparatus in Embodiment 1 of this invention. It is a figure which shows the example of the pattern used as a synchronous pattern in the data receiver circuit shown in FIG. It is a time chart which shows the determination operation | movement of the measurement timer part in the data receiving circuit shown in FIG. 1, and a transmission rate determination part. FIG. 2 is a state transition diagram of a transmission rate determination unit in the data receiving circuit shown in FIG. 1. FIG. 2 is a state transition diagram of a reception control unit in the data reception circuit shown in FIG. 1.

  In the present invention, in the case of a synchronization pattern in which the lengths of the Low and High sections are equal to the synchronization pattern code, for example, in the case of a total of 10 bits including a start bit of 1 bit, a data length of 8 bits, and a stop bit of 1 bit, a pattern having a data portion of 0x1C is used. The time width of each of the low and high sections of the synchronization pattern code is measured, and the optimum baud rate is specified from the measurement result.

  In specifying the baud rate, information on the time width at a predetermined baud rate is held, and the baud rate that matches most compared with the measurement result of each section is determined as the optimum baud rate.

  This baud rate determination circuit can be composed of a simple counter, conditional branch circuit, state machine, and majority circuit, and can be easily implemented by hardware or software.

  However, since it is necessary to hold time width information at a predetermined baud rate in order to implement the present invention, it is necessary to mutually determine corresponding baud rates.

  Hereinafter, specific embodiments of the present invention will be described. FIG. 1 is a block diagram showing a data receiving circuit of an asynchronous serial data communication apparatus according to Embodiment 1 of the present invention. In the data receiving circuit shown in FIG. 1, a synchronization pattern in which the lengths of Low and High sections are equal is used as the synchronization pattern of serial data. For example, as shown in FIG. 2, it is assumed that a pattern in which the data portion is 0x1C is used with a total of 10 bits including a start bit of 1 bit, a data length of 8 bits, and a stop bit of 1 bit.

  The data reception circuit shown in FIG. 1 includes a change point detection unit 1 that detects a change point (falling / rising) of received serial data, and a free-run counter that resets the counter each time a change point is detected. And a measurement timer unit 2 that measures the time width of the measurement interval.

  The counting operation of the measurement timer unit 2 is shown in the time chart of FIG. The changing point of the received serial data (see b in FIG. 3) is detected by the changing point detector 1 and an output signal at the changing point is output (see c in FIG. 3). The measurement timer unit 2 resets the counter each time a change point is detected based on the output signal from the change point detection unit 1 (see d in FIG. 3), and sets the count value (see d in FIG. 3) to 0. . The measurement timer unit 2 stops the counting operation when the state of the reception control unit 7 to be described later is in a state other than “SYNC“ synchronization establishment mode ”.

  In FIG. 3, a is a system clock, e is a status value of a transmission rate determination unit 3 described later, f is a determination result of the transmission rate determination unit 3, g is a synchronization establishment notification signal of the transmission rate determination unit 3, and h is The synchronization failure notification signal of the transmission rate determination unit 3 is shown.

  The data reception circuit shown in FIG. 1 operates when the state of the reception control unit 7 to be described later is in the “SYNC“ synchronization establishment mode ”state, and is the most based on the measurement results of three time widths by the measurement timer unit 2. It further includes a transmission rate determination unit 3 having a function of selecting a baud rate that matches many.

  Details of the operation of the transmission rate determination unit 3 will be described based on the state transition diagram shown in FIG. First, the transmission rate determination unit 3 starts the operation from “IDLE“ standby ”” which is a standby state. When the first change point is detected by the change point detector 1, the transition is made to “SMPL1“ measurement interval [circle 1] measurement ””, and the measurement state of the time width of the first low interval of the synchronous pattern is entered (measurement in FIG. 2). Section [circle 1]). When the next change point is detected by the change point detector 1, the state transits to “SMPL1 JUDGE“ measurement interval [circle 1] baud rate determination ””, and the measurement result of the time width of the first low interval (measurement timer portion in FIG. 1) 2) and the information of the time width prepared in advance are compared to specify the baud rate.

  Next, the state transitions to “SMPL2“ measurement interval [circle 2] measurement ””, the time width of the next high interval is measured (see measurement interval [circle 2] in FIG. 2), and the change point is detected again. Then, the state transits to “SMPL2 JUDGE“ measurement interval [circle 2] baud rate determination ””, and the baud rate in the high interval is specified in the same manner as “SMPL1 JUDGE“ measurement interval [circle 1] baud rate determination ”described above.

  In the subsequent “SMPL3“ measurement interval [circle 3] measurement ”” and “SMPL3 JUDGE“ measurement interval [circle 3] baud rate determination ”” (see measurement interval [circle 3] in FIG. 2), the last is the same as before. The baud rate in the low interval is specified, and finally, the state transitions to “SYNC JUDGE“ Baud rate determination ””.

  In “SYNC JUDGE“ determination of baud rate ””, if there is a baud rate that most closely matches from the three measurement results, the reception control unit 7 is notified of synchronization establishment, and the determined baud rate is set in the baud rate clock generation unit 4. If no matching candidate is listed, the reception control unit 7 is notified of the synchronization failure. When the state of the reception control unit 7 to be described later returns to the “IDLE“ standby ”” state, it returns to “IDLE“ standby ””.

  Further, in the data receiving circuit shown in FIG. 1, the state of the baud rate clock generating unit 4 that generates a baud rate clock by dividing the system clock based on the result of the transmission rate determining unit 3 and the state of the receiving control unit 7 described later are “DATA”. A reception shift register unit 5 that captures received serial data into the reception shift register unit 5 in synchronization with the baud rate clock from the baud rate clock generation unit 4 in the “data reception” state, and converts the serial data into parallel data; When the state of the reception control unit 7 is “SYNC JUDGE“ synchronization determination ”” and the notification of establishment of synchronization is received from the transmission rate determination unit 3, the response character is synchronized with the baud rate clock of the baud rate clock generation unit 4. Is provided with a transmission shift register unit 6 for transmitting the data to the transmission side and a reception control unit 7 for controlling the entire data reception circuit. That.

  Details of the operation of the reception control unit 7 will be described based on the state transition diagram of FIG. First, the reception control unit 7 starts the operation from “IDLE“ standby ”” which is a standby state. When the first change point is detected, transition is made to “SYNC“ synchronization establishment mode ””. At this time, the measurement timer unit 2 and the transmission rate determination unit 3 are enabled, and the operation for specifying the baud rate from the above-described synchronization pattern is performed.

  Next, when the change point is detected three times, the state transits to the “SYNC JUDGE“ synchronization determination ”” state, and the following operation is executed according to the result notified from the transmission rate determination unit 3. When the baud rate is fixed and a notification of synchronization establishment is received, a pattern indicating that synchronization is established is transmitted from the transmission shift register unit 6 to the transmission side. On the other hand, when a notification of synchronization establishment failure is received, nothing is done and the process returns to “IDLE“ wait ”” and waits for a retry from the transmission side. When synchronization is established, transition to the data reception mode “DATA“ data reception mode ”” to perform normal communication. When a character indicating the end of communication is received, transition to “FLAME END“ frame reception end ”” After ending, the process returns to “IDLE“ standby ”” and waits for the next data transmission.

  As described above, according to the present invention, using the synchronization pattern in which the lengths of the Low and High sections are equal, the time widths of the Low and High sections of the synchronization pattern code are measured, and the optimum baud rate is determined from the measurement result. Since it is determined, there is an effect of improving the reliability of the determination result.

DESCRIPTION OF SYMBOLS 1 Change point detection part 2 Measurement timer part 3 Transmission speed judgment part 4 Baud rate clock generation part 5 Reception shift register part 6 Transmission shift register part 7 Reception control part a System clock b Reception serial data input signal c Output of change point detection part 1 Signal d Count value of measurement timer unit 2 e Status value of transmission rate determination unit 3 f Determination result of transmission rate determination unit 3 g Synchronization establishment notification signal of transmission rate determination unit 3 h Synchronization failure notification signal of transmission rate determination unit 3

Claims (5)

In a data receiving circuit of an asynchronous serial data communication device that receives serial data composed of a start bit, a data bit, and a stop bit,
A change point detector for detecting a change point of received serial data;
A data reception circuit of an asynchronous serial data communication device, comprising: a measurement timer unit that measures a time between change points detected by the change point detection unit. In the data receiving circuit of the asynchronous serial data communication device according to claim 1,
A data receiving circuit of an asynchronous serial data communication device, wherein a pattern in which the lengths of Low and High sections are equal is used for the synchronous pattern code of the serial data. In the data receiving circuit of the asynchronous serial data communication device according to claim 1 or 2,
A data reception circuit of an asynchronous serial data communication device, further comprising a transmission rate determination unit that specifies a baud rate based on a measurement result of a time between change points from the measurement timer unit. In the data receiving circuit of the asynchronous serial data communication device according to claim 3,
The transmission rate determination unit measures the time width of each section of the synchronization pattern code between Low and High, and specifies an optimum baud rate from a plurality of time width measurement results. A data receiving circuit of a data communication device. In the data receiving circuit of the asynchronous serial data communication device according to claim 4,
A transmission rate determination circuit for an asynchronous serial data communication device, further comprising a baud rate clock generation unit that generates an appropriate baud rate clock according to the baud rate specified by the transmission rate determination unit.

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