JP5704506B2 - Communication device and field device system - Google Patents

Description

  The present invention relates to a communication apparatus that performs binary signal communication using two different frequencies, and a field device system to which the communication system is applied.

  HART (Highway Addressable Remote Transducer) communication can be used as one of methods for communicating signals between two different devices. In HART communication, signal logic is expressed by different frequencies. As a general standard, when logic “0” is indicated, the frequency is 2200 Hz, and when logic “1” is indicated, the frequency is 1200 Hz. Therefore, the transmission side apparatus modulates the signal to 2200 Hz when the logic is “0”, and transmits the signal after being modulated to 1200 Hz when the logic is “1”.

  The receiving device receives the signal transmitted from the transmitting device and demodulates the signal based on the frequency of this signal. That is, the signal is demodulated as logic "0" when the frequency of the signal is 2200 Hz, and as logic "1" when the signal frequency is 1200 Hz. Thereby, HART communication is performed. As this type of technology, there is a technology disclosed in Patent Document 1.

  FIG. 7 shows an example of the demodulator 100 that constitutes the receiving apparatus. The demodulator 100 receives a signal transmitted from the receiving apparatus as an input signal rxd. The input signal rxd is demodulated to determine the logic and output as the output signal sig. As shown in the figure, the demodulator 100 includes a rise edge detection circuit 101 (R edge detection circuit in the figure), a fall edge detection circuit 102 (F edge detection circuit in the figure), a first OR circuit 103, and a timer. A circuit 104, a second OR circuit 105, a flip-flop 106, a first comparator 107, a second comparator 108, and a third OR circuit 109 are provided.

  The rise edge detection circuit 101 detects the rising edge (rise edge) of the input signal rxd, and the fall edge detection circuit 102 detects the falling edge (fall edge) of the input signal rxd. The first OR circuit 103 performs an OR operation between the rise edge signal rxdr output from the rise edge detection circuit 101 and the fall edge signal rxdf output from the fall edge detection circuit 102.

  The timer circuit 104 is a 9-bit counter (data in the figure) and starts from “0” and counts up to “511”. When counting up to “511”, all the 9-bit values are “1”. The timer circuit 104 operates at a predetermined clock frequency (here, 1.2288 MHz), and increments the count value during this one clock. Then, after the count value of the timer circuit 104 reaches “511”, “511” is fixed and output (does not wrap around).

  The timer circuit 104 receives the output (trig in the figure) of the first OR circuit 103 and starts counting using this as a trigger. That is, counting starts at the edge timing when the input signal rxd changes. At this time, the count value is reset (the value is set to “0”), and then the count is started.

  The timer circuit 104 outputs the counted value as the count value prdpre. When the count value reaches “511”, the timer circuit 104 outputs a pulse indicating that as a carry-out signal carry. The second OR circuit 105 performs an OR operation between the output trig of the first OR circuit 103 and the carryout signal carry and outputs the result to the flip-flop 106 as an enable signal.

  The flip-flop 106 receives the count value prdpre from the timer circuit 104 and holds the value. At this time, the value is held when the enable signal is input from the second OR circuit 105. The held value is output to the first comparator 107 as the count value prd at the next timing.

  The first comparator 107 compares the count value prd output from the flip-flop 106 and outputs the first output signal prdh. If the count value prd is “361” or more, the first output signal prdh is output as High, and if it is less than “361”, it is output as Low. Similarly, the second comparator 108 compares the count value prdpre output from the timer circuit 104 and outputs a second output signal prdpreh. The second output signal prdpreh becomes high when the count value is “361” or more, and becomes low when the count value is less than “361”.

  The first output signal prdh is a signal that passes through the flip-flop 106, and the second output signal prdpreh is a signal that does not pass through the flip-flop 106. Therefore, the count value prdpre is originally the same. For this reason, the first output signal prdh and the second output signal prdpreh are the same signal and are out of timing.

  The third OR circuit 109 performs an OR operation between the first output signal prdh and the second output signal prdpreh. The output signal sig is output to the subsequent signal processing circuit. The output signal sig is a signal obtained by demodulating the signal transmitted from the transmission side device. As described above, communication by HART communication is performed and the logic is restored.

  Next, the operation will be described with reference to the timing chart of FIG. The rise edge detection circuit 101 and the fall edge detection circuit 102 detect the edge of the input signal rxd. The timer circuit 104 starts the count value from zero at the timing when the edge is detected, and counts up until the next edge is detected. When the edge is detected, the count value is returned to zero.

  The input signal rxd has a frequency of 1200 Hz or 2200 Hz in order to express different logic. The count value differs depending on whether the input signal rxd is 1200 Hz or 2200 Hz. That is, the timer circuit 104 measures a time interval between edges, and the count value varies depending on the frequency of the input signal rxd. This expresses logic.

  A value “361” serving as a reference for comparison between the first comparator 107 and the second comparator 108 is a reference for determining the frequency of the input signal rxd. An intermediate value between the frequencies of 1200 Hz and 2200 Hz is 1700 Hz. If this is based on 1.2288 MHz which is the clock frequency of the demodulator 100, the count value is “722”. That is, the count value is “722 = 1.2288 MHz / 1700 Hz”.

  The input signal rxd has one rise and one fall during one period. Therefore, the interval between the edge (rise edge or fall edge) and the edge (fall edge or rise edge) is half of one period. For this reason, the threshold value is set to “361” which is half of “722”. The first comparator 107 and the second comparator 108 determine whether or not “361” or more.

  When it is less than “361”, it is recognized that the frequency of the input signal rxd is high. Therefore, the logic is determined as “0” (that is, the frequency of the input signal rxd is 2200 Hz). On the other hand, when the frequency is “361” or more, it is recognized that the frequency of the input signal rxd is low. Therefore, the logic is determined as “1” (that is, the frequency of the input signal rxd is 1200 Hz).

  Accordingly, the logic is determined by the timer circuit 104 measuring the time between the edges of the input signal rxd using “361” as a threshold value. Thereby, the logic of the input signal rxd can be determined and demodulated, and the output signal sig can be output.

JP 2002-111752 A

  Therefore, the logical determination is performed based on the interval (time: pulse width) between the edges. This point is the same for the technique shown in FIG. 7 and the technique of Patent Document 1 described above. The interval between the edges differs depending on whether the logic of the input signal rxd is “0” or “1”.

  That is, in the HART communication, the logic is expressed by changing the frequency of the input signal rxd between 1200 Hz and 2200 Hz. For this reason, the timing at which the edge appears changes in the time axis direction depending on whether the logic is “0” (= 2200 Hz) or the logic is “1” (= 1200 Hz). Therefore, the timing at which the logic of the signal changes is indefinite.

  On the other hand, the demodulator 100 generates the output signal sig at a constant frequency (the frequency of the rate period CT), and in the circuit that processes the output signal sig connected to the demodulator 100, the output signal sig at the frequency of the rate period CT. And a predetermined process is performed. The rate cycle CT at this time is a fixed cycle in which the demodulator 100 and the subsequent circuit operate, and is independent of the logic of the input signal rxd.

  That is, the frequency of the rate period CT and the frequency of the input signal rxd are not synchronized. For this reason, when the timing of the rate period CT and the timing at which the logic of the input signal rxd changes are close, an edge that is originally detected is not detected during the rate period CT, or an edge that is not detected otherwise May be detected. For this reason, the count value of the timer circuit 104 becomes different from the original value of the input signal rxd, and the interval between the edges cannot be accurately detected. As a result, the logic indicated by the input signal rxd cannot be accurately demodulated, and correct communication cannot be performed.

  In addition, since the logic cannot be accurately demodulated, the start of communication cannot be detected. The start of communication is detected when transmission of a signal from the transmission side device to the reception side device is started. This communication start is detected when the logic of the input signal rxd is detected as “0”. , Detecting the start of communication. At this time, as described above, if the logic cannot be accurately demodulated because the frequency of the rate period CT and the frequency of the input signal rxd are not synchronized, the start of communication cannot be detected accurately.

  Therefore, an object of the present invention is to perform accurate communication when communicating by expressing signal values using different frequencies.

In order to solve the above problems, a communication device of the present invention is a communication device that communicates binary signals using different frequencies, and includes a first timer that defines a constant rate period, and the rate period. A second timer that is provided within each of the rate periods as a synchronized period and that defines a period shorter than the rate period, and counts the number of edges of the signal within the period that is defined by the second timer And a logic determination circuit that determines the logic of the signal based on the number of edges counted by the edge counter, and the logic determination circuit includes the rate period defined by the first timer. According to this communication apparatus, the logic of the signal is determined every time, and the frequency of the rate period coincides with a lower frequency among the frequencies. For example, since the logic is determined based on the number of edges detected at regular intervals rather than the edge interval, accurate communication can be performed.

The first timer and the second timer, characterized in that constructed by sharing one of the timer circuit for counting a clock signal having a constant period.

The second timer defines a period shorter than one period of the first frequency and longer than 1.5 periods of the second frequency higher than the first frequency as the period, The logic determination circuit performs logic determination based on whether or not the number of edges is three or more. As a result, the number of edges can always be made different between the first frequency and the second frequency, so that the logic can be determined reliably and accurate communication can be realized.

  The logic determination circuit determines that the logic is “0” when the number of edges is 3 or more when the first frequency is 1200 Hz and the second frequency is 2200 Hz, and less than 3. In this case, it is determined that the logic is “1”. As a result, when performing HART communication using frequencies of 1200 Hz and 2200 Hz, communication can be accurately performed.

  The logic determination circuit determines that the signal is not communicated when the number of edges is “0”, and communication of the signal starts when the number of edges changes from “0” to “3”. It is characterized by determining that it was done. Thereby, the start of communication can be detected.

The logic determination circuit outputs the logic of the signal at each rate period defined by the first timer .

  A field device system according to the present invention includes any one of the communication devices. The communication device can be applied to communication between the host controller of the field device system and the field device.

  The present invention determines the logic based on the number of edges per fixed determination period, not the signal edge interval, when performing communication expressing the logic with two different frequencies. As a result, the correct logic can always be demodulated regardless of the signal logic, and accurate communication can be performed.

It is a block diagram which shows the structure of a communication apparatus. It is a block diagram which shows the structure of a demodulation part. It is a flowchart which shows operation | movement of the demodulation part of embodiment. FIG. 4 is a continuation flowchart of FIG. 3. It is a timing chart which shows the timing of operation of an embodiment. It is a timing chart at the time of losing a pulse. It is a block which shows the structure of the conventional demodulation part. It is a timing chart which shows the timing of operation | movement of the conventional demodulation part.

  Embodiments of the present invention will be described below with reference to the drawings. The communication apparatus of this embodiment can be applied to, for example, a field device system. The field device system connects various field devices such as sensors, actuators, controllers and the like such as a differential pressure meter, a flow meter, and a thermometer, and a host control device. At this time, the following communication device can be applied when performing communication between the field device and the host control device. Of course, the present invention may be applied to any system other than the field device system.

  In this embodiment, communication is performed by HART (Highway Addressable Remote Transducer) communication. In HART communication, logic is expressed by setting the frequency of a signal to 1200 Hz or 2200 Hz. Hereinafter, when the frequency is 1200 Hz, a logic “1” is indicated, and when the frequency is 2200 Hz, a logic “0” is indicated. Of course, the logic corresponding to the frequency may be reversed, and the frequency indicating the logic may be arbitrarily set. In addition, if it is a communication apparatus of this embodiment, it will not be limited to the name of HART communication.

  FIG. 1 shows a communication device 1. The communication apparatus 1 includes a UART transmission unit 2, a modulation unit 3, an analog waveform transmission circuit 4, an analog waveform reception circuit 5, a demodulation unit 6, and a UART reception unit 7. The UART transmission unit 2 generates a signal to be transmitted (a signal whose logic is “0” or “1”) and outputs the signal to the modulation unit 3. In the embodiment of FIG. 1, the UART transmission unit 2, the modulation unit 3, the analog waveform transmission circuit 4, the analog waveform reception circuit 5 and the demodulation unit 6 perform HART communication.

  The modulation unit 3 modulates the frequency of the signal to be transmitted to the first frequency FL and the second frequency FH (FH> FL) according to the logic of the input signal. Here, when the logic is “1”, it is modulated to the first frequency FL (= 1200 Hz), and when it is “0”, it is modulated to the second frequency FH (= 2200 Hz).

  The analog waveform transmission circuit 4 converts the signal after modulation by the modulation unit 3 from a digital signal to an analog signal. Then, this analog signal is transmitted. The UART transmitter 2 to the analog waveform transmitter circuit 4 constitute a transmitter circuit. The transmission circuit can be provided in a field device, for example.

  The analog waveform receiving circuit 5 receives the analog signal transmitted by the analog waveform transmitting circuit 4. The received analog signal is converted into a digital signal. This digital signal is input to the demodulator 6 as an input signal rxd, and the demodulator 6 performs demodulation to restore the logic from the input signal rxd. Then, the demodulated signal is output to the UART receiver 7 as an output signal sig.

  The UART receiver 7 acquires an output signal sig input at a constant cycle (rate cycle CT) and performs predetermined signal processing. The analog waveform receiving circuit 5 to the UART receiving unit 7 constitute a receiving side circuit. For example, a reception-side circuit can be provided in the host controller in the field device system.

  Next, the demodulator 6 will be described with reference to FIG. The demodulator 6 is a signal generator that generates the output signal sig. The demodulator 6 includes a rise edge detection circuit 11, a fall edge detection circuit 12, a logical sum circuit 13, a state determination circuit 14, a timer circuit 15, an edge number counter 16, a logical determination circuit 17, and a start bit detection circuit 18. It is composed.

  The demodulator 6 operates based on a predetermined clock frequency CLK. Here, the frequency of the clock frequency CLK is 1.2288 MHz. Of course, the value of the clock frequency CLK is not limited to this, and can be an arbitrary frequency.

  The rise edge detection circuit (R edge detection circuit in the figure) 11 operates at the clock frequency CLK and detects the rising edge (rise edge) of the input signal rxd. The fall edge detection circuit (F edge detection circuit in the figure) 12 operates at the clock frequency CLK and detects the falling edge (fall edge) of the input signal rxd.

  The OR circuit 13 performs a logical OR operation of the rise edge signal rxdr indicating that the rise edge detection circuit 11 has detected the rise edge and the fall edge signal rxdf indicating that the fall edge detection circuit 12 has detected the fall edge. ing. That is, the OR circuit 13 detects the edges (rise edge and fall edge) of the input signal rxd. A signal output from the OR circuit 13 is defined as an edge signal rxdrf.

  The state determination circuit 14 determines whether the reception state has received the input signal rxd or the idle state in which the input signal rxd has not been received. For this purpose, a rise edge signal rxdr is input. When the rise edge signal rxdr is input, it is determined that the idle state is switched to the reception state. Then, a state signal stat indicating the reception state is output.

  The timer circuit 15 is a counter that operates at the clock frequency CLK. This timer circuit 15 is a 10-bit counter (data in the figure), and counts up from “0” to “1023” (increments the count value). The timer circuit 15 operates when a state signal stat is input, that is, when it is in a receiving state.

  The count value counted by the timer circuit 15 starts from “0”, and the carry-out signal carry is output at the timing when it reaches “1023”. The timer circuit 15 resets the count value (returns the count value to “0”) at the timing when the carry-out signal carry is output, that is, when the count value reaches “1023”.

  The carry-out signal carry defines the timing of the rate period CT. This rate period CT is the timing at which the output signal sig is output, that is, the timing at which the UART receiver 7 acquires the output signal sig. The timer circuit 15 outputs a control signal ctr. This control signal ctr becomes a signal indicating that when the count value of the timer circuit 15 reaches a predetermined threshold th (here, 837).

  The edge number counter 16 measures the number of times the edge signal rxdrf output from the OR circuit 13 is input, and detects the measured number as the number of edges. The edge number counter 16 has an initial value “0”, and increments the value every time the edge signal rxdrf is input. The edge number counter 16 receives the carry-out signal carry, and resets the value at each timing when the carry-out signal carry is inputted, that is, at the timing of the rate period CT (returns the count value to “0”).

  The edge number counter 16 outputs the measured edge number (count value) as an edge signal edg. The edge number counter 16 is input with a status signal stat, and the edge number counter 16 operates in the reception state.

  The logic determination circuit 17 determines the logic of the input signal rxd. The logic is determined based on the edge signal edg output from the edge number counter 16. The logic determination circuit 17 receives the control signal ctr and determines the logic based on the edge signal edg at the timing of the control signal ctr, that is, the timing at which the threshold th is reached.

  At this time, when the edge signal edg is “3”, it is determined that the logic is “0”, and when it is less than “3”, it is determined that the logic is “1”. The determined logic is output to the UART receiver 7 as an output signal sig for each rate period CT. For this reason, the carry-out signal carry is input from the timer circuit 15 and the output signal sig is output at the timing of this signal (the timing of the rate period CT). Thus, demodulation for restoring the signal is performed.

  The start bit detection circuit 18 detects the start of communication. Here, the start of communication is detected when the logic of the input signal rxd initially indicates “0”. The start of communication may be detected when the logic is “1”. For this purpose, the edge signal edg is input from the edge number counter 16. The edge signal edg is input at the timing when the control signal ctr is input, that is, when the count value counted by the timer circuit 15 reaches the threshold th. When the edge signal edg input at this time is “3”, it recognizes that the logic is “0” and detects the start of communication.

  The operation in the above configuration will be described with reference to the flowcharts of FIGS. 3 and 4 and the timing chart of FIG. First, the state determination circuit 14 detects a communication state based on the rise edge signal rxdr (step S11). Then, it is determined whether or not a rise edge has been detected (step S12).

  If the rising edge is not detected, the idle state is entered. Therefore, the operation of returning to step S11 is repeated. On the other hand, when the rising edge is detected, the state determination circuit 14 outputs a state signal stat indicating that the reception state has been established. By inputting the status signal stat, the timer circuit 15 resets its count value and returns the value to “0” (step S13). Further, the value of the edge number counter 16 is also reset to set the value to “0” (step S14).

  Then, the timer circuit 15 starts counting up (step S15). The timer circuit 15 operates at a timing synchronized with the clock frequency CLK, and counts from “0” to “1023”. The maximum count value “1023” at this time is a value (= 1024 = 1.2288 MHz / 1200 Hz) obtained by dividing the clock frequency CLK (= 1.2288 MHz) by the frequency (= 1200 Hz) of the rate period CT.

  Here, the first frequency FL (= 1200 Hz), which is the lower frequency of the first frequency FL and the second frequency FH, is matched with the frequency of the rate period CT. Thus, the output signal sig is generated and output at the timing of the first frequency FL. The frequency of the rate period CT may be set to a frequency other than the first frequency FL.

  Therefore, the timer circuit 15 counts up every clock of the clock frequency CLK. A threshold value th is set in the timer circuit 15, and it is determined whether or not the count value has reached the threshold value th (step S16). If not, the process returns to step S15 to continue counting up.

  The threshold value th is the timing at which the edge number counter 16 counts the number of edges. Here, the threshold value th is “837”. The timer circuit 15 measures the period from when the count value becomes “0” to “837” as the determination cycle JT. This determination cycle JT defines the cycle (that is, the timing for determining logic) in which the edge number counter 16 counts the number of edges. Here, the determination period JT is set to 1.5 periods of the second frequency FH (= 2200 Hz).

  The frequency of the rate cycle CT is 1200 Hz, and the timer circuit 15 counts “1024” to detect one cycle of the rate cycle CT. Therefore, the threshold th that defines the determination cycle JT corresponding to 1.5 cycles of the second frequency FH (= 2200 Hz) is “th = (1200/2200) × 1024 × 1.5 = 837”. Note that the determination period JT can be set to an arbitrary value by satisfying the predetermined condition, even if the determination period JT is not 1.5 periods of the second frequency FH. This point will be described later. When the count value of the timer circuit 15 reaches the threshold value th, the fact is output as a control signal ctr.

  The edge number counter 16 detects the number of edges counted until the control signal ctr is input (step S17). The edge number counter 16 is “0” as an initial value, and each time the edge signal rxdrf output from the OR circuit 13 is input, the number of times is measured. Then, the count value at the timing when the control signal ctr is input is output as the edge signal edg. When the control signal ctr is input, the edge number counter 16 returns its count value to “0”.

  The edge signal edg at this time indicates the logic of the input signal rxd. As also shown in the timing chart of FIG. 5, the number of edges detected during the determination period JT varies depending on whether the input signal rxd is the first frequency FL or the second frequency FH. That is, at the second frequency FH (= 2200 Hz), the number of edges detected during the determination period JT is “3”, and at the first frequency FL (= 1200 Hz), it is detected during the determination period JT. The number of edges to be performed is “2” (that is, less than “3”). This is because the number of edges in the time of the predetermined determination cycle JT increases at a high frequency and decreases at a low frequency.

  Here, in order to clearly distinguish the first frequency FL and the second frequency FH, the threshold th is set to 1.5 periods of the second frequency FH. If the input signal rxd is the second frequency FH, the number of edges during the 1.5 period of the second frequency FH is three (rise, fall, rise or fall, rise, fall).

  On the other hand, 1.5 periods of the second frequency FH are smaller than one period of the first frequency FL (count value is “1024”). Therefore, if the input signal rxd is the first frequency FL, the number of edges becomes two (rise, fall or fall, rise) during 1.5 periods of the second frequency FH. Thereby, by setting the threshold th so that the determination period JT is 1.5 periods of the second frequency FH, the number of edges is always different between the first frequency FL and the second frequency FH. Become. That is, the logic can be reliably determined.

  The start bit detection circuit 18 determines whether or not the start of communication is detected (step S18). For this purpose, the start bit detection circuit 18 inputs the edge signal edg from the edge number counter 16. When the edge signal edg is “3”, it indicates that the frequency is the second frequency FH, that is, it is recognized that the logic is “0”.

  Therefore, the start bit detection circuit 18 detects the start of communication when the edge signal edg is “3”. On the other hand, when the edge signal edg is less than “3”, the start of communication is not detected. In this case, the process returns to the process of resetting the timer circuit 15 in step S13, and the flow starts from this process.

  When the state determination circuit 14 determines that the state is the idle state, the edge of the input signal rxd has not changed. That is, the edge signal edg to be detected is “0” in a state where communication is not performed. Therefore, the start bit detection circuit 18 detects the start of communication when the edge signal edg changes from “0” to “3”.

  When the start of communication is detected in step S18, the timer circuit 15 continues counting as it is (timer free run: step S19). Thereby, even after the count value of the timer circuit 15 reaches “837”, the count-up is continued from “838”. Then, the timer circuit 15 determines whether or not the count value has reached “1023”, that is, whether or not the rate cycle CT has ended (step S20). Until the count value reaches “1023”, the timer circuit 15 counts up.

  When the count value of the timer circuit 15 reaches “1023”, the carrier-out signal carry is output on the assumption that the one-rate period CT has ended. As shown in FIG. 4, the timer circuit 15 resets the count value at the timing when the carry-out signal carry is output (step S21). The edge number counter 16 resets the count value (step S22).

  The timer circuit 15 counts up (step S23). The timer circuit 15 determines whether or not the count value has reached the threshold th (= 837) (step S24). If it is determined that the count value has not reached, the process returns to step S23 to continue counting up.

  On the other hand, when it is determined that the threshold value th has been reached, the timer circuit 15 outputs a control signal ctr. Based on the control signal ctr, the edge number counter 16 outputs the measured edge number as the edge signal edg (step S25). This edge signal edg is input to the logic determination circuit 17.

  The logic determination circuit 17 determines the input edge signal edg (step S26). When the edge signal edg indicates “3”, it is recognized that the input signal rxd is the second frequency FH as described above. Thereby, it is determined that the logic is “0” (step S27). On the other hand, when the edge signal edg is “2” (less than “3”), it is recognized that the input signal rxd has the first frequency FL as described above. Thereby, it is determined that the logic is “1” (step S28).

  The timing at which the threshold value th is reached, that is, the timing at which the logic determination circuit 17 determines the logic by inputting the control signal ctr, has not yet ended the rate period CT. Therefore, the timer circuit 15 counts up from “838” which is a continuation of the threshold th (= 837) (timer free run: step S29).

  Then, it is determined whether or not the count value of the timer circuit 15 has reached “1023”, that is, whether or not the 1-rate period CT has ended (step S30). If the count value has not reached “1024”, the timer free run in step S29 is continued. On the other hand, when the rate cycle CT ends, the logic determination circuit 17 outputs the determined logic to the UART reception unit 7 as an output signal sig.

  The UART receiver 7 receives the output signal sig at every timing of the rate period CT and performs predetermined signal processing. At this time, the timing at which the UART receiver 7 acquires the output signal sig is always a constant cycle (rate cycle CT). For this purpose, the logic determination circuit 17 outputs the output signal sig at every timing when the carry-out signal carry is input. Then, it is determined whether or not all communication has been completed (step S31). If it is determined that the communication has not ended, the process returns to step S21 again, and if it is determined that the communication has ended, the process ends.

  Therefore, the timer circuit 15 detects the number of edges of the input signal rxd every fixed determination period JT, and determines the logic based on the number of edges. That is, the logic is determined based on the number of edges of the input signal rxd within a certain time interval.

  The logic of the input signal rxd is expressed by making the frequency different between the first frequency FL and the second frequency FH. When measuring the interval between edges (time: pulse width) to determine logic, an edge that should not be detected during the rate period CT or an edge that should not be detected should be detected May be detected. This impairs the accuracy of the communicated signal.

  In this regard, in this embodiment, the logic is determined by detecting the number of edges during a certain time (determination period JT), not the interval between edges. For this reason, the timing is not affected by whether the logic of the input signal rxd is “0” or “1”, and the correct logic can always be determined during a certain rate period CT. As a result, accurate communication can be performed.

  Further, in order to realize the operation of the present embodiment, it is necessary to detect two times of the determination cycle JT and the rate cycle CT. In this regard, as shown in FIG. 2, one timer circuit 15 counts both the determination cycle JT and the rate cycle CT. That is, since the counter for detecting the judgment cycle JT and the counter for detecting the rate cycle CT are not provided separately and are realized by one timer circuit, the circuit can be simplified.

  In the above, when starting communication, it is desirable to transmit preamble data. In the preamble data, the logic of the first bit is “0”, and the subsequent bits are data in which the data of “1” is repeated a plurality of times (that is, data such as 0111101111). This preamble data is data indicating the start of communication.

  FIG. 6 shows the timing chart of FIG. 5 in which the first pulse is lost (no edge appears). At the start of communication, the first pulse may be lost due to noise or the like. For this reason, it should be detected that the number of edges is originally “3” in the first determination period JT as shown in FIG. 6, but the number of edges is detected as “2” due to the loss of the pulse. become.

  In this case, logic “0” should be detected, but logic “1” is detected. Therefore, the start of communication cannot be detected. At this time, preamble data is transmitted. As a result, even if the first pulse is lost, when the logic next becomes “0”, the number of edges becomes “3”, and the start of communication can be detected as a star and a bit. In any case, when the number of edges detected by the edge number counter 16 first changes from “0” to “3”, the start of communication is detected.

  The determination cycle JT is 1.5 cycles of the second frequency FH, and the corresponding threshold value of the timer circuit 15 is “837”, but the determination cycle JT is 1.5 cycles of the second frequency FH. It may be set as a value other than the period. The determination cycle JT may be an arbitrary value as long as it is 1.5 cycles or more of the second frequency FH (= 2200 Hz) and 1 cycle or less of the first frequency FL (= 1200 Hz). . For example, the threshold th may be set to “900” instead of “837”.

  This is because, during the determination period JT, when the input signal rxd is the second frequency FH (that is, the logic is “0”), the number of edges is “3” and the input signal rxd is the first frequency. This is because the number of edges is set to “2” (less than “3”) when FL (that is, logic is “1”). For this reason, if the number of edges detected during the determination period JT is always different between the second frequency FH and the first frequency FL, the determination period JT (that is, the threshold th) can be arbitrarily set. it can. Alternatively, the number of edges may be “4” when the logic is “0”, and may be less than “4” when the logic is “1”.

  Further, although the frequency of the rate period CT is matched with the first frequency FL, it may not be matched with the first frequency FL. However, when the UART receiver 7 acquires the output signal sig at the timing synchronized with the first frequency FL, the rate period CT is made to coincide with the first frequency FL.

DESCRIPTION OF SYMBOLS 1 Communication apparatus 6 Demodulation part 7 UART receiving part 11 Rise edge detection circuit 12 Fall edge detection circuit 13 OR circuit 14 State determination circuit 15 Timer circuit 16 Edge number counter 17 Logic determination circuit 18 Start bit detection circuit

Claims (7)

A communication device that communicates binary signals using different frequencies,
A first timer defining a constant rate period;
A second timer defining a period shorter than the rate period provided in each of the rate periods as a period synchronized with the rate period;
An edge counter that counts the number of edges of the signal within the period defined by the second timer;
A logic determination circuit that determines the logic of the signal based on the number of edges counted by the edge counter;
With
The logic determination circuit determines the logic of the signal for each rate period defined by the first timer ;
The frequency of the said rate period corresponds with the low frequency among the said frequencies .   2. The communication apparatus according to claim 1, wherein the first timer and the second timer are configured to share a timer circuit that counts a clock signal having a constant period. The second timer defines a period shorter than one period of the first frequency and longer than 1.5 periods of the second frequency higher than the first frequency as the period.
The communication apparatus according to claim 2, wherein the logic determination circuit determines a logic based on whether or not the number of edges is three or more.   When the first frequency is 1200 Hz and the second frequency is 2200 Hz, the logic determination circuit determines that the number of edges is 3 or more and is logic “0”, and the number is less than 3 4. The communication device according to claim 3, wherein the communication device is determined to be logic “1”.   The logic determination circuit determines that the signal is not communicated when the number of edges is “0”, and communication of the signal is started when the number of edges changes from “0” to “3”. The communication apparatus according to claim 4, wherein the determination is made.   5. The communication apparatus according to claim 1, wherein the logic determination circuit outputs the logic of the signal for each rate period defined by the first timer. 6.   A field device system comprising the communication device according to claim 1.

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