JP2007251930A - Wireless demodulation circuit and remote controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To determine a more accurate data sampling point by highly accurately discriminating a threshold value. <P>SOLUTION: In a wireless demodulation circuit of the present invention, a multi-level FSK signal is demodulated by a digital demodulator, a data discriminator makes a threshold value discrimination on a demodulated output of the digital demodulator, and a threshold value of the data discriminator is held by a threshold value holder. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a radio demodulation circuit that optimizes a threshold value and corrects a data synchronization point in data determination in data communication by multi-level FSK radio communication using an FSK signal that is one of frequency modulation signals.

  Conventionally, data communication for wirelessly transmitting various data by FSK wireless communication using an FSK (Frequency Shift Keying) signal, which is one of FM (frequency modulation) signals, has been widely used as one method of data communication.

  In the case of data transmission in data communication by this FSK wireless communication, first, the digital signal is frequency-modulated by the frequency shift of the carrier wave corresponding to “1”, “0” of the digital signal, A high-frequency signal obtained thereby is transmitted as a radio wave. Then, the transmitted high frequency signal is received by the FSK receiver, and the transmitted data is demodulated. During demodulation, the frequency component of the demodulated baseband signal voltage-converted by the frequency-voltage conversion circuit is compared by a comparator to determine a digital value, and transmission source data is obtained based on the determined digital value.

  In order to realize high-speed transmission in narrow-band FSK wireless communication, multilevel processing is used from the viewpoint of effective frequency utilization. In the case of multilevel conversion, for example, in the case of four values, the carrier wave is frequency-shifted in correspondence with digital signals “00”, “01”, “11”, “10”. In this case, three types of comparators are prepared, and “00” and “01”, “01” and “11”, and “11” and “10” are determined to obtain data of the transmission source.

  In the four-value FSK wireless communication as described above, when communication is realized in the same band, the threshold value determination becomes more severe. In addition, more accurate data sampling points need to be determined, and more accurate synchronization is required on the transmission side and the reception side to achieve high-speed transmission.

On the other hand, in a conventional FSK receiving apparatus (for example, Patent Document 1), FSK demodulation is performed by analog processing, and threshold determination is also performed by an analog comparator. In a conventional FSK receiver, FSK demodulation is performed by analog processing, an optimal threshold value is calculated from a bit synchronization signal, a bit error rate, and the like, and the calculation result is fed back to a reference voltage of a threshold determination comparator. Thus, the optimum threshold value is calculated. However, if the threshold value has a width due to variations in the reference voltage of the comparator, the width between the threshold values becomes narrow. Therefore, there is a limit to the determination at the time of multilevel modulation at the time of reception. In addition, the synchronization point can be determined by using a unique clock based on the transmission speed information, so that there is a limit to the acquisition of synchronization on the transmission side and reception side, which greatly affects reception characteristics for realizing high-speed transmission.
JP-A-9-8854

  As described above, in the conventional FSK receiver, the threshold value corrector is composed of an analog comparator. As a result, noise is superimposed on the reference voltage of the threshold value corrector (analog comparator), and as a result, the determination result is greatly deteriorated. Further, when the threshold calculator analog circuit is used, it is difficult to determine an accurate data sampling point.

  In view of the problems described above, an object of the present invention is to perform threshold determination with high accuracy and to determine a more accurate data sampling point.

In order to achieve the above-described object, the radio demodulation circuit of the present invention includes:
A digital demodulator that demodulates the multilevel FSK signal;
A data determiner for determining a threshold value of the demodulated output of the digital demodulator;
A threshold value holder for holding a threshold value of the data determiner;
Is provided. As a result, more accurate threshold determination can be performed and reception characteristics can be improved.

The present invention detects a change point in the demodulated output, and then detects a synchronization point of the multilevel FSK signal based on the detected change point;
A demodulated signal synchronization output unit that outputs a threshold determination result of the data determination unit at the synchronization point and a synchronization clock synchronized with a transmission rate of the demodulation output;
Further comprising
There is a mode. In this case, it is preferable to further include a synchronization point holder that holds the synchronization point.

The present invention further comprises a multi-level synchronization point determiner,
The multi-level FSK signal has a plurality of frequency components in which a modulation degree is set in accordance with each code superimposed on the signal,
The demodulated output has a plurality of voltage components corresponding to the plurality of frequency components,
The multi-level synchronization point determiner has a voltage transition between the voltage components corresponding to the frequency components whose modulation degrees are equally separated from a center frequency of the multi-level FSK signal in the threshold determination result. Selectively determining the resulting synchronization point as a synchronization point;
There is a mode.

Further, the present invention further comprises a multi-level synchronization point determiner,
The multi-level FSK signal has a plurality of frequency components in which a modulation degree is set in accordance with each code superimposed on the signal,
The demodulated output has a plurality of voltage components corresponding to the plurality of frequency components,
The multi-level sync point determiner is configured such that, from the sync point group detected by the sync point detector, the frequency component having the maximum modulation degree with respect to a center frequency of the multi-level FSK signal in the threshold determination result. Extracting the synchronization point where a voltage transition occurs between the voltage components according to, and determining the extraction synchronization point as a synchronization point;
There is a mode. In this case, the threshold value holder sets a threshold value that can be pseudo-binary discriminated as the threshold value at the time of multi-level modulation, and the multi-level synchronization point determiner determines the threshold value determination. There is a further aspect in which the synchronization point at which a binary change occurs in the result is extracted, and the extracted synchronization point is determined as the synchronization point. Thereby, even when a synchronization point is detected based on a specific voltage transition, a synchronization point equivalent to that at the time of binary modulation can be detected, and the transmission side and the reception side can be synchronized earlier.

The present invention provides a maximum value holder for holding the maximum value of the demodulated output,
A minimum value holder for holding a minimum value of the demodulated output;
An optimum threshold value calculator for calculating an optimum value of the threshold value from the output of the maximum value holder and the output of the minimum value holder;
With
There is an aspect in which the threshold value holder holds the threshold value calculated by the optimum threshold value calculator. As a result, an optimum threshold value can be calculated from the received data itself, and a more optimum threshold value determination can be made. In addition, since it becomes possible to set a threshold corresponding to the radio wave condition at that time for each communication, stable communication is possible at any time.

In the present invention, after the synchronization point is determined based on the synchronization point holding count number held in the synchronization point holder, after the synchronization point is determined, any time axis centering on the determined synchronization point is determined. A synchronization point monitor that extracts a synchronization point detected by the synchronization point detector in a range and determines the extracted synchronization point as a synchronization point;
In addition,
There is such an aspect.

In addition, a wireless communication LSI that incorporates the wireless demodulation circuit of the present invention and performs wireless transmission and reception;
An antenna for transmitting and receiving a wireless signal of the wireless communication LSI;
A microcontroller for controlling the wireless communication LSI;
A key input device for inputting to the microcontroller;
A display device for performing arbitrary display under the control of the microcontroller;
A remote controller can be configured.

  According to the present invention described above, an accurate data sampling point can be determined by detecting an accurate synchronization point, and data can be accurately determined even when high-speed transmission is performed. Further, since the data sampling point is determined in a state where the synchronization point is always followed, it is possible to perform communication while correcting an error in clock accuracy, which contributes to speeding up of wireless communication. As a result, more accurate threshold determination can be performed and reception characteristics can be improved.

  Further, even when a synchronization point is detected based on a specific voltage transition, a synchronization point equivalent to that at the time of binary modulation can be detected, and the transmission side and the reception side can be synchronized earlier.

  In addition, the optimal threshold value can be calculated from the received data itself, enabling more optimal threshold judgment, and setting a threshold value according to the radio wave condition at that time for each communication. Communication becomes possible, and a stable wireless receiver can be realized.

  With the configuration of the present invention described above, even in multi-level FSK wireless communication, more accurate data determination and acquisition of synchronization on the transmission side and reception side become possible, thereby enabling high-speed communication and improving wireless reception characteristics. It becomes possible.

  Hereinafter, a radio demodulation circuit showing an embodiment of the present invention will be specifically described with reference to the drawings.

(Embodiment 1)
A radio demodulation circuit according to the first embodiment of the present invention will be described. FIG. 1 is a block diagram showing a configuration example of the radio demodulation circuit according to the first embodiment. Specifically, the circuit configuration is related to data threshold determination and synchronization point determination during multilevel FSK wireless communication.

  First, the configuration of the present embodiment will be described. In FIG. 1, reference numeral 1 denotes a digital demodulator. The digital demodulator 1 receives a multilevel FSK signal S1 obtained by down-converting, filtering, and digitizing a high-frequency signal. The digital demodulator 1 performs digital FSK demodulation by performing frequency voltage conversion of the input multilevel FSK signal S1. Reference numeral 2 denotes a data determiner. The data determiner 2 performs quaternary data determination from the output signal of the demodulated baseband signal S2 frequency-voltage converted by the digital demodulator 1, and outputs a demodulated data signal S3. 3 is a threshold value holder. The threshold value holder 3 holds the determination threshold value of the data determiner 2 and outputs threshold value information S4. Reference numeral 6 denotes a demodulated signal synchronous output device. The demodulated signal synchronous output unit 6 generates a clock signal synchronized with the transmission speed of the threshold value information S4 and the demodulated data signal S3, and then synchronously outputs the clock signal and the demodulated data signal S3 as digital data. Hereinafter, the clock signal output from the demodulated signal synchronous output unit 6 is referred to as a synchronous digital clock S7, and the demodulated data signal S3 output from the demodulated signal synchronous output unit 6 in synchronization with the synchronous digital clock S7 is referred to as synchronous digital data S8. . Reference numeral 4 denotes a sync point detector. The synchronization point detector 4 detects the synchronization point by detecting the voltage change point of the demodulated baseband signal S2. Hereinafter, the information regarding the synchronization point detection position detected by the synchronization point detector 4 is referred to as synchronization point detection position information S5. Reference numeral 5 denotes a synchronization point holder. The synchronization point holder 5 holds the synchronization point detection position information S5 and holds the synchronization points accumulated and held as the optimum synchronization point. Hereinafter, information regarding the synchronization point position output by the synchronization point holder 5 is referred to as synchronization point position information S6.

The detailed operation of the radio demodulation circuit according to the first embodiment will be described below. High frequency signal in advance
・ Down-conversion processing to enable digital processing even at low processing speeds,
A filtering process for removing signals outside the desired frequency band;
-A / D conversion processing,
As a result, the multilevel FSK signal S1 is generated.

  The multi-level FSK signal S1 generated in this way is input to the digital demodulator 1. The digital demodulator 1 performs a frequency voltage conversion process on the input multilevel FSK signal S1 to generate a demodulated baseband signal S2. There are various methods of frequency-voltage conversion processing in this case, but any method may be used. The data determiner 2 determines the threshold value of the demodulated baseband signal S2 and outputs threshold value information S4.

  The threshold information S4 functions as a data determination threshold. The threshold value information S4 is held in the threshold value holder 3. The threshold value holder 3 may be any storage device as long as it can hold a value. The threshold value holder 3 includes a ROM, a RAM, and a register. The threshold value may be set as a fixed value. In the following description, as an example, the operation of a radio demodulating circuit including a threshold value holder 3 composed of a register will be described. There are various multilevel FSK modulations. In the following description, quaternary FSK modulation is used as an example.

  As the number of modulations in FSK modulation increases to 8 and 16, the number of threshold values changes accordingly. Therefore, in this radio demodulation circuit, it is necessary to increase the number of threshold values held in accordance with the fluctuation. In the 4-level FSK modulation, the modulation frequencies are sequentially set in accordance with the codes “00”, “01”, “11”, and “10” superimposed on the multi-level FSK signal S1. Taking such a system as an example, the operation of the present embodiment will be described as follows. That is, there are three threshold values for determining each code. The first threshold value is “00” and “01”, and the second threshold value is “01” and “11”. The third threshold value is used for the determination of “11” and “10”, respectively. The threshold determination unit 3 determines a code in the demodulated baseband signal S2 based on the three thresholds. The demodulated data signal S3, which is the data determination result, is sent to the demodulated signal synchronization output unit 6. The demodulated signal synchronous output unit 6 generates a synchronous digital clock S7 corresponding to a known transmission rate. When the value of the demodulated data signal S3 is “00”, two bits “0” and “0” are generated and output as the synchronous digital data S8 in synchronization with the synchronous digital clock. Thus, by performing data determination in the state of digital data, it becomes possible to perform threshold determination with higher accuracy. Further, since the threshold value can be arbitrarily set in the threshold value holder 3 (register), it is possible to easily cope with, for example, a case where the modulation degree is changed.

  The synchronization point detector 4 detects a synchronization point by detecting a change point (specifically, a voltage change point) of the demodulated baseband signal S2. Various methods are conceivable for detecting the change point of the demodulated baseband signal S2. As an example of the simplest configuration, a method using the detection point of the zero cross point as the change point will be described below. Assuming that the demodulated baseband signal S2 is digital data and is represented by a complement of “2”, the most significant bit is a sign bit. The change point of the sign bit, that is, the point at which “0” is changed to “1” and “1” is changed to “0” is the zero cross point. The synchronization point detector 4 detects this change point by performing an oversampling process on the demodulated baseband signal. The change point can be detected with higher accuracy by increasing the number of oversampling, but here, a case where 10 times oversampling is performed will be described as an example.

  When 10 times oversampling is performed, there are changing points from 0 to 9, and information indicating which changing point is the timing at which the changing point is detected by the synchronizing point detector 4 is 0-9. It is sent to the synchronization point holder 5 as point detection position information S5. The synchronization point holder 5 accumulates the information of the synchronization point detection position information S5, determines the most likely change point as the synchronization point, and holds the change point as the synchronization point. Specifically, since values that can be taken as information are 0 to 9, counters corresponding to the respective values are provided, and the corresponding counter is incremented by 1 each time the information is sent. The change point having the highest counter value is regarded as a synchronization point, and synchronization point position information S6n indicating the change point regarded as the synchronization point is sent to the demodulated signal synchronization output unit 6.

  The demodulated signal synchronization output unit 6 determines, as a data sampling point, a point at which a half of the transmission speed has elapsed from the synchronization point based on the input synchronization point position information S6. Here, the transmission rate is a sampling period. The demodulated signal synchronous output unit 6 determines the value of the demodulated data signal S3 at the determined data sampling point, and outputs the determination result as synchronous digital data S8.

  The demodulated signal synchronization output unit 6 generates a clock that rises at the point of the synchronization point position information S6 and falls at the data sampling point when the data sampling timing on the reception side of the synchronization digital data S8 falls, Output as clock S7.

  As described above, in the present embodiment, it is possible to perform more accurate data determination by determining a synchronization point based on change point detection and performing data sampling. Therefore, even when the transmission rate is increased, it is possible to suppress the deterioration of reception characteristics.

(Embodiment 2)
A radio demodulation circuit according to the second embodiment of the present invention will be described. FIG. 2 is a block diagram showing a configuration example of the radio demodulation circuit according to the second embodiment, and shows a circuit configuration of a main part for detecting a synchronization point at the time of multilevel FSK modulation.

  In the second embodiment, the multi-level synchronization point determination unit 7 is further added to the configuration of the first embodiment (FIG. 1). The multi-level synchronization point determination unit 7 determines only the code change point of a specific 4-level FSK code in the synchronization point detection position information S5 and the demodulated data signal S3 as a synchronization point. Hereinafter, information regarding the multi-level synchronization point detection position determined by the multi-level synchronization point determination unit 7 is referred to as multi-level synchronization point detection position information S9. The multi-level synchronization point detection position information S9 is supplied to the synchronization point holder 5.

  The operation of the radio demodulation circuit according to the second embodiment will be described below. In the case of 4-level FSK wireless communication, the 4-level code in the demodulated data signal S3 determined by the multilevel synchronization point determination unit 7 is “00” to “10”, “10” to “00”, or “ From “01” to “11”, “11” is changed to “01”, that is, as shown in FIG. 4, the multi-level synchronization point determination unit 7 is ± the same from the voltage corresponding to the center frequency of the band. A synchronization point determination is performed using only a sampling point (hereinafter referred to as a code change point) that has made a voltage transition to a code-corresponding voltage corresponding to a remote modulation degree as a synchronization point, and the determination result is synchronized as multilevel synchronization point detection position information S9 Send to the point holder 5.

  In the case of detecting the synchronization point by the code change point in the detection of the synchronization point in the case of multiple values, the code may transition in a state where the code change point is away from the synchronization point (does not match). For example, at the code change point 100 in FIG. 5, the code changes from “01” to “10”, and at the code change point 102, the code changes from “00” to “11”. The points 100 and 102 are separated from the synchronization point, and the two points do not match. For this reason, the synchronization point is detected, for example, using the code change point from “00” to “10” and the code change point from “01” to “11” as the synchronization point, or from “10” to “00”. The code change point to “11” and the code change point “11” to “01” may be set as the synchronization point. In this way, by using only the code change points separated by the same modulation degree as the synchronization point, the synchronization point can be detected more accurately as indicated by the detection point 101 in FIG.

  Further, in the case of quaternary FSK wireless communication, the multi-level synchronization point determination unit 7 uses the demodulated data signal S3 in the demodulated data signal S3, the code change point at which the quaternary code transitions from “00” to “10”, The code change point at which the transition is made, that is, the code change point at which the code shifts most away may be selectively determined as the synchronization point. In this case, a code change point in both directions is not determined as a synchronization point, but a code change point at which a code changes from “00” to “10” and a code change point at which a code changes from “10” to “00”. Any one of the code change points may be determined as a synchronization point, which has the following merit.

  Assume that there is a frequency offset. In this case, since there is an influence of offset, in the process of determining code change points that are separated by the same degree of modulation as synchronization points, four code change points 103, 104, 105, and 106 are represented as shown in FIG. There is a possibility that the synchronization points may be dispersed because the synchronization points are determined. On the other hand, when the process of determining only the code change point having the farthest modulation degree as the synchronization point is performed, only the two code change points 104 and 105 are selectively determined as the synchronization point. Therefore, the synchronization point can be accurately detected even when there is a frequency offset.

  Note that only the code change point where the code transitions from “00” to “10” or only the code change point where the code transitions from “10” to “00” may be determined as the synchronization point. By doing so, it becomes possible to selectively determine the code change point 104 or the code change point 105 shown in FIG. 5 as the synchronization point, and the synchronization point can be obtained more accurately.

  In general, when synchronization is established between a transmission device and a reception device in wireless communication, synchronization is achieved with a bit synchronization code. In this case, if the transmitted code is continuous data of a code whose transmission rate can be determined, that is, 4-level FSK, “00” and “10” are repeated. Therefore, when synchronizing with the bit synchronization code, the threshold value holder 3 can pseudo-binary discriminate the value located in the middle among the values shown in the above three threshold information. Set as threshold. By doing so, as shown in FIG. 6, the multi-level synchronization point determination unit 7 selectively extracts the synchronization point where the binary change occurs in a pseudo manner, and the code determination result is only “00” and “10”. It becomes. Hereinafter, the reason why the code determination result by the multi-level synchronization point determination unit 7 is only “00” and “10” will be described.

  When a code determination process including at least “00” and “10” as a code determination result by the multi-level synchronization point determination unit 7 is performed in the radio demodulation circuit synchronized with the bit synchronization code, the sampling points shown in FIG. When 200 and 201 are set as the initial synchronization points, the code change point between “11” and “01” is determined as the synchronization point thereafter, and therefore, between code “11” and code “01”. Will be synchronized. Once synchronization is established in this state, the code change point from the code “00” to the code “10” is no longer detected and the synchronization point does not transition, and therefore the operation continues at the wrong synchronization timing. Will be.

  On the other hand, in the case of performing a determination process in which the code determination result by the multi-level synchronization point determination unit 7 is only the codes “00” and “10”, the sampling points 202 and 203 shown in FIG. Even when sampling is performed, a correct synchronization point can be determined, and synchronization can be quickly acquired on the transmission side and the reception side. Further, after synchronization is established between the transmission side and the reception side, the synchronization point can be corrected during communication by setting the threshold value to three again. As the initial synchronization point determination process, for example, as shown in the first embodiment, the synchronization point can be determined based on the synchronization count holding count held in the synchronization point holder 5.

(Embodiment 3)
A radio demodulation circuit according to the third embodiment of the present invention will be described. FIG. 3 is a block diagram showing a configuration example of a radio demodulation circuit according to the third embodiment, and shows a circuit configuration of a main part for detecting a synchronization point at the time of multilevel FSK modulation.

  In the third embodiment, the configuration of the second embodiment (FIG. 2) further includes a maximum value holder 8, a minimum value holder 9, and an optimum threshold value calculator 10. The maximum value holder 8 holds the maximum value of the demodulated baseband signal S2. Hereinafter, information regarding the maximum value of the demodulated baseband signal S2 output from the maximum value holder 8 is referred to as maximum value information S10. The minimum value holder 9 holds the minimum value of the demodulated baseband signal S2. Hereinafter, information regarding the minimum value of the demodulated baseband signal S2 output from the minimum value holder 9 is referred to as minimum value information S11. The optimum threshold value calculator 10 calculates an optimum threshold value from the maximum value information S10 and the minimum value information S11. Hereinafter, information relating to the optimum threshold output from the optimum threshold calculator 10 is referred to as optimum threshold information S12. The optimum threshold value information S12 is supplied to the threshold value holder 3.

  Next, a detailed operation of the radio demodulation circuit according to the third embodiment will be described. When performing 4-level FSK wireless communication, the maximum value holder 8 holds the maximum value of the demodulated baseband signal S2 and supplies the output maximum value information S10 to the optimum threshold value calculator 10. The minimum value holder 9 holds the minimum value of the demodulated baseband signal S2, and supplies the minimum value information S11 to the optimum threshold value calculator 10. The optimum threshold value calculator 10 determines an optimum threshold value from the output maximum value information S10 and the minimum value information S11. As shown in FIG. 4, the optimum threshold value is obtained by dividing the maximum value and the minimum value of the demodulated baseband signal S2 into four. That is, the first threshold value is (maximum value−minimum value) × 3/4, the second threshold value is (maximum value−minimum value) × 2/4, and the third threshold value is (maximum value). −Minimum value) × 1/4.

  By sending the threshold value thus determined to the threshold value holder 3, even if there is a variation in the frequency modulation degree on the transmission side, an optimum threshold value is determined according to the radio wave condition, and reception characteristics are deteriorated. Can be prevented.

(Embodiment 4)
A radio demodulation circuit according to a fourth embodiment of the present invention will be described. FIG. 7 is a block diagram showing a configuration example of a radio demodulation circuit according to the fourth embodiment, and shows a circuit configuration of a main part for detecting a synchronization point at the time of multilevel FSK modulation. In the fourth embodiment, the synchronization point monitor 11 is further added to the configuration of the first embodiment (FIG. 1). The synchronization point monitor 11 is in a certain degree along the synchronization period estimated from the synchronization point group defined in advance in the synchronization point group (code change point group) detected by the synchronization point detector 4 (for example, While the detected synchronization point (within a range of ± 0.2 sampling time) is regarded as an accurate synchronization point, the detected synchronization point at some distance from the synchronization period (within the same range as described above) Not considered a sync point. The synchronization point monitor 11 sends synchronization point monitoring information S9 indicating the result of such synchronization point monitoring to the synchronization point holder 5.

  The detailed operation of the radio demodulation circuit according to the fourth embodiment will be described below. In the case of 4-level FSK wireless communication, the synchronization point monitor 11 does not consider a synchronization point (code change point) that is somewhat distant from the synchronization point period as an accurate synchronization point based on the synchronization point position information S6. After generating information S9 having the other synchronization points (synchronization points along the synchronization point period to some extent) as accurate synchronization points, the information S9 is sent to the synchronization point holder 5. Hereinafter, as shown in FIG. 8, when synchronization is first established, synchronization is performed with a signal that causes a code transition from “00” to “10”, or from “10” to “00”. A case where it operates as a synchronization point will be described as an example.

  In this case, the sync point monitor 11 sets in advance a sync point monitoring range W having an arbitrary width around the accurate sync point (in this case, the code change point 101) on the time axis. The synchronization point monitor 11 selectively extracts a synchronization point (code change point) detected in the synchronization point monitoring range W as an accurate synchronization point, and is detected in a time zone other than the synchronization point monitoring range W. Is not extracted as an exact synchronization point. Accordingly, for example, as shown in FIG. 8, the synchronization point (code change point) 100 detected by the synchronization point detector 4 that the code transition from “01” to “10” is detected, or “00” to “11”. As for the synchronization point 102 detected by the synchronization point detector 4 that the code has been changed to “”, the detection timing is not included in the synchronization point monitoring range W. Therefore, the synchronization point monitor 11 does not regard these synchronization points 100 and 102 as accurate synchronization points.

  As described above, the synchronization point monitor 11 does not regard the synchronization points 100 and 102 as accurate synchronization points, but generates synchronization point monitoring information S9 that regards only the synchronization point 101 as an accurate synchronization point and generates the synchronization point holder 5. Therefore, in the synchronization point holder 5, only the synchronization point 101 detected in the synchronization point monitoring range W among the synchronization point group detected by the synchronization point detector 4 is selectively held as an accurate synchronization point. Will be. In addition, there is a limit on the number of times that a synchronization point detected at a certain distance or more by the synchronization point monitor 11 is not regarded as an accurate synchronization point. This limit number may be a fixed value or a variable value. When the communication partner is changed, the synchronization point is shifted and communication is not possible while the communication is under the limit number of times that is not considered as the synchronization point. When a synchronization point is detected, that point is regarded as a synchronization point. That is, the point is corrected (set) as a synchronization point with the changed communication partner.

  By monitoring such a synchronization point by the synchronization point monitor 11, a stable synchronization point can be detected even during four-value FSK wireless communication, and stable even if there is temporary mixing of unnecessary noise. Wireless 4-level FSK communication can be continued.

(Embodiment 5)
Embodiment 5 of the present invention shown in FIG. 9 is a remote controller in which the wireless demodulation circuit of the present invention is incorporated. In FIG. 9, 12 is an antenna through which radio is transmitted and received. Reference numeral 13 denotes a wireless communication IC in which the wireless demodulation circuit according to any one of Embodiments 1-4 is incorporated. Reference numeral 14 denotes a microcontroller. Reference numeral 15 denotes a display device. Reference numeral 16 denotes a key input unit.

  The detailed operation of the remote controller according to the fifth embodiment will be described below. In general wireless communication, an operation is started by first synchronizing with a communication partner. Radio waves from the communication partner are received by the antenna 12. The reception signal is input to the wireless communication IC 13 as a wireless reception signal S13. The wireless communication IC 13 includes any one of the radio demodulation circuits according to the first to fourth embodiments, so that synchronization with the communication partner can be established at an early stage and stable multilevel FSK communication can be realized. The wireless communication IC 13 sends the wireless reception demodulation data S15 to the microcontroller 14. The microcontroller 14 generates a signal for informing the communication partner that synchronization has been established from the radio reception demodulated data as radio transmission modulation data S16, and sends it to the radio communication IC 13. The wireless communication IC 13 multi-value modulates the data S16 and transmits it as a radio wave via the antenna 12 as a radio transmission signal S14.

  For example, when the communication partner of the remote controller is an air conditioner, when the air conditioner is OFF, the operator first performs a key input indicating an instruction to turn on the air conditioner on the key input unit 16. . This instruction is sent from the key input unit 16 to the microcontroller 14 as a key input signal S18. The microcontroller 14 generates command data for turning on the air conditioner and then converts the command data into the wireless modulation data S16. The microcontroller 14 sends the radio modulation data S16 to the radio communication IC 13. The radio communication IC 13 generates a radio modulation signal S14 on which the radio modulation data S16 is superimposed and outputs the radio modulation signal S14 via the antenna 12 as radio waves.

  When the air conditioner that is the wireless communication partner returns a wireless radio wave on which information such as that the air conditioner is turned on or the current room temperature and set temperature is superimposed, the antenna 12 receives the wireless radio wave and wirelessly receives it. The received signal S13 is sent to the wireless communication IC 13. The wireless communication IC 13 sends the wireless demodulated data S15 to the microcontroller 14. The microcontroller 14 discriminates that the air conditioner is turned on, the current room temperature, the set temperature, etc. from the sent information, and then generates a display device control signal S17 indicating the discrimination result to the display device 15. send. Based on the display device control signal S17, the display device 15 displays that the air conditioner is in the ON state, the current room temperature, the set temperature, and the like.

  By performing stable multilevel FSK communication with the communication partner in this way, it is possible to perform high-speed communication even with the same data amount, and it is possible to suppress current consumption. Thereby, the battery consumption of a remote controller can be suppressed. By doing so, the battery can be miniaturized and the remote controller itself can be miniaturized. In addition, high-speed bidirectional communication becomes possible, and one-to-many communication that could not be performed by an infrared remote controller so far becomes possible, thereby increasing added value.

  The radio demodulation circuit of the present invention can realize high-speed communication without degrading radio reception characteristics because it can realize high-speed transmission speed and more accurate and high-accuracy communication in multi-level FSK modulated radio communication. It is useful in the required radio field.

1 is a block diagram showing a schematic configuration of an FSK radio using a radio demodulation circuit according to a first embodiment of the present invention. The block diagram which shows schematic structure of the FSK radio | wireless machine using the radio | wireless demodulation circuit of Embodiment 2 of this invention. The block diagram which shows schematic structure of the FSK radio | wireless machine using the radio | wireless demodulation circuit of Embodiment 3 of this invention. The timing chart figure of threshold value judgment of the demodulation baseband signal of Embodiment 2 of the present invention. The figure which shows the code transition and detection change point at the time of 4 value FSK radio | wireless communication of Embodiment 2 of this invention. The code | cord | chord judgment timing chart figure at the time of 4 value FSK radio | wireless communication of Embodiment 2 of this invention. The block diagram which shows schematic structure of the FSK radio | wireless machine using the radio | wireless demodulation circuit of Embodiment 4 of this invention. The figure which shows the code transition at the time of the 4-value FSK radio | wireless communication of Embodiment 4 of this invention, and a synchronous point monitoring range. The block diagram which shows schematic structure of the remote controller of Embodiment 5 of this invention.

Explanation of symbols

Digital demodulator 2 Data determination means 3 Threshold holding means 4 Synchronization detection circuit 5 Synchronization point holding means 6 Demodulated signal synchronization output circuit 7 Multi-level synchronization point determination circuit 8 Maximum value holding means 9 Minimum value holding means 10 Optimal threshold Calculation means 11 Synchronization point monitoring means 12 Antenna 13 Wireless communication IC
14 Microcontroller 15 Display device 16 Key input part S1 Multi-level FSK signal S2 Demodulated baseband signal S3 Demodulated data signal S4 Threshold information S5 Sync point detection position information S6 Sync point position information S7 Sync digital clock S8 Sync digital data S9 Multi Value synchronization point detection position information S10 Maximum value information S11 Minimum value information S12 Optimal threshold information S13 Radio reception signal S14 Radio transmission signal S15 Reception demodulation data signal S16 Transmission modulation data signal S17 Display device control signal S18 Key input signal 10001 10 change detection point 101 detection change point 10200 to 11 change change detection point 103 11 to 01 change change detection point 104 10 to 00 change change detection point 10500 to 10 change change detection point 10601 to 11 Change point detected at change 200 Code size Sampling point 201 codes determined sampling point 202 codes determined sampling point 203 codes determined sampling point

Claims (9)

A digital demodulator that demodulates the multilevel FSK signal;
A data determiner for determining a threshold value of the demodulated output of the digital demodulator;
A threshold value holder for holding a threshold value of the data determiner;
Comprising
Wireless demodulation circuit. A synchronization point detector for detecting a synchronization point of the multi-level FSK signal based on the detected variation point after detecting a variation point in the demodulated output;
A demodulated signal synchronization output unit that outputs a threshold determination result of the data determination unit at the synchronization point and a synchronization clock synchronized with a transmission rate of the demodulation output;
Further comprising
The radio demodulation circuit according to claim 1. A synchronization point holder for holding the synchronization point;
In addition,
The radio demodulation circuit according to claim 2. It further comprises a multi-level sync point determiner,
The multi-level FSK signal has a plurality of frequency components in which a modulation degree is set in accordance with each code superimposed on the signal,
The demodulated output has a plurality of voltage components corresponding to the plurality of frequency components,
The multi-level synchronization point determiner has a voltage transition between the voltage components corresponding to the frequency components whose modulation degrees are equally separated from a center frequency of the multi-level FSK signal in the threshold determination result. Selectively determining the resulting synchronization point as a synchronization point;
The radio demodulation circuit according to claim 2. It further comprises a multi-level sync point determiner,
The multi-level FSK signal has a plurality of frequency components in which a modulation degree is set in accordance with each code superimposed on the signal,
The demodulated output has a plurality of voltage components corresponding to the plurality of frequency components,
The multi-level sync point determiner is configured such that, from the sync point group detected by the sync point detector, the frequency component having the maximum modulation degree with respect to a center frequency of the multi-level FSK signal in the threshold determination result. Extracting the synchronization point where a voltage transition occurs between the voltage components according to, and determining the extraction synchronization point as a synchronization point;
The radio demodulation circuit according to claim 2. The threshold value holder sets a threshold value capable of pseudo binary discrimination as the threshold value in multi-level modulation,
The multi-level synchronization point determiner extracts the synchronization point where a binary change occurs in a pseudo manner in the threshold determination result, and determines the extraction synchronization point as a synchronization point.
The radio demodulation circuit according to claim 5. A maximum value holder for holding the maximum value of the demodulated output;
A minimum value holder for holding a minimum value of the demodulated output;
An optimum threshold value calculator for calculating an optimum value of the threshold value from the output of the maximum value holder and the output of the minimum value holder;
With
The threshold value holder holds the threshold value calculated by the optimum threshold value calculator;
The radio demodulation circuit according to claim 1. After the synchronization point is determined based on the synchronization point holding count number held in the synchronization point holder, and after the synchronization point is determined, the synchronization is performed in an arbitrary range of the time axis centering on the determined synchronization point. A synchronization point monitor that extracts a synchronization point detected by the point detector and determines the extracted synchronization point as a synchronization point,
In addition,
The radio demodulation circuit according to claim 3. A wireless communication LSI that incorporates the wireless demodulation circuit according to claim 1 and performs wireless transmission and reception;
An antenna for transmitting and receiving a wireless signal of the wireless communication LSI;
A microcontroller for controlling the wireless communication LSI;
A key input device for inputting to the microcontroller;
A display device for performing arbitrary display under the control of the microcontroller;
Comprising
Remote controller.

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