JP2007201626A - Receiving unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable reception of a signal including a pulse with high accuracy, while restraining the increase of a circuit scale. <P>SOLUTION: A comparator 14 outputs to a counter 15 "1" if a signal from a low-noise amplifier 12 is not smaller than a threshold set by a threshold set circuit 13, or "0" if the signal is not larger than the threshold. The counter 14 counts the number of "1" output from the comparator 14. A decision circuit 17 compares a counter value C1 with a predetermined value SH at the timing of being output from a bit synchronization circuit 16, and decides presence/absence of a pulse by letting "1" if the counter value C1 is greater than the predetermined value SH, while letting "0" if the counter value C1 is smaller. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a receiver, and is particularly suitable for application to a pulse radio communication system.

As a conventional wireless communication system using pulses, as disclosed in Patent Document 1, there is a UWB-IR (Ultra Wide Bandwidth-Impulse Radio) system which is a kind of spread spectrum system. In this UWB-IR system, data can be transmitted without using a carrier wave by transmitting a pulse of about nanosecond time.
JP 2004-72589 A

  However, in the conventional pulse radio communication system, in order to detect a pulse on the receiver side, it is necessary to multiply the pulse transmitted from the transmitter and the pulse generated on the receiver side in synchronization. For this reason, in the conventional pulse radio communication system, it is necessary to generate the same pulse as the pulse transmitted from the transmitter on the receiver side, or to match the timing of these pulses with high accuracy, and the configuration of the receiver is complicated. There was a problem of becoming.

  Therefore, an object of the present invention is to provide a receiver that can accurately receive a signal including a pulse while suppressing an increase in circuit scale.

In order to solve the above-described problem, according to a receiver according to an aspect of the present invention, a pulse signal receiving unit that receives a signal including a pulse, a counting unit that counts a wave number included in the pulse, and the wave number And determining means for determining the presence or absence of a pulse based on the count value.
Thereby, it is possible to demodulate the signal including the pulse by counting the wave number included in the pulse. This makes it possible to digitize the demodulation process, generate the same pulse as the pulse transmitted from the transmitter on the receiver side, or perform multiplication while accurately matching the timing of these pulses. Therefore, it is possible to accurately receive a signal including a pulse while suppressing an increase in circuit scale.

According to the receiver of one aspect of the present invention, the pulse signal receiving unit that receives a signal including a pulse, the prescaler that divides the received signal, and the pulse that is divided by the prescaler. It is characterized by comprising counting means for counting the wave number contained therein, and determining means for determining the presence or absence of a pulse based on the count value of the wave number.
Thereby, even in a high frequency band where the wave number cannot be counted directly, a demodulation operation can be performed, and a signal including a pulse can be accurately received while suppressing an increase in circuit scale.

In the receiver according to one aspect of the present invention, the determination unit determines the presence or absence of a pulse based on a reference value of the count value or a specific bit of the prescaler.
Thereby, it is possible to determine the presence or absence of a pulse only from a specific bit of the count value, and it is possible to efficiently demodulate a signal including the pulse.

According to the receiver of one aspect of the present invention, the determination unit stops the demodulation operation of the signal received this time when the count value exceeds a predetermined value.
Thereby, an unnecessary counting operation can be omitted without affecting the determination result of the presence / absence of a pulse, and a signal including a pulse can be accurately demodulated while reducing power consumption.

In the receiver according to the aspect of the present invention, the determination unit estimates a noise level based on a count value counted in a predetermined section.
As a result, it is possible to transmit data with the minimum power capable of determining data, and it is possible to reduce transmission power without degrading demodulation accuracy.
According to the receiver of one embodiment of the present invention, the signal including the pulse is an OOK signal or an FSK signal.

Thus, demodulation can be performed by counting the number of waves included in the pulse, and multilevel modulation can be employed by using the FSK signal.
Further, according to the receiver of one aspect of the present invention, the synchronization acquisition unit that acquires the synchronization of the received signal by setting the window timing so that the count values coincide in the first half period and the second half period. Is further provided.

  As a result, the wave number can be counted only in the section where the pulse exists, and the counting operation can be prevented from being performed in the section where the pulse does not exist. For this reason, it is possible to prevent the noise included in the section where no pulse is present from affecting the count value, and it is possible to efficiently demodulate the signal including the pulse while suppressing an increase in circuit scale.

The receiver according to one aspect of the present invention further includes synchronization acquisition means for acquiring synchronization of the received signal so that the timing at which the count value exceeds the threshold is in the center of the window.
As a result, the synchronization of the received signal can be quickly performed, and the signal including the pulse can be demodulated at high speed while suppressing an increase in circuit scale.

Hereinafter, a receiver according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of a receiver according to the first embodiment of the present invention, and FIG. 2 is a diagram showing a data demodulation method of the receiver of FIG.
In FIG. 1, the output from the antenna 11 that receives a signal including a pulse TW as a radio wave, the bandpass filter 19 that removes unnecessary band components from the signal received by the antenna 11, and the bandpass filter 19 are output to the receiver. A low noise amplifier 12 for amplifying the received signal, a threshold setting circuit 13 for setting a threshold for discriminating the wave included in the pulse as a logical value “0” or “1”, and comparing the wave included in the pulse with the threshold A comparator 14 that detects a wave included in the pulse, a counter 15 that counts the wave number detected by the comparator 14, a bit synchronization circuit 16 that performs synchronization acquisition of a signal including the pulse, and a count of the wave number counted by the counter 15 A determination circuit 17 for determining the presence or absence of a pulse based on the value is provided. An example of the signal including the pulse TW is an OOK (On Off Keying) signal. Data “1” is assigned to a section with the pulse TW, and data “0” is assigned to a section without the pulse TW. be able to.

  The signal including the pulse TW received by the antenna 11 is amplified to a predetermined level by the low noise amplifier 12 after a necessary band component is removed by the band pass filter 19, and the threshold setting circuit 13 and the comparator 14. Is input. Here, the threshold value setting circuit 13 determines the threshold value of the comparator 14 based on the signal from the low noise amplifier 12. As a method of determining the threshold value of the comparator 14, the threshold value can be set at a point that is 1/2 of the peak value of the input signal. Alternatively, at the start of communication, a change in the count value by the counter 15 may be observed while sequentially decreasing the threshold value, the count value of one section may be compared with an ideal count value, and the threshold value may be adjusted according to the magnitude.

  On the other hand, in the comparator 14, the signal from the low noise amplifier 12 is compared with a threshold value, converted into a signal S1 having a logical value “0” or “1”, and then output to the counter 15 (FIG. 2A). That is, the comparator 14 outputs “1” to the counter 15 if the signal from the low noise amplifier 12 is equal to or greater than the threshold set by the threshold setting circuit 13, and “0” if it is less than that. The counter 15 counts the number of “1” output from the comparator 14 (FIG. 2C), and outputs the count value C 1 to the bit synchronization circuit 16 and the determination circuit 17.

  Here, the bit synchronization circuit 16 can set the window signal M1 based on the count operation by the counter 15 and can capture the synchronization of the received signal (FIG. 2B). As a method for setting the window signal M1, the timing of the window signal M1 can be set so that the count values coincide in the first half period and the second half period. That is, while the window signal M1 is “H” in a state in which the reception signal is not synchronized, the counter 15 is set with the period of 1/2 of Tw as an up counter and the remaining period of 1/2 as a down counter. Make it work. That is, when a pulse is input during the first half of the Tw period, the counter 15 increases the count value, and when a pulse is input during the second half of the Tw period, the counter value is increased. To go down. Then, the window timing is operated so as to synchronize from the count values at the intermediate point and the final point of the window signal M1. In the state where the received signal is not synchronized and no pulse is input during the Tw period, the count values at the intermediate point and the final point of the window are both zero (or below a certain value). If the count value of the Tw period for a certain number of times is zero, the timing of the window signal M1 is shifted by a predetermined amount, and the same operation is repeated, so that one pulse is added to the timing of the window signal M1. Parts can be entered.

  Then, the bit synchronization circuit 16 outputs the window signal M1 to the counter 15, and the counter 15 can perform the counting operation only during the period when the window signal M1 is output from the bit synchronization circuit 16. That is, the counter 15 counts according to the output from the comparator 14 when the window signal (Enable) output from the bit synchronization circuit 16 is “H”, and counts regardless of the output from the comparator 14 when “L”. The operation can be stopped.

  On the other hand, the determination circuit 17 compares the count value C1 with the predetermined value SH at the timing output from the bit synchronization circuit 16, and sets the pulse as “1” if the count value C1 is larger than the predetermined value SH and “0” if it is smaller. By determining the presence or absence, data can be demodulated (FIG. 2D). When the predetermined value SH is a power of 2, data can be determined by referring to a specific bit of the counter output. For example, when SH = 8, data can be determined by referring to the fourth bit of the counter.

  Thereby, it is possible to demodulate the signal including the pulse by counting the wave number included in the pulse. This makes it possible to digitize the demodulation process, generate the same pulse as the pulse transmitted from the transmitter on the receiver side, or perform multiplication while accurately matching the timing of these pulses. Therefore, it is possible to accurately receive a signal including a pulse while suppressing an increase in circuit scale.

  The determination circuit 17 sets a threshold value SH for determining “1” when the count value C1 is greater than or equal to “0” when the count value C1 is less than or equal to “0”. As a method of setting the threshold value SH of the count value C1, the wave number included in the transmitted pulse can be half. For example, if 16 waves are included in one pulse, the threshold value SH of the count value C1 can be set to 8.

  Alternatively, the threshold value SH of the count value C1 may be set in consideration of the SNR (signal noise ratio) of the received signal. In this method, when the received signal is determined to be “0” (no pulse is sent), the count value C1 is determined to be counted up due to the noise N1, and the threshold is set slightly higher based on that value. be able to. Thereby, the erroneous detection of the pulse by noise N1 can be suppressed. In addition to the count value when the received signal is determined to be “0”, the receiving circuit is operated between pulses (in this case, there is definitely no pulse), and the threshold value SH is calculated from the count value C1 at that time. May be set.

  In the above-described embodiment, since the presence or absence of a pulse is determined based on the count value C1 counted by the counter 15, the low noise amplifier is used when the threshold value SH in the determination circuit 17 is exceeded (that is, when data is determined). 12 or the counter 15 may be stopped immediately. If the count value C1 is not counted up to the center of the window signal M1, it may be determined that there is no pulse during that period, and the operations of the low noise amplifier 12 and the counter 15 may be stopped immediately. As a result, it is not necessary to perform an extra demodulation operation, and low power consumption is possible.

3 is a diagram showing a synchronization acquisition method when the window signal is delayed with respect to the received signal, FIG. 4 is a diagram showing a synchronization acquisition method when the window signal is advanced with respect to the received signal, and FIG. This is a synchronization acquisition method when the signal and the window signal are synchronized.
In FIG. 3, when the signal S2 from the comparator 14 is applied to the first half of the window signal M2, the count value C2 of the counter 15 is counted up, and the count value C2 at the end of the Tw period becomes positive. At this time, it can be determined that the window signal M2 is delayed with respect to the pulse, and the timing of the window signal M2 is advanced.
On the other hand, in FIG. 4, when the signal S2 from the comparator 14 is applied to the second half of the window signal M2, the count value C2 of the counter 15 is counted down, and the count value C2 at the time when the Tw period ends becomes negative. At this time, it can be determined that the window signal M2 is advanced with respect to the pulse, and the timing of the window signal M2 is delayed. By repeating this operation, as shown in FIG. 5, the timing of the window signal M2 is adjusted so that the count value C2 of the intermediate point of the window signal M2 is positive and the count value C2 becomes 0 at the final point of the window signal M2. Can be controlled. For synchronization acquisition from a state in which synchronization is not achieved, the Tw period may be longer than the data transmission period to increase the probability that a pulse enters the Tw period.

When the timing of the received pulse and the window signal M2 coincides, synchronous tracking can be performed. In this synchronization tracking, the timing of the window signal M2 can be finely adjusted by counting up and counting down the count value C2 of the counter 15 for each fixed number of window signals M2 in the same manner as the synchronization acquisition operation (note that , Synchronous tracking does not have to be performed every time).
In the above-described embodiment, the method of synchronizing the circuit by operating the circuit only in the section in which the window signal M1 is “H” has been described. However, the signal being synchronized is continuously received and the count value C1 is the threshold value SH. Control may be performed so that the timing exceeding the center of the window signal M1. As a result, the timing of the received pulse and the window signal M1 can be matched in a short time. Further, in synchronization tracking, normal intermittent reception may be performed and fine adjustment may be performed so that the timing at which the count value C1 exceeds the threshold SH is at the center of the window signal M1.

Here, the first synchronization acquisition method described above has high synchronization acquisition accuracy, and the second synchronization acquisition method has a higher synchronization acquisition speed. Therefore, the synchronization acquisition can be performed quickly and with high accuracy by roughly synchronizing with the second synchronization acquisition method and then matching the timing of the window signal M1 with high accuracy by the first synchronization acquisition method.
In relation to the determination circuit 17, the SNR may be determined based on the count value when there is no pulse and the count value when there is a pulse. By obtaining the SNR on the receiving side, the noise level is determined, and the determination result is fed back to the transmitting side, whereby the transmission power can be adjusted and transmission can be performed with the minimum power that data can be determined.

FIG. 6 is a block diagram showing a schematic configuration of a receiver according to the second embodiment of the present invention.
6, a prescaler 18 is inserted in front of the counter 15 in addition to the configuration of FIG. 1. The output of the comparator 14 is input to the prescaler 18. The prescaler 18 divides the output of the comparator 14 and then outputs it to the counter 15. The counter 15 counts the signal divided by the prescaler 18 and outputs the count value to the bit synchronization circuit 16 and the determination circuit 17. Thereby, the pulse can be detected even in a high frequency region where the counter 15 does not operate.

FIG. 7 is a diagram illustrating a reception method according to the third embodiment of the present invention.
In FIG. 7, FSK modulation can be used as a modulation method for pulse radio communication. In the case of this FSK modulation, a plurality of FSK signals S3 and S4 having different wave numbers in a certain section can be selected and transmitted according to data “1” or “0”. Then, the reception side counts the wave number of the reception signal at the timing of the window signals M3 and M4, and determines the count values C3 and C4 at that time to determine which FSK signals S3 and S4 are transmitted. Data 1 "or" 0 "can be determined, and by using three or more FSK signals having different wave numbers, multi-level modulation can be performed for only the types of pulses, and efficient communication is possible.

1 is a block diagram showing a schematic configuration of a receiver according to a first embodiment of the present invention. The figure which shows the data demodulation method of the receiver of FIG. The figure which shows the synchronous acquisition method of the receiver of FIG. The figure which shows the synchronous acquisition method of the receiver of FIG. The figure which shows the synchronous acquisition method of the receiver of FIG. The block diagram which shows schematic structure of the receiver which concerns on 2nd Embodiment of this invention. The figure which shows the receiving method which concerns on 3rd Embodiment of this invention.

Explanation of symbols

  11 antenna, 12 low noise amplifier, 13 threshold setting circuit, 14 comparator, 15 counter, 16 bit synchronization circuit, 17 determination circuit, 18 prescaler, 19 band pass filter

Claims (8)

Pulse signal receiving means for receiving a signal including a pulse;
Counting means for counting the number of waves contained in the pulse;
A receiver for determining the presence or absence of a pulse based on the count value of the wave number. Pulse signal receiving means for receiving a signal including a pulse;
A prescaler that divides the received signal;
Counting means for counting the number of waves included in the pulses divided by the prescaler;
A receiver for determining the presence or absence of a pulse based on the count value of the wave number.   The receiver according to claim 1, wherein the determination unit determines the presence or absence of a pulse based on a reference value of the count value or a specific bit of the prescaler.   The receiver according to any one of claims 1 to 3, wherein the determination unit stops a demodulation operation of a signal received this time when the count value exceeds a predetermined value.   The receiver according to any one of claims 1 to 4, wherein the determination unit estimates a noise level based on a count value counted in a predetermined section.   6. The receiver according to claim 1, wherein the signal including the pulse is an OOK signal or an FSK signal.   7. The synchronization acquisition unit according to claim 1, further comprising synchronization acquisition means for acquiring synchronization of a received signal by setting the window timing so that the count values coincide in the first half period and the second half period. The receiver according to claim 1.   The receiver according to any one of claims 1 to 6, further comprising synchronization acquisition means for acquiring synchronization of a received signal so that a timing at which the count value exceeds a threshold is in the center of the window.

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