JP4994865B2 - Wireless receiver - Google Patents

Description

  The present invention relates to a radio reception apparatus that receives a radio signal having a pulsed signal at a predetermined cycle at a timing synchronized with the cycle.

  In recent years, as one of high-speed wireless transmission methods, attention has been paid to an ultra wide band (UWB) communication method that performs ultra-wideband communication using a pulse signal sequence composed of pulse signals synchronized with a predetermined cycle timing. Yes. As one aspect of UWB communication, there is known one in which communication is performed using a pulse signal sequence including an extremely short pulse signal such as a pulse width of 1 nsec (nanoseconds) or less without using a carrier wave (for example, Patent Documents). 1).

There is also known a radio apparatus that detects the reception intensity of a radio signal and discriminates the radio signal from noise depending on whether or not the reception intensity exceeds a predetermined determination level so as not to receive noise (for example, , See Patent Document 2).
Japanese National Patent Publication No. 10-508725 Japanese Patent Laid-Open No. 10-32504

  By the way, as in the wireless device described in Patent Document 2 described above, the reception strength of a wireless signal is detected, the wireless signal and noise are determined depending on whether the reception strength exceeds a predetermined determination level, and the noise is received. It is conceivable to reduce the influence of noise by applying a technique for avoiding this to the above-described UWB receiver. However, UWB communication does not use a carrier wave, and uses an extremely short pulse signal such as a pulse width of 1 nsec or less. Therefore, the transmission power spectral density is very low compared to other wireless communication systems, and the noise signal level is low. There is a disadvantage that the difference between the signal level of the radio signal pulse and the radio signal pulse is small, and it is difficult to set the determination level capable of discriminating between the radio signal and the noise.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a radio receiving apparatus that can improve the discrimination accuracy between radio signals and noise and improve the reliability of communication. To do.

  A radio receiving apparatus according to the present invention includes a receiving unit that receives a radio signal containing predetermined data and has pulses arranged at a predetermined period, and an amplifying unit that amplifies the signal received by the receiving unit. An integration unit that integrates the signal amplified by the amplification unit for each window period that is a part of the period, and the number of times that the integration value obtained by the integration unit is out of a predetermined determination range. In the state where the wireless signal is not received by the counting unit for counting and the receiving unit, the counting unit counts the number of times within a preset determination period, and the count value of the counting unit is preset. When the upper limit of the set number range is exceeded, the upper limit value of the determination range is increased and the lower limit value of the determination range is decreased, and the count value of the counting unit falls below the lower limit of the set number range A determination range setting for setting the determination range so that the count value of the counting unit falls within the set number of times by decreasing the upper limit value of the determination range and increasing the lower limit value of the determination range. A synchronization unit that synchronizes the timing of the pulse and the timing of the window period in the signal received by the reception unit, and a synchronization window period that is a window period synchronized with the timing of the pulse, by the integration unit When the obtained integral value exceeds the upper limit of the determination range, a determination unit that determines that the signal received by the reception unit is the radio signal, and a signal that is received by the reception unit by the determination unit is And a demodulator that starts demodulation of the radio signal received by the receiver when the radio signal is determined to be the radio signal.

  According to this configuration, the signal received by the receiving unit is amplified by the amplifying unit, and the signal amplified by the amplifying unit is set for each window period, which is a part of the period in which pulses are arranged by the integrating unit. Integrated. In addition, the number of times the integrated value obtained by the integrating unit deviates from the predetermined determination range is counted by the counting unit within a preset determination period in a state where no wireless signal is received by the receiving unit. . Here, generally, the signal received by the receiving unit may contain noise, and the larger the amplitude of the noise received by the receiving unit, the more times the integrated value obtained by the integrating unit deviates from the predetermined determination range. Will increase. Therefore, when the count value of the counter exceeds the upper limit of the set number of times, it is considered that the noise amplitude is large and it is difficult to discriminate the radio signal. In such a case, the determination range setting unit sets the determination range so that the upper limit value of the determination range is increased and the lower limit value of the determination range is decreased, and the count value of the counting unit falls within the set number of times range. As a result, the upper limit value of the determination range is increased. As a result, the determination unit increases the upper limit of the integral value determined as noise, thereby improving the accuracy of determining noise and radio signals. In addition, since noise exists to some extent in most environments, if the count value of the counter is below the lower limit of the set number of times, the determination range is too wide to be counted by the counter. It is thought that there is. Therefore, when the count value of the counting unit falls below the lower limit of the set number range, the upper limit value of the determination range is decreased and the lower limit value of the determination range is increased, so that the count value of the counting unit is within the set number range. Thus, the determination range is narrowed. In this way, the determination range is set according to the noise level, and the noise and the radio signal are discriminated based on the upper limit value of the determination range, so that the discrimination accuracy between the noise and the radio signal is improved. In this way, when the determination unit determines that the signal received by the reception unit is a radio signal, the demodulation unit starts demodulation of the radio signal received by the reception unit. It is possible to improve discrimination accuracy between signals and noise and improve communication reliability.

  Further, the output level of the integration unit is adjusted so that the average value of the integration values obtained by the integration unit is within the determination range within a predetermined period when the wireless signal is not received by the reception unit. It is preferable to further include an integral offset initial adjustment unit for performing the above.

  According to this configuration, the so-called integration unit offset, which is the output level of the integration unit when no radio signal is received, is adjusted by the integration offset initial adjustment unit to be within the determination range. As a result of the offset, the output level of the integration unit becomes excessive, and the possibility that the circuit provided at the subsequent stage of the integration unit will not operate normally is reduced.

  Further, the difference between the maximum value and the minimum value of the integral value obtained by the integration unit within a predetermined period in a state where the wireless signal is not received by the reception unit is calculated as an upper limit and a lower limit of the determination range. It is preferable to further include an amplification factor initial adjustment unit that adjusts the amplification factor of the amplification unit so as to approach the difference.

  According to this configuration, the difference between the maximum value and the minimum value of the integration value obtained by the integration unit by the amplification factor initial adjustment unit within a predetermined period when the wireless signal is not received by the reception unit, Since the amplification factor of the amplification unit is adjusted so as to approach the difference between the upper limit and the lower limit of the determination range, the amplification value of the amplification unit is excessive, so that the integrated value is out of the determination range or the amplification factor of the amplification unit. The possibility that the integrated value does not deviate from the determination range due to being too small is reduced.

  Further, the integral value obtained by the integration unit in a plurality of the synchronization window periods is an upper limit number of times exceeding an upper limit of the determination range within a preset period and a lower limit number of times less than the lower limit of the determination range. The difference between the upper / lower limit counting unit to be counted and the upper limit count and the lower limit count counted by the upper / lower limit count unit exceeds a preset operating determination threshold, and the upper limit count is the lower limit count. It is preferable to further include an integration offset adjusting unit that lowers the output level of the integrating unit when larger, and increases the output level of the integrating unit when the lower limit number is larger than the upper limit number.

  According to this configuration, the upper / lower limit counting unit sets the upper limit number of times that the integration value obtained by the integration unit in a plurality of synchronization window periods exceeds the upper limit of the determination range within the preset period and the lower limit of the determination range. The lower limit number below is counted. In this case, when the offset voltage of the integration unit increases, the upper limit number increases and the lower limit number decreases, and when the integration unit offset voltage decreases, the upper limit number decreases and the lower limit number increases. If the difference between the number of times and the lower limit number exceeds a preset threshold value during operation, it means that the offset voltage of the integration unit has fluctuated. Therefore, when the difference between the upper limit count and the lower limit count exceeds a preset threshold value during operation, if the upper limit count is greater than the lower limit count, the integration offset adjuster reduces the output level of the integration section. When the lower limit number is larger than the upper limit number, the output level of the integration unit is increased, so that the offset voltage of the integration unit can be adjusted even when a radio signal is received by the reception unit.

  In addition, the state where the counting unit counts the number of times within the determination period and the count value of the counting unit exceeds the upper limit value of the set number of times exceeds a noise determination time longer than the communication frame length of the wireless signal. It is preferable to further include an amplification factor adjustment unit that lowers the amplification factor of the amplification unit.

  According to this configuration, when the state in which the count value of the counting unit exceeds the upper limit value of the set number of times range continues for a noise determination time longer than the communication frame length of the radio signal, that is, noise is received by the receiving unit. In the case where the amplification factor of the amplification unit is considered to be excessive, the amplification factor of the amplification unit is reduced by the amplification factor adjustment unit. Can be detected, and the amplification factor of the amplifier can be adjusted.

  In addition, the amplification factor adjustment unit further, when the state in which the count value counted by the counting unit is below the lower limit value of the set number of times exceeds the noise determination time, It is preferable to increase the amplification factor.

  According to this configuration, when the state where the count value of the counting unit is below the lower limit value of the set number of times range continues for a noise determination time longer than the communication frame length of the radio signal, that is, noise is received by the receiving unit. And the amplification factor of the amplification unit is increased by the amplification factor adjustment unit when the amplification factor of the amplification unit is considered to be too low. Can be detected, and the amplification factor of the amplifier can be adjusted.

  In addition, the demodulating unit is configured such that an integrated value obtained by integrating the integrated value obtained by the integrating unit in the synchronous window period for a unit period indicating 1-bit data is a preset logic determination threshold value. By determining that the radio signal of the unit period indicates a first logical value when exceeding the logical determination threshold, and that the radio signal of the unit period indicates a second logical value when the logical determination threshold is not satisfied, The radio signal is demodulated, and a value obtained by multiplying the integrated value in a unit period determined to indicate the first logical value by the demodulator by a preset ratio is newly set as the logical determination threshold value. It is preferable to further include a logic determination threshold setting unit.

  According to this configuration, when the integration value obtained by integrating the integration value obtained by the integration unit during the synchronization window period by the demodulation unit during the unit period exceeds a preset logic determination threshold value. The wireless signal of the unit period indicates a first logical value, and if the wireless signal of the unit period does not satisfy the logical determination threshold, the wireless signal is determined to indicate a second logical value. Demodulated. Then, the value obtained by multiplying the integrated value in the unit period indicating the first logic value by the preset ratio is set as a new logic determination threshold by the logic determination threshold setting unit, so that the radio received by the receiver Since the logic determination threshold value for determining the logic value of the radio signal is set according to the signal strength, the demodulation accuracy of the radio signal is improved.

  In the radio receiving apparatus having such a configuration, the signal received by the receiving unit is amplified by the amplifying unit, and the signal amplified by the amplifying unit is a partial period in the period in which the pulse is arranged by the integrating unit. It is integrated every window period. In addition, the number of times the integrated value obtained by the integrating unit deviates from the predetermined determination range is counted by the counting unit within a preset determination period in a state where no wireless signal is received by the receiving unit. . Here, the larger the amplitude of the noise received by the receiving unit, the greater the number of times that the integrated value obtained by the integrating unit deviates from the predetermined determination range. Therefore, when the count value of the counter exceeds the upper limit of the set number of times, it is considered that the noise amplitude is large and it is difficult to discriminate the radio signal. In such a case, the determination range setting unit sets the determination range so that the upper limit value of the determination range is increased and the lower limit value of the determination range is decreased, and the count value of the counting unit falls within the set number of times range. As a result, the upper limit value of the determination range is increased. As a result, the determination unit increases the upper limit of the integral value determined as noise, thereby improving the accuracy of determining noise and radio signals. In addition, since noise exists to some extent in most environments, if the count value of the counter is below the lower limit of the set number of times, the determination range is too wide to be counted by the counter. It is thought that there is. Therefore, when the count value of the counting unit falls below the lower limit of the set number range, the upper limit value of the determination range is decreased and the lower limit value of the determination range is increased, so that the count value of the counting unit is within the set number range. Thus, the determination range is narrowed. In this way, the determination range is set according to the noise level, and the noise and the radio signal are discriminated based on the upper limit value of the determination range, so that the discrimination accuracy between the noise and the radio signal is improved. In this way, when the determination unit determines that the signal received by the reception unit is a radio signal, the demodulation unit starts demodulation of the radio signal received by the reception unit. It is possible to improve discrimination accuracy between signals and noise and improve communication reliability.

  Embodiments according to the present invention will be described below with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted. FIG. 1 is a block diagram illustrating an example of a configuration of a wireless reception device 1 according to an embodiment of the present invention. FIG. 2 is an explanatory diagram illustrating an example of a radio signal received by the radio reception device 1 illustrated in FIG. 1. FIG. 2A is a diagram showing an example of the communication frame F1, and FIG. 2B is an enlarged view of a portion indicated by the symbol A in FIG. As shown in FIG. 2A, the communication frame F1 includes a pulse synchronization continuous pulse train F11 (synchronization pulse train), a bit synchronization pulse array F12, a unique word F13, and a data portion F14. . Further, as shown in FIG. 2B, the short pulse signal P is arranged at a cycle t1, for example, 50 nsec, and the pulse width of the short pulse signal P is set to 1 nsec, for example.

  The continuous pulse train F11 is a pulse train for synchronizing the communication frame F1 and the reception timing of the short pulse signal P in the wireless reception device 1 so that, for example, the short pulse signal P is continuous at a cycle of 50 nsec for a period of about 100 μsec to 900 μsec. Has been. The pulse sequence F12 for bit synchronization is a pulse train for bit synchronization, and is a pulse in which a short pulse signal P without a short pulse signal P and a short pulse signal P are continuous at a cycle of 50 nsec every preset unit period t0. The sections B1 are alternately arranged. The unique word F13 is a pulse train for distinguishing the bit synchronization pulse array F12 from the data portion F14.

  The data part F14 is configured to represent a logical value of 1-bit data by a pulse no-interval B0 and a pulse present interval B1, for example, the pulse no-interval B0 is bit “0” and the pulse present interval B1 is bit. It represents “1”.

  1 includes an antenna 2 (receiving unit), an amplifier 3 (amplifying unit), a filter 4, a detector 5, integration blocks 6-1 to 6-n, an adder 7, a signal processing unit 8, A gate signal generation unit 9 and a phase control unit 10 are provided.

  The antenna 2 is a receiving antenna that receives an ultra-wideband radio signal. The amplifier 3 is an amplifier circuit that amplifies the signal received by the antenna 2. The filter 4 is a band filter that filters the output signal of the amplifier 3. The detector 5 is a detector that envelope-detects the output signal of the filter 4 and outputs the detected signal to the integration blocks 6-1 to 6-n as the detection signal K1. The antenna 2, the amplifier 3, the filter 4, and the detector 5 detect, for example, a signal in the band of 3.2 GHz received by the antenna 2 by envelope detection, and frequency-converts it to several hundred MHz, for example, about 500 MHz, and performs pulse demodulation. It has come to be.

  The integration blocks 6-1 to 6-n integrate the detection signal K1 output from the detector 5 over the window periods indicated by the gate signals G1 to Gn output from the phase control unit 10, and integrate signals S1 to Sn. Integration circuits 61-1 to 61-n (integration units) output as integral signals, and the integration signals S1 to Sn output from the integration circuits 61-1 to 61-n are converted into digital values, which are used as integration value signals AD1 to ADn. AD converters 62-1 to 62-n for outputting are provided. The AD converters 62-1 to 62-n are, for example, 8-bit, 255-stage AD converters. Hereinafter, when referring generically, it shows with the reference symbol which abbreviate | omitted the suffix, and when referring to an individual structure, it shows with the reference symbol which attached the suffix.

  In addition, the integration block 6 is not restricted to the example provided with two or more, One may be sufficient. In this case, the adder 7 may not be provided.

  FIG. 3 is a circuit diagram showing an example of the configuration of the integrating circuit 61 shown in FIG. The integration circuit 61 shown in FIG. 3 receives an integrator 611 that integrates the detection signal K1 only while the gate signals G1 to Gn are at a high level, for example, and an integration offset adjustment signal Q1 that is output as a digital signal from the signal processing unit 8. A DA converter 612 that converts to an analog voltage, and an adder 613 that adds the output voltage of the integrator 611 and the output voltage of the DA converter 612 and outputs the result to the AD converter 62 as integration signals S1 to Sn. ing.

  The integral offset adjustment signal Q1 can take positive and negative values, and the output voltage of the DA converter 612 can also take positive and negative voltage values. Accordingly, the signal processing unit 8 adjusts the value of the integral offset adjustment signal Q1, thereby increasing or decreasing the voltage level of the integration signals S1 to Sn output from the integration circuit 61 as a whole. The output voltage level of the integrating circuit 61 when no signal is input to the integrating circuit 61, so-called offset voltage, can be adjusted as appropriate.

  The adder 7 adds the integration value signals AD1 to ADn output from the AD converters 62-1 to 62-n, that is, the integration values of the integration circuits 61-1 to 61-n to obtain an addition value AD0. 8 is an adder circuit that outputs the data to 8. The gate signal generation unit 9 is configured to include, for example, an oscillation circuit, and in order to cause the integration circuits 61-1 to 61-n to perform an integration operation at the same cycle as the cycle of the radio signal pulse in ultra-wideband communication. The circuit unit outputs a reference gate signal G indicating an integration period, that is, a window period, every t1.

  The phase control unit 10 converts the phase of the reference gate signal G based on the reference gate signal G output from the gate signal generation unit 9 and the control signal from the signal processing unit 8 to the integration circuits 61-1 to 61-n. Are respectively changed to indicate the timing of the integration operation, and are output to the integration circuits 61-1 to 61-n as the gate signals G1 to Gn, respectively. Thereby, the detection signal K1 is integrated by the integration blocks 6-1 to 6-n in the window periods having different timings.

  The signal processing unit 8 is a control circuit configured using, for example, a microcomputer, and is synchronized with the received pulse based on the integrated value signals AD1 to ADn output from the AD converters 62-1 to 62-n. This is a circuit unit that acquires and maintains timing, demodulates data from the received signal based on the output signal of the adder 7, and outputs the data as data Dout to the outside.

  FIG. 4 is a block diagram illustrating an example of the configuration of the signal processing unit 8. The signal processing unit 8 illustrated in FIG. 4 includes a determination range setting unit 81, a determination unit 82, a synchronization unit 83, a signal acquisition unit 84, a baseband demodulation unit 85 (demodulation unit), an integral offset initial adjustment unit 86, and an amplification factor initial stage. An adjustment unit 87 is provided.

  The synchronization unit 83 compares the integration value signals AD1 to ADn output from the integration blocks 6-1 to 6-n, for example, and supplies them to the integration blocks 6-1 to 6-n having the largest integration value. The timing of the gate signal is acquired as the synchronization timing, or the timing at which the largest integrated value is obtained is searched while shifting the timing obtained in this way to acquire the synchronization timing. Then, the synchronization unit 83 performs pulse synchronization by matching one of the gate signals G1 to Gn output from the phase control unit 10 with the synchronization timing. In this case, the synchronization window period is indicated by the gate signal coincident with the synchronization timing.

  Note that the number of integration blocks 6 may be one, and the synchronization timing may be acquired by searching for the timing at which the largest integration value is obtained while shifting the timing of the gate signal of the integration block.

  After the synchronization is established, the signal acquisition unit 84 shifts the synchronization timing, that is, the timing of the synchronization window period with respect to the synchronization shift caused by the frequency deviation of the internal clock signal between the wireless transmission device and the reception device, for example. This makes it possible to maintain synchronization and continue to capture the signal.

  The determination range setting unit 81 is in a state in which no radio signal is received by the antenna 2, for example, an ultra-wideband radio transmission device is not transmitting a radio signal and no radio signal is received by the antenna 2. In such a case, when the user gives an instruction to set a determination range by operating an operation switch (not shown) or the like, the integral value obtained by the integration block 6 is determined in advance according to the setting instruction. Within the period t2, the upper limit determination value REFU and the lower limit are set such that the number of deviations from the determination range indicated by the preset upper limit determination value REFU and the lower limit determination value REFD falls within the preset set number range. A determination value REFD is set.

  FIG. 5 is a block diagram illustrating an example of the configuration of the determination range setting unit 81. The determination range setting unit 81 illustrated in FIG. 5 includes an average processing unit 801, a comparison unit 802, a count unit 803 (counting unit, upper and lower limit counting unit), a temporary storage unit 804, a set number of times storage unit 805, a comparison unit 806, and a determination value. An adjustment unit 807, a determination value storage unit 808, a timer 809, an amplification factor adjustment unit 810, and an integral offset adjustment unit 811 are provided.

  The average processing unit 801 averages the integral value signal AD1 for a preset period, for example, the determination period t2, and outputs the average value AV1 to the comparison unit 802. In the determination value storage unit 808, an upper limit determination value REFU and a lower limit determination value REFD of an integral value indicating a predetermined determination range are stored in advance, and the upper limit determination value REFU and the lower limit determination value REFD are stored in the comparison unit 802. Output. For example, the upper limit determination value REFU is lower than the level of the integral value signal AD1 that is assumed to be obtained when the communication frame F1 is received, and the integral value signal AD1 that is assumed to be obtained when background noise is received. A value higher than the level is set as an initial value. In addition, for example, the lower limit determination value REFD is set as an initial value at the same level as the integrated value signal AD1 that is assumed to be obtained when general background noise is received.

  The upper limit determination value REFU is used as a determination reference value for determining a radio signal and noise in the determination unit 82. When the determination unit 82 determines that a radio signal has been received, the baseband demodulation unit 85 starts demodulating the received signal.

  The comparison unit 802 compares the integral value signal AD1, the upper limit determination value REFU, and the lower limit determination value REFD. When the integral value signal AD1 exceeds the upper limit determination value REFU, the integration value signal AD1 is lower than the lower limit determination value REFD. In any case, the signal indicating that the integrated value signal AD1 is out of the determination range is output to the count unit 803. Further, the comparison unit 802 sends a signal indicating the respective cases to the count unit 803 when the integral value signal AD1 exceeds the upper limit determination value REFU and when the integral value signal AD1 falls below the lower limit determination value REFD. Output.

  Note that the average processing unit 801 is not provided, and the comparison unit 802 may use the average value AV1 instead of the integral value signal AD1. Further, the average processing unit 801 and the comparison unit 802 may use the added value AD0 instead of the integrated value signal AD1.

  The counting unit 803 counts the number of times that a signal indicating that the integrated value signal AD1 is out of the determination range is output from the comparison unit 802 within the determination period t2 timed by the timer 809, and the count value CT1 is calculated as, for example, The data is stored in a temporary storage unit 804 configured by a register circuit. In addition, the count unit 803 determines the upper limit number CTU of the integral value signal AD1 exceeding the upper limit determination value REFU and the integral value in accordance with the signal output from the comparison unit 802 within the determination period t2 timed by the timer 809. The lower limit count CTD at which the signal AD1 falls below the lower limit determination value REFD is counted and stored in the temporary storage unit 804.

  The set number storage unit 805 stores in advance an upper limit number set value CSU and a lower limit number set value CSD representing a predetermined set number range. If the signal obtained by the antenna 2 is the ultra-wideband communication frame F1 shown in FIG. 2, since the short pulse signal P is arranged at a certain frequency or more, the upper limit number setting value CSU is set to the communication frame F1. Is less than the number of times that the integral value signal AD1 exceeds the upper limit determination value REFU in the determination period t2, and more than the number of times that the integration value signal AD1 exceeds the upper limit determination value REFU in the determination period t2 in the background noise. Many values are set.

  In addition, as the lower limit number set value CSD, the number of times that is assumed that the integrated value signal AD1 exceeds the lower limit determination value REFD within the determination period t2 due to background noise is set. The comparison unit 806 compares the count value CT1 stored in the temporary storage unit 804 with the upper limit number set value CSU and the lower limit number set value CSD stored in the set number storage unit 805, and outputs a signal indicating the comparison result. The determination value adjustment unit 807, the amplification factor adjustment unit 810, and the integral offset adjustment unit 811 are output.

  When the determination value adjustment unit 807 receives a setting instruction that is not received by the antenna 2, for example, when the user operates an operation switch (not illustrated) as described above, the determination value adjustment unit 807 performs comparison of the comparison unit 806. Based on the signal indicating the result, the upper limit determination value REFU and the lower limit determination value REFD stored in the determination value storage unit 808 are adjusted. Specifically, for example, when the comparison result of the comparison unit 806 indicates that the count value CT1> the upper limit number set value CSU, the determination value adjustment unit 807 stores the upper limit determination value stored in the determination value storage unit 808. By increasing REFU and decreasing the lower limit determination value REFD, the width of the determination range is expanded and the count value CT1 is decreased. On the other hand, for example, when the comparison result of the comparison unit 806 indicates that the count value CT1 <the lower limit number set value CSD, the determination value adjustment unit 807 decreases the upper limit determination value REFU stored in the determination value storage unit 808. By increasing the lower limit number set value CSD, the width of the determination range is narrowed to increase the count value CT1.

  In this way, the determination value adjustment unit 807 is based on the level of the integral value signal AD1 obtained in the state where the radio signal is not received by the antenna 2 and the signal obtained by the antenna 2 is background noise. By setting the upper limit determination value REFU and the lower limit determination value REFD so that the upper limit number setting value CSU ≧ count value CT1 ≧ lower limit number setting value CSD, according to the background noise level in the installation environment of the wireless reception device 1 The upper limit determination value REFU and the lower limit determination value REFD are adjusted, and the determination unit 82 appropriately adjusts the set value of the upper limit determination value REFU used as a determination reference value for determining a radio signal and noise. Therefore, the discrimination accuracy between the radio signal and the noise is improved.

  The amplification factor adjustment unit 810 and the integral offset adjustment unit 811 will be described later.

  Returning to FIG. 4, when the addition value AD0 output from the adder 7 exceeds the upper limit determination value REFU, the determination unit 82 determines that the signal obtained by the antenna 2 is not a noise but a radio signal. Then, a determination notification signal Q3 indicating that a radio signal has been received is output to the baseband demodulation unit 85.

  The baseband demodulation unit 85 includes a logic determination threshold value setting unit 851 and a logic determination threshold value storage unit 852. In addition, when the determination notification signal Q3 indicating that the wireless signal has been received is output from the determination unit 82, the baseband demodulation unit 85 starts the demodulation operation.

  FIG. 6 is an explanatory diagram for explaining the operation of the baseband demodulator 85. As shown in FIG. 6, when demodulating the data part F14 of the communication frame F1 received by the antenna 2, for example, the baseband demodulator 85 adds the value output from the adder 7 during the unit period t0, for example. When AD0 is integrated and the obtained integrated value is equal to or greater than the logic determination threshold Th stored in advance in the logic determination threshold storage unit 852, it is determined as the pulsed section B1 in which the short pulse signal P is arranged, and the obtained integration If the value does not satisfy the logic determination threshold Th stored in advance in the logic determination threshold storage unit 852, it is determined that the pulseless section B0 in which the short pulse signal P is not disposed, and the pulsed section B1 is further set to the logic value “1”. By determining the pulse non-interval B0 as a logical value “0”, the signal obtained by the antenna 2 is demodulated to generate data Dout.

  Note that the baseband demodulator 85 has a logical value “1” if, for example, 1 bit is formed by combining the pulsed section B1 after the pulseless section B0, and the pulseless section B0 after the pulsed section B1. May be configured to generate data Dout as a logical value “0”.

  Further, the logic determination threshold value setting unit 851 integrates the addition value AD0 output from the adder 7 during the unit period t0, and a value obtained by multiplying the obtained integration value X by a predetermined ratio, for example, 0.5. (50% of the integrated value X) is set as a new logic determination threshold Th.

  As a result, the logic determination threshold Th is adjusted according to the signal level received by the antenna 2, that is, according to the strength of the radio signal, so that even if noise such as an interference wave exists, the radio By setting the logical determination threshold Th according to the signal strength, the possibility that the logical value of the wireless signal is erroneously determined is reduced, and the reliability of wireless communication is improved.

  When the integration offset initial adjustment unit 86 receives a setting instruction given by a state where no radio signal is received by the antenna 2, for example, a user operates an operation switch (not shown) as described above, the average processing unit 801. The integrated offset adjustment signal Q1 is output to adjust the output level of the integrating circuit 61 so that the average value AV1 obtained in the above equation satisfies the upper limit determination value REFU ≧ average value AV1 ≧ lower limit determination value REFD.

  When the amplification factor initial adjustment unit 87 receives a setting instruction that is not received by the antenna 2, for example, a user operates an operation switch (not shown) as described above, the amplification factor initial adjustment unit 87 starts from the integration block 6. The difference between the maximum value and the minimum value of the output integral value signal, for example, the integral value signal AD1, within a preset period is determined by using the upper limit determination value REFU and the lower limit determination value REFD stored in the determination value storage unit 808. The gain adjustment signal Q2 is output so that the gain of the amplifier 3 is adjusted so as to approach the difference between the two.

  Returning to FIG. 5, when the difference between the upper limit number CTU and the lower limit number CTD stored in the temporary storage unit 804 exceeds the preset in-operation determination threshold, the integral offset adjustment unit 811 determines that the upper limit number CTU is If the lower limit number CTD is larger than the lower limit number CTD, the output level of the integration circuit 61 is lowered by the integral offset adjustment signal Q1, and if the lower limit number CTD is larger than the upper limit number CTU, the output level of the integration circuit 61 is increased by the integral offset adjustment signal Q1. Thus, the difference between the upper limit number CTU and the lower limit number CTD is reduced.

  When the count value CT1 stored in the temporary storage unit 804 exceeds the upper limit number of times setting value CSU, for example, when the gain adjustment unit 810 continues beyond a noise determination time longer than the communication frame length of the communication frame F1, If the amplification factor of the amplifier 3 is decreased by the amplification factor adjustment signal Q2, and the state where the count value CT1 stored in the temporary storage unit 804 is lower than the lower limit number set value CSD exceeds the noise determination time, amplification is performed. The amplification factor of the integration circuit 61 is increased by the rate adjustment signal Q2.

  Next, the operation of the wireless reception device 1 configured as described above will be described. First, for example, in a state in which an ultra-wideband wireless transmission device is not transmitting a wireless signal and a wireless signal is not received by the antenna 2, background noise is received by the antenna 2, and the noise signal is amplified by the amplifier 3. , Filtered by the filter 4, detected by the detector 5 to be a detection signal K 1, and integrated by the integration blocks 6-1 to 6 -n.

  On the other hand, a reference gate signal G indicating a window period of, for example, 10 nsec is output from the gate signal generation unit 9 to the phase control unit 10 every period t1, for example. Then, the phase control unit 10 shifts the timing of the reference gate signal G to output the gate signals G1 to Gn having different timings to the integrating circuits 61-1 to 61-n.

  Then, the detection signals K1 are integrated by the integration blocks 6-1 to 6-n in the window periods indicated by the gate signals G1 to Gn, and the integration signals S1 to Sn are digitally converted by the AD converters 62-1 to 62-n. After being converted, the integrated value signals AD1 to ADn are output to the adder 7 and the signal processing unit 8.

  Then, the average processing unit 801 averages the integral value signal AD1 for a preset period, for example, the determination period t2, and outputs the average value AV1 to the determination value adjustment unit 807.

  Next, the determination range setting unit 81 sets the upper limit determination value REFU and the lower limit determination value REFD. FIG. 7 is an explanatory diagram for explaining an example of the operation of the determination range setting unit 81. First, the comparison unit 802 compares the integral value signal AD1 with the upper limit determination value REFU and the lower limit determination value REFD. Then, during the determination period t2 shown in FIG. 7, as indicated by the symbol U, when the integral value signal AD1> the upper limit determination value REFU, a signal indicating that the integral value signal AD1> the upper limit determination value REFU is counted. When the integrated value signal AD1 <lower limit determination value REFD, as indicated by reference numeral D, a signal indicating that the integrated value signal AD1 <lower limit determination value REFD is output to the counting unit 803.

  Then, by the counting unit 803, during the determination period t2, the upper limit number CTU in which the integral value signal AD1> the upper limit determination value REFU, the lower limit number CTD in which the integral value signal AD1 <the lower limit determination value REFD is satisfied, and the upper limit number The count value CT1, which is the sum of the CTU and the lower limit number of times CTD, is counted and stored in the temporary storage unit 804.

  Next, the comparison unit 806 compares the count value CT1 stored in the temporary storage unit 804 with the upper limit number set value CSU and the lower limit number set value CSD stored in the set number storage unit 805, and compares them. A signal indicating the result is output to determination value adjustment section 807, amplification factor adjustment section 810, and integral offset adjustment section 811.

  Next, for example, when the user gives a setting instruction by operating an operation switch (not shown) as described above, the determination value adjustment unit 807 stores the determination value based on the signal indicating the comparison result of the comparison unit 806. The values of the upper limit determination value REFU and the lower limit determination value REFD stored in the unit 808 are adjusted. Specifically, for example, when the comparison result of the comparison unit 806 indicates that the count value CT1> the upper limit number setting value CSU, the upper limit determination value stored in the determination value storage unit 808 by the determination value adjustment unit 807 REFU is increased, lower limit determination value REFD is decreased, and the width of the determination range is widened. In this case, the upper limit determination value REFU and the lower limit determination value REFD are set so as to center on the average value AV1 obtained by the average processing unit 801.

  Then, in the comparison unit 802, the frequency with which the integral value signal AD1> the upper limit determination value REFU and the frequency with which the integration value signal AD1 <the lower limit determination value REFD are decreased, and the count value CT1 in the count unit 803 decreases.

  Thereby, when the wireless receiver 1 is used in a poor noise environment, the frequency at which the amplitude of the integrated value signal AD1 increases due to noise and the integrated value signal AD1> the upper limit determination value REFU, and the integrated value signal AD1 < When the frequency of the lower limit determination value REFD increases, the upper limit determination value REFU is increased and the lower limit determination value REFD is decreased, and the value of the upper limit determination value REFU is obtained when the communication frame F1 is received. The upper limit determination value REFU is adjusted to a level at which noise and a radio signal can be distinguished by being brought close to the level of the integrated value signal AD1 assumed to be generated.

  On the other hand, when the comparison result of the comparison unit 806 indicates that the count value CT1 <the lower limit number set value CSD, the determination value adjustment unit 807 decreases the upper limit determination value REFU stored in the determination value storage unit 808. At the same time, the lower limit number set value CSD is increased, and the width of the determination range is narrowed. In this case, the upper limit determination value REFU and the lower limit determination value REFD are set so as to center on the average value AV1 obtained by the average processing unit 801.

  Then, in comparison unit 802, the frequency at which integral value signal AD1> upper limit determination value REFU and the frequency at which integration value signal AD1 <lower limit determination value REFD are increased, and count value CT1 in count unit 803 increases.

  Since background noise is present to some extent in most environments, if the comparison result of the comparison unit 806 satisfies the count value CT1 <the lower limit number set value CSD, the determination range is too wide and the communication signal is calculated. There is a possibility that noise and a communication signal cannot be discriminated because they are not counted as the numerical value CT1. Therefore, when the comparison result of the comparison unit 806 indicates that the count value CT1 <the lower limit number set value CSD, the determination range is narrowed so that the noise and the communication signal can be distinguished.

  In this way, no radio signal is received by the antenna 2 by the judgment value adjusting unit 807, and therefore the signal obtained by the antenna 2 is based on the level of the integral value signal AD1 obtained in the state of background noise. By setting the upper limit determination value REFU and the lower limit determination value REFD so that the upper limit number set value CSU ≧ count value CT1 ≧ lower limit number set value CSD, it corresponds to the level of background noise in the installation environment of the wireless receiver 1. Thus, the upper limit determination value REFU and the lower limit determination value REFD are adjusted, and the determination unit 82 appropriately adjusts the set value of the upper limit determination value REFU used as a determination reference value for determining a radio signal and noise. As a result, the discrimination accuracy between the radio signal and the noise can be improved.

  Further, when the average value AV1 obtained by the average processing unit 801 is larger than the upper limit determination value REFU by the integral offset initial adjustment unit 86, an integration offset adjustment signal Q1 is output so as to reduce the amplification factor of the amplifier 3, When the average value AV1 is smaller than the lower limit determination value REFD, the integral offset adjustment signal Q1 is output so as to increase the amplification factor of the amplifier 3, so that the upper limit determination value REFU ≧ the average value AV1 ≧ the lower limit determination value REFD. The output voltage level of the integrating circuit 61 when no radio signal is received, so-called offset voltage level, is adjusted.

  As a result, the offset voltage level of the integration circuit 61 is adjusted. For example, since the offset voltage level of the integration circuit 61 is excessive, the integration signal S1 of the integration circuit 61 exceeds the convertible voltage range of the AD converter 62. Therefore, it is possible to reduce the possibility that the wireless signal reception operation cannot be normally performed.

  Further, the amplification factor initial adjustment unit 87 amplifies the amplifier 3 based on the maximum value and the minimum value of the integral value signal AD1 obtained by the integral block 6-1 within a predetermined period, for example, during the determination period t2. The rate is adjusted. Specifically, for example, the difference between the maximum value and the minimum value of the integration value signal AD1 obtained by the integration block 6-1 during the determination period t2, for example, by the amplification factor initial adjustment unit 87 is set as the upper limit determination value REFU. The amplification factor adjustment signal Q2 is output and the amplification factor of the amplifier 3 is adjusted so as to be close to, for example, substantially the same as the difference from the lower limit determination value REFD.

  As a result, for example, when the wireless receiver 1 is manufactured, the amplification signal setting of the amplifier 3 is excessive, and thus the voltage level of the detection signal K1 becomes excessive and exceeds the voltage range that can be integrated by the integration circuit 61. The possibility that the integration signal S1 of the integration circuit 61 exceeds the convertible voltage range of the AD converter 62 and the wireless signal reception operation cannot be normally performed can be reduced.

  The determination range setting unit 81 sets the upper limit determination value REFU and the lower limit determination value REFD, then the integration offset initial adjustment unit 86 adjusts the offset voltage of the integration circuit 61, and then the amplification factor initial adjustment unit 87 adjusts the amplifier 3. Although the example in which the amplification factor is adjusted is shown, the setting of the upper limit determination value REFU and the lower limit determination value REFD, the offset adjustment of the integration circuit 61, and the amplification factor adjustment of the amplifier 3 are not limited to the examples executed in this order. For example, the amplification factor adjustment of the amplifier 3, the offset adjustment of the integration circuit 61, and the setting of the upper limit determination value REFU and the lower limit determination value REFD may be performed in this order.

  Next, a radio signal, for example, a communication frame F1 is received by the antenna 2. The signal obtained by the antenna 2 is amplified by the amplifier 3, filtered by the filter 4, detected by the detector 5, and output to the integration blocks 6-1 to 6-n as the detection signal K 1. The detection signal K1 is integrated by the integration blocks 6-1 to 6-n in each window period indicated by the gate signals G1 to Gn output from the phase control unit 10, and the obtained integration value signals AD1 to ADn are obtained as follows. The data is output to the adder 7 and the signal processing unit 8. Further, the adder 7 adds the integration value signals AD1 to ADn and outputs the addition value AD0 to the signal processing unit 8.

  Next, synchronization processing is performed by the synchronization unit 83. FIG. 8 is an explanatory diagram for explaining the operation of the synchronization unit 83. FIG. 8A shows a state where synchronization is not achieved, and FIG. 8B shows a state where synchronization is achieved. FIG. 8 shows an example in which the gate signal G1 is synchronized to simplify the description. The gate signal G1 is at a high level and indicates a window period.

  First, as shown in FIG. 8A, in a state where synchronization is not established, the pulse position of the detection signal K1 is shifted from the timing when the gate signal G1 is at a high level. Then, the pulse of the detection signal K1 is not integrated by the integration block 6-1, and the integrated value signal AD1 does not increase. On the other hand, as shown in FIG. 8B, in the synchronized state, the pulse position of the detection signal K1 coincides with the high level timing of the gate signal G1, and the pulse of the detection signal K1 is integrated in the integration block 6- The integrated value signal AD1 increases as a result of being integrated by 1.

  Therefore, for example, the integration value signals AD1 to ADn output from the integration blocks 6-1 to 6-n are compared by the synchronization unit 83 and supplied to the integration blocks 6-1 to 6-n having the largest integration value. The timing of the gate signal is acquired as the synchronization timing, or the timing at which the largest integrated value is obtained is searched while shifting the timing obtained in this way, and the synchronization timing is acquired. Then, the synchronization unit 83 matches one of the gate signals G1 to Gn output from the phase control unit 10 with the synchronization timing, and for example, as shown in FIG.

  When the pulse synchronization is established, the signal acquisition unit 84 shifts the timing of the synchronization window period with respect to the synchronization shift caused by the frequency deviation of the internal clock signal between the wireless transmission device and the reception device, for example. Synchronization is maintained.

  Next, when the addition value AD0 output from the adder 7 exceeds the upper limit determination value REFU, the determination unit 82 determines that the signal obtained by the antenna 2 is not a noise but a radio signal, and the radio signal is A determination notification signal Q3 indicating that it has been received is output to the baseband demodulator 85, and the baseband demodulator 85 starts a radio signal demodulation operation.

  In this case, the determination unit 82 determines whether the signal obtained by the antenna 2 is noise or a radio signal. When it is determined that the signal is a radio signal, the baseband demodulation unit 85 performs a radio signal demodulation operation. Therefore, malfunction due to noise in the baseband demodulator 85 is reduced, and communication reliability is improved. Further, the determination unit 82 sets the upper limit determination value REFU and the lower limit determination value REFD used to determine noise and a radio signal to the background noise level in the installation environment of the wireless reception device 1 by the determination range setting unit 81. Accordingly, since the determination accuracy of the radio signal and the noise in the determination unit 82 is improved, the reliability of communication can be improved.

  Next, after the baseband demodulator 85 starts demodulating the radio signal, for example, when the ambient temperature in the installation environment of the radio receiver 1 fluctuates, the amplifier 3 and the integrator 611 have temperature characteristics, so that the amplifier 3 And the offset voltage of the integration circuit 61 change. Then, the amplification factor of the amplifier 3 set by the amplification factor initial adjustment unit 87 as described above and the offset voltage of the integration circuit 61 set by the integration offset initial adjustment unit 86 may change.

  However, after the transmission of the wireless signal by the wireless transmission device is started, it is unknown whether the signal obtained by the antenna 2 is a wireless signal or noise. The adjustment unit 87 cannot adjust the amplification factor of the amplifier 3 and the offset voltage of the integration circuit 61.

  Therefore, the integral offset adjustment unit 811 compares the difference between the upper limit number CTU and the lower limit number CTD stored in the temporary storage unit 804 with a preset in-operation determination threshold value. In this case, when the difference between the upper limit number CTU and the lower limit number CTD becomes larger than the determination threshold during operation, the value of the integral value signal AD1 is shifted up and down from the middle between the upper limit determination value REFU and the lower limit determination value REFD as a whole. It is considered that the offset voltage of the integrating circuit 61 has changed.

  Therefore, when the difference between the upper limit number CTU and the lower limit number CTD becomes larger than the determination threshold during operation, the integral offset adjustment unit 811 reduces the output level of the integration circuit 61 when the upper limit number CTU is larger than the lower limit number CTD. When the number of times CTD is larger than the upper limit number of times CTU, the output level of the integrating circuit 61 is increased, thereby reducing the difference between the upper limit number of times CTU and the lower limit number of times CTD. If the difference between the upper limit number CTU and the lower limit number CTD decreases, the output level of the integration circuit 61 is adjusted so that the value of the integral value signal AD1 approaches the intermediate position between the upper limit determination value REFU and the lower limit determination value REFD as a whole. Therefore, even after the transmission of the wireless signal by the wireless transmission device is started, if the offset voltage of the integration circuit 61 changes due to a change in ambient temperature or the like, the integration offset adjustment unit 811 performs integration. The offset voltage of the circuit 61 can be adjusted.

  In addition, since the communication frame length of the communication frame F1 used for wireless communication is determined in advance, the count value CT1 continuously exceeds the upper limit number set value CSU for a noise determination time longer than the communication frame length of the communication frame F1. If it continues to exceed, it is considered that noise together with the radio signal exceeds the upper limit determination value REFU and is counted by the counting unit 803, and the amplification factor of the amplifier 3 is considered to be too high. Therefore, when the state where the count value CT1 stored in the temporary storage unit 804 exceeds the upper limit number set value CSU exceeds a noise determination time longer than the communication frame length of the communication frame F1, for example, the amplification factor adjustment unit 810 The amplification factor of the amplifier 3 is reduced. Thereby, even when the amplification factor of the amplifier 3 increases due to a temperature change or the like during execution of wireless communication, the amplification factor of the amplifier 3 can be adjusted.

  Further, when the state where the count value CT1 is lower than the lower limit number set value CSD continues for example exceeding the noise determination time, it is considered that the amplification factor of the amplifier 3 is too low. Therefore, when the state where the count value CT1 is lower than the lower limit number set value CSD continues, for example, exceeding the noise determination time, the amplification factor of the amplifier 3 is lowered by the amplification factor adjustment unit 810. Thereby, even when the amplification factor of the amplifier 3 is reduced due to a temperature change or the like during the execution of wireless communication, the amplification factor of the amplifier 3 can be adjusted.

It is a block diagram which shows an example of a structure of the radio | wireless receiving apparatus which concerns on one Embodiment of this invention. It is explanatory drawing which shows an example of the radio signal received by the radio | wireless receiver shown in FIG. (A) is a figure which shows an example of a communication frame, (b) is the figure which expanded and showed the part of the code | symbol A in (a). FIG. 2 is a circuit diagram illustrating an example of a configuration of an integration circuit illustrated in FIG. 1. It is a block diagram which shows an example of a structure of the signal processing part shown in FIG. It is a block diagram which shows an example of a structure of the determination range setting part shown in FIG. It is explanatory drawing for demonstrating operation | movement of the baseband demodulation part shown in FIG. It is explanatory drawing for demonstrating an example of operation | movement of the determination range setting part shown in FIG. It is explanatory drawing for demonstrating operation | movement of the synchronizer shown in FIG. (A) shows a state where synchronization is not achieved, and (b) shows a state where synchronization is achieved.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wireless receiver 2 Antenna 3 Amplifier 4 Filter 5 Detector 6,6-1 to 6-n Integration block 7 Adder 8 Signal processing part 9 Gate signal generation part 10 Phase control part 61, 61-1 to 61-n Integration Circuit 62, 62-1 to 62-n AD converter 81 Determination range setting unit 82 Determination unit 84 Signal acquisition unit 85 Baseband demodulation unit 86 Integration offset initial adjustment unit 87 Amplification factor initial adjustment unit 611 Integrator 612 DA converter 613 Adder 801 Average processing unit 802 806 Comparison unit 803 Count unit 805 Setting number storage unit 807 Determination value adjustment unit 808 Determination value storage unit 809 Timer 810 Amplification rate adjustment unit 811 Integration offset adjustment unit 851 Logic determination threshold setting unit 852 Logic determination Threshold value storage unit AD0 addition value AD1 to ADn integrated value signal AV1 average value B0 pal No section B1 Pulsed section CSD Lower limit set value CSU Upper limit set value CT1 Count value CTD Lower limit count CTU Upper limit count Dout Data F1 Communication frame F14 Data part G1 to Gn Gate signal P Short pulse signal REFD Lower limit determination value REFU Upper limit determination value t0 unit period t1 period t2 judgment period

Claims (7)

A receiving unit that receives a radio signal containing predetermined data as well as pulses arranged at a predetermined period;
An amplifying unit for amplifying a signal received by the receiving unit;
An integration unit that integrates the signal amplified by the amplification unit for each window period that is a partial period in the period;
A counting unit that counts the number of times the integral value obtained by the integrating unit deviates from a predetermined determination range;
In the state where the wireless signal is not received by the receiving unit, the counting unit counts the number of times within a preset determination period, and the count value of the counting unit is an upper limit of a preset number of times set range. Is exceeded, the upper limit value of the determination range is increased and the lower limit value of the determination range is decreased. When the count value of the counting unit is lower than the lower limit of the set number of times range, the upper limit value of the determination range is decreased. And a determination range setting unit for setting the determination range so that the count value of the counting unit is within the set number of times range by increasing the lower limit value of the determination range,
A synchronizing unit that synchronizes the timing of the pulse and the timing of the window period in the signal received by the receiving unit;
In the synchronous window period that is a window period synchronized with the timing of the pulse, when the integrated value obtained by the integrating unit exceeds the upper limit of the determination range, the signal received by the receiving unit is the radio signal A determination unit for determining
And a demodulation unit that starts demodulation of the radio signal received by the reception unit when the determination unit determines that the signal received by the reception unit is the radio signal. Receiver device. Integration that adjusts the output level of the integration unit so that an average value of integration values obtained by the integration unit is within the determination range within a predetermined period when the wireless signal is not received by the reception unit. The radio reception apparatus according to claim 1, further comprising an offset initial adjustment unit. The difference between the maximum value and the minimum value of the integration value obtained by the integration unit is set to the difference between the upper limit and the lower limit of the determination range within a predetermined period when the radio signal is not received by the reception unit. The radio reception apparatus according to claim 1, further comprising an amplification factor initial adjustment unit that adjusts the amplification factor of the amplification unit so as to be close to each other. The integration value obtained by the integration unit in a plurality of the synchronization window periods counts the upper limit number of times that exceeds the upper limit of the determination range and the lower limit number of times that falls below the lower limit of the determination range within a preset period. Upper and lower limit counting part,
When the difference between the upper limit count and the lower limit count counted by the upper / lower limit count section exceeds a preset threshold value during operation, and when the upper limit count is greater than the lower limit count, the integration section 4. The integration offset adjusting unit according to claim 1, further comprising an integration offset adjusting unit that decreases the output level and increases the output level of the integrating unit when the lower limit number is larger than the upper limit number. Wireless receiver. The counting unit counts the number of times within the determination period, and the state where the count value of the counting unit exceeds the upper limit value of the set number of times range continues for a noise determination time longer than the communication frame length of the radio signal. The radio reception apparatus according to claim 1, further comprising an amplification factor adjustment unit that reduces the amplification factor of the amplification unit. The amplification factor adjustment unit may further increase the amplification factor of the amplification unit when the count value counted by the counting unit continues below the lower limit value of the set number of times exceeding the noise determination time. The wireless reception device according to claim 5, wherein the wireless reception device is increased. The demodulating unit integrates the integrated value obtained by the integrating unit during the synchronization window period during a unit period indicating 1-bit data, and the integrated value obtained exceeds a preset logic determination threshold value. The wireless signal of the unit period indicates a first logical value, and when the wireless signal of the unit period does not satisfy the logical determination threshold, the wireless signal of the unit period indicates the second logical value. Demodulate the signal,
A logic determination threshold value setting unit that newly sets, as the logic determination threshold value, a value obtained by multiplying the integrated value in the unit period determined to indicate the first logic value by the demodulation unit by a preset ratio; The wireless reception device according to claim 1, wherein the wireless reception device is a wireless communication device.

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