JP4888354B2 - Wireless receiver - Google Patents

Description

  The present invention relates to a radio receiving apparatus that receives radio signals.

  In recent years, as one of high-speed wireless transmission systems, an ultra wide band (UWB) communication system that performs ultra-wideband communication using a pulse signal sequence composed of pulse signals synchronized with a predetermined cycle timing has attracted attention. Yes.

  As a conventional radio receiving apparatus used in radio communication systems including the UWB communication system, Patent Document 1 discloses an antenna that receives a radio signal transmitted from a radio transmission apparatus, and detects a signal received by the antenna. A detector including a detector and a plurality of integration blocks each integrating a detection signal in an integration period and converting the integration value into a digital signal is disclosed.

The wireless receiver of Patent Document 1 changes the timing of two integration periods in opposite directions, and when the integrated value integrated in one integration period becomes maximum, the timing of the pulse of the wireless signal and the integration period The initial synchronization between the timing is taken.
JP 2007-60507 A

  However, although the wireless reception device of Patent Document 1 changes the timing of two integration periods, it is only one integration period that is used to determine whether or not the initial synchronization is finally achieved. Therefore, there is a problem that the accuracy of the initial synchronization cannot be increased. In addition, since the timing change direction of each integration period is determined in advance, there is a problem that it may take time to obtain initial synchronization. Specifically, even if the synchronization can be obtained immediately if the timing of the integration period is changed in a certain direction, the change direction of the timing of the integration period is predetermined in the opposite direction to the certain direction. It changes in the opposite direction and takes a very long time to synchronize.

  As a wireless reception apparatus that solves the above problem, using two integration periods shifted in timing, as shown in FIG. 9A, digital signals AD1 and AD2 that are integrated values in two integration periods are used. In at least one of the ranges above the threshold L0 (the range below L0 in FIG. 9A), the timing of the integration period of the integration circuit is changed so that these two digital signals AD1 and AD2 are equal, and synchronization is performed. What can be taken is considered.

  However, as shown in FIG. 9A, the above-described wireless receiving apparatus has two digital signals AD1 and AD2 inverted in magnitude when the magnitude relationship between the digital signals AD1 and AD2 of the two integrating circuits shifted in timing is normal. Since the initial synchronization can be normally performed only once, as shown in FIG. 9B, any one of the digital signals AD1 and AD2 (in the case of FIG. 9B, the digital signal If the AD2) is distorted and the two digital signals AD1 and AD2 are inverted in magnitude several times (twice in FIG. 9B), the timing of the two integration periods changes in the opposite direction. There was a new problem that the initial synchronization could not be taken.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a radio receiving apparatus capable of accurately obtaining initial synchronization.

  The invention of claim 1 is a radio receiving apparatus that receives a pulse composed of a plurality of ultrashort pulses intermittently in a predetermined cycle in synchronization with a radio signal and demodulates data contained in the radio signal, Receiving means for receiving the radio signal, and envelope detecting the signal received by the receiving means, and detecting means for outputting a detection signal including a pulse that is an envelope of the plurality of ultrashort pulses, respectively, The detection signal output from the detection means is integrated in an integration period of the same length, and a timing of one integration period of the pair of integration blocks having an integration circuit that outputs an integration value and one pair of the integration blocks Is controlled by the timing control means, which simultaneously changes the timings of the two integration periods in a state shifted from the timing of the other integration period in the advance direction. Comparison means for comparing the integration value of each of the pair of integration blocks with a threshold each time the timing of one integration period is changed, and in a range where at least one of the two integration values is equal to or greater than the threshold, By controlling the timing control means so as to change the timing of the two integration periods with respect to the timing of the pulse of the detection signal so that the two integration values are equal, the timing of the two integration periods is set. Synchronizing means for synchronizing with the pulse timing of the detection signal, and detecting the presence or absence of the pulse within the detection period with the center of the synthesis period of the two integration periods synchronized by the synchronizing means as the center of the detection period And decoding means for decoding the data contained in the wireless signal, and threshold setting means for setting the threshold level. And wherein the door.

  According to a second aspect of the present invention, in the first aspect of the invention, the threshold value setting means sets the maximum value to any one of the two integral values when the timing control means changes the timing of the two integral periods. A value obtained by multiplying a predetermined ratio is set as the threshold level.

  According to a third aspect of the present invention, in the second aspect of the present invention, the threshold value setting means can set the ratio variably.

  The invention of claim 4 is the invention of claim 2 or 3, wherein the threshold value setting means sets a lower limit value of the threshold value.

  According to the first aspect of the present invention, even when the integral value of any of the integral blocks is distorted and the magnitude relationship between the two integral values is inverted at a portion that is not originally assumed, it is used by the synchronizing means. By resetting the threshold value, initial synchronization can be performed in a range excluding a portion where the inversion of the magnitude relationship between the two integral values is not originally assumed, and pulse lost can be prevented.

  According to the invention of claim 2, it is possible to determine a threshold value corresponding to the magnitude of the integral value of each integration block.

  According to the invention of claim 3, the optimum threshold value can be set by changing the ratio of multiplying the maximum integral value.

  According to the invention of claim 4, by preventing the threshold from being lower than the lower limit value, it is possible to prevent erroneous recognition of noise as a pulse. Can be solved.

(Embodiment 1)
First, the configuration of the wireless reception apparatus according to the first embodiment will be described with reference to FIGS. This radio receiving apparatus receives a pulse composed of a plurality of ultrashort pulses (pulses having a pulse width of about 1 nanosecond) in synchronization with a UWB radio signal intermittently having a predetermined period, and is included in the radio signal. As shown in FIG. 1, an antenna (receiving means) 1 that receives the wireless signal from a wireless transmission device (not shown) and an envelope detection of the signal received by the antenna 1 as shown in FIG. Then, a detection block (detection means) 2 that outputs a detection signal including a pulse that is an envelope of a plurality of ultrashort pulses, and each of the detection signals output from the detection block 2 are integrated in an integration period of the same length. The _first to _n integration blocks 3 _{1 to} 3 _n having the integration circuits 30 ₁ to 30 _n for outputting the integration values and the signals (digital signals) output from the _first to _n integration blocks 3 _{1 to} 3 _n AD1 ~ An adder 4 for outputting Dn) as a sum value AD0 are added, with synchronization between the received signal SIG1 using digital signal AD1~ADn outputted from the integration block ₃ 1 to 3 _n of the 1~n The signal processing unit 5 that demodulates the data contained in the radio signal from the output signal (added value AD0) of the adder 4 and outputs it to the outside, the intermittent drive gate generation unit 6, and the first to n integration blocks And a phase control unit (timing control means) 7 that changes the timing of the integration periods 3 _{1 to} 3 _n .

  Here, an example of a radio signal will be described with reference to FIG. FIG. 3A is a diagram showing a communication frame F1 of a radio signal, and FIG. 3B is an enlarged view of a range A after the radio signal of FIG. 3A is detected by envelope detection. In the communication frame F1, as shown in FIG. 3A, a continuous pulse train F1 for achieving pulse synchronization, and a section without a pulse P and a section with a pulse P for bit synchronization are alternately arranged. The bit synchronization pulse array F2, the unique word F3 which is a pulse train for distinguishing the bit synchronization pulse array F2 and the data portion F4 described later, and “0” when there is no pulse P, and there is a pulse P It has a data part F4 in which the time is “1”. The pulses P are arranged with a period of 50 nanoseconds, for example, and the pulse width of the pulse P is set to 10 nanoseconds, for example. Each pulse P is composed of, for example, about 10 continuous ultrashort pulses.

  The continuous pulse train F11 is a pulse train for synchronizing the communication frame F1 and the reception timing of the wireless reception device. For example, the pulse P is continuous with a period of 50 nanoseconds for a period of about 100 microseconds to 900 microseconds.

  The pulse array F12 for bit synchronization is a pulse train for achieving bit synchronization, and a pulse-free interval B0 in which the pulse P does not exist during a preset unit period t0 and a pulse P interval in which the pulse P continues with a period of 50 nanoseconds B1 are alternately arranged.

  In the data portion F14, one pulse no-interval B0 and one pulse interval B1 are combined to represent 1-bit data, and in the bit interval tb representing 1 bit, for example, the pulse no-interval B0 Next, a bit “1” is represented when the pulsed section B1 is reached, and a bit “0” is represented when the pulseless section B0 is followed by the pulse-free section B1.

The detection block 2 shown in FIG. 1 includes an amplifying unit 20 that amplifies the received signal SIG1 received by the antenna 1, and a filter (band filter) that extracts a component of a use frequency band of a radio signal from the output signal SIG2 of the amplifying unit 20. 21 and a detector 22 that performs envelope detection on the output signal SIG3 of the filter 21 and outputs it as a detection signal K. For example, the reception signal SIG1 in the band of 3.8 GHz received by the antenna 1 is frequency-converted to about 500 MHz by the detection block 2, and the detection signal K is output from the detector 22 to each of the integration blocks 3 _{1 to} 3 _n . Is done.

Each of the integration blocks 3 _{1 to} 3 _n integrates the detection signal K in an integration period of a certain period, and outputs the integration signals 30 ₁ to 30 _n and the integration signals S ₁ to Sn which are output as analog integration signals S ₁ to Sn. AD converters 31 _{1 to} 31 _n that convert values into digital signals AD1 to ADn are provided. For example, the integration period is preferably 6 to 10 nanoseconds, and more preferably 8 nanoseconds.

The AD converters 31 _{1 to} 31 _n are, for example, 8 bits and 255 stages. Therefore, in the output of the digital signals AD1 to ADn from the AD converters 31 _{1 to} 31 _n to the adder 4 and the signal processor 5, one signal line is provided for each bit as shown in FIG. A total of 8 signal lines are used.

The adder 4 adds the digital signals AD1 to ADn output from the AD converters 31 _{1 to} 31 _n , that is, the digital values of the integration values of the integration circuits 30 ₁ to 30 _n , and the signal processing unit 5 as an addition value AD0. Output to.

As shown in FIG. 1, one signal line is assigned for each bit to the output of the added value AD0 from the adder 4 to the signal processing unit 5, and a total of (8+ (8+ ( n-1)) signal lines are used. n is the number of integration blocks 3 _{1 to} 3 _n (AD converters 31 _{1 to} 31 _n ). For example, when 8-bit digital signals AD1 to ADn are input to the adder 4 from each of the two AD converters 31 _{1 to} 31 _n , the added value AD0 output from the adder 4 carries 9 bits, that is, 8+ (N-1) bits. In addition, when 8-bit digital signals AD1 to ADn are input to the adder 4 from each of the three AD converters 31 _{1 to} 31 _n , the added value AD0 output from the adder 4 is the two AD converters 31. from 9bit state when the digital signal AD1~ADn is input from ₁ to 31 _n, since become more 10bit and up one digit at a maximum, the 8 + (n-1) bit .

  However, the number of bits necessary for the added value AD0 output from the adder 4 is not simply determined as 8+ (n-1), but in an actual circuit, it overflows to zero due to insufficient bits. In order not to return, a bit width with a margin is prepared. For example, when four digital signals AD1 to ADn of 255 (decimal number) = FF (hexadecimal number) are added, the addition value AD0 is 1020 (decimal number) = 3FC (hexadecimal number), so it is only necessary to add 2 bits. As a result, the number of bits required to output the added value AD0 may be 10 bits instead of 11 bits. Therefore, the remaining 1 bit is for giving a margin.

The intermittent drive gate generation unit 6 includes an oscillation circuit, for example, and performs integration operation on the integration circuits 30 ₁ to 30 _n at the same cycle as the pulse cycle of a radio signal transmitted from a radio transmission device (not shown). In order to achieve this, the circuit unit outputs a reference gate signal G indicating an integration period, that is, a window period.

The phase control unit 7 determines the timing of the integration period of the _first integration block 31 based on the reference gate signal G output from the intermittent drive gate generation unit 6 and the control signals SIG4 and SIG5 from the signal processing unit 5. the timing of the two integration periods so as to vary simultaneously in a state shifted in the advance direction than the timing of the second integration block 3 _second integration period, the integration circuit 30 _1, 30 timing of the _second integration period to be different from each The phase of the reference gate signal G is changed and output to the integration circuits 30 ₁ and 30 ₂ as the gate signals G1 and G2, respectively. The integration circuit is configured to simultaneously change the timings of the two integration periods while the timing of the integration period of the k-th integration block 3 _k is also shifted in the advance direction from the timing of the integration period of the (k + 1) -th integration block 3 _{k + 1.} The phase of the reference gate signal G is changed so that the timings of the integration periods 30 _k and 30 _{k + 1} are different from each other, and are output to the integration circuits 30 _k and 30 _{k + 1} as the gate signals Gk and Gk _{+ 1} , respectively. k is 1, 3, 5... n−1.

Here, the relative change of the pulse period of a radio | wireless transmitter (not shown) and the pulse period of a radio | wireless receiver is demonstrated using FIG. First, when the period of the pulse P (radio signal pulse) of the detection signal K is longer than the period of the integration period of the _two integration blocks 3 ₁ and 3 ₂ (represented by the gate signals G1 and G2 in FIG. 4), The timings of the two integration periods change with respect to the timing of the pulse P of the detection signal K in the direction indicated by the arrow a in FIG. In this case, in the digital signals AD1 and AD2, first, the digital signal AD1 is larger than the digital signal AD2 in (1), and the digital signal AD1 is maximum in (2). Thereafter, in (3), the center of the combined integration period of the two integration periods coincides with the center of the pulse P, and the digital signal AD1 and the digital signal AD2 are equal. In (3) to (4), the digital signal AD2 is more digital. It becomes larger than the signal AD1.

On the other hand, when the cycle of the pulse P of the detection signal K is shorter than the cycle of the integration period of the _two integration blocks 3 ₁ and 3 ₂ , the timing of the pulse P of the detection signal K in the direction indicated by the arrow b in FIG. The timing of the two integration periods is delayed. In this case, the digital signals AD1 and AD2 are initially larger in (4) than in the digital signal AD1, and in (3) the center of the combined integration period of the two integration periods coincides with the center of the pulse P. The digital signal AD1 is equal to the digital signal AD2. Thereafter, the digital signal AD1 becomes maximum in (2), and the digital signal AD1 becomes larger than the digital signal AD2 in (2) to (1).

  As shown in FIG. 2, the signal processing unit 5 includes a synchronization unit 50, a baseband decoding unit (decoding unit) 52, and a threshold setting unit (threshold setting unit) 51.

  The synchronization unit 50 includes a signal arrival determination unit (comparison unit) 500, a signal acquisition / tracking control unit (synchronization maintaining unit) 501, and a synchronization control unit 502.

Signal incoming determination unit 500, a first integrator block 3 ₁ of the integration interval and the second integrator block 3 _second integration interval in shaft synchronization control unit 502 described later time so as to overlap partially, two integration When the timing of the period is simultaneously changed in one direction (see FIG. 4), the digital signals AD1 and AD2 output from the _first and _second integration blocks 3 ₁ and 3 ₂ and the threshold setting unit 51 are set. And the result of determination as to whether or not the digital signals AD1 and AD2 are equal to or greater than the threshold is output to the synchronization control unit 502 as a determination signal H.

Synchronization control unit 502, first, simultaneously changing the timing of the two integration periods in a state of shifting the timing of the first integration block 3 ₁ integration period in a direction advances the timing of the second integration block 3 ₂ integration period The phase control unit 7 is controlled so that

The synchronization control unit 502 determines that the two digital signals AD1 and AD2 are equal in a range where at least one of the two digital signals (integrated values) AD1 and AD2 is equal to or greater than a threshold based on the determination signal H from the signal arrival determination unit 500. as to vary both the timing of the first integrating circuit 30 ₁ of the integration period and the second integrating circuit 30 _second integration period at the same time made to control the signal acquisition / tracking control unit 501.

Signal acquisition / tracking control unit 501, among the first and second integration block ₃ 1, _{3 2} of the digital signals AD1, AD2, the first integration block _{3 1} and a second integrator which is selected by the synchronization control unit 502 as block _{3 2} digital signals AD1, AD2 is equal, and outputs a control signal SIG5 the phase controller 7.

Specifically, in two at least one of equal to or larger than the threshold value range of the digital signals AD1, AD2, if the first integration block _{3 1} of the digital signal AD1 is greater than the second integration block _{3 2} digital signal AD2, The timing of the two integration periods is shifted in the advance direction with respect to the timing of the pulse P of the detection signal K. On the other hand, if the second integration block 3 ₂ digital signal AD2 is greater than the first integration block 3 ₁ of the digital signal AD1, the timing of the two integration periods in the delay direction with respect to the timing of the pulses P of the detection signal K The phase control unit 7 is controlled to shift. As described above, the two digital signals AD1 and AD2 are made equal to synchronize the timing of the two integration periods with the timing of the pulse P of the detection signal K.

In addition, after initial synchronization, the signal acquisition / tracking control unit 501 uses the timing of the two integration periods of the _first and _second integration blocks 3 ₁ and 3 ₂ as the timing of the pulse P of the detection signal K in the normal state. On the other hand, the phase controller 7 is controlled so as to shift by a certain shift amount in either the forward direction or the backward direction, and the difference (AD1-AD2) between the two digital signals (integral values) AD1, AD2 is controlled. It is determined whether the polarity is reversed. When it is determined that the polarity of the difference (AD1-AD2) between the two digital signals AD1 and AD2 is inverted, the signal acquisition / tracking control unit 501 determines the timing of the two integration periods with respect to the timing of the pulse P of the detection signal K. Then, the phase control unit 7 is controlled so as to shift in the reverse direction by a preset shift amount. Note that the preset shift amount is a shift amount larger than a certain shift amount.

  At this time, the signal acquisition / tracking control unit 501 determines whether to shift the timing of the two integration periods in the forward direction or the delay direction with respect to the pulse P of the detection signal K in the normal state. It has a function of selecting by setting from a computer. For example, when the relationship between the two digital signals AD1 and AD2 and the shift direction are different due to an unexpected condition compared to the design time due to the influence of noise of an analog circuit such as an integration circuit or a detection circuit. However, the signal can be tracked without making a determination error, and an increase in error rate can be prevented.

  As shown in FIG. 5, the threshold setting unit 51 can select and set a plurality of threshold levels (L1 to L3). The threshold setting unit 51 is provided with an operation unit (not shown) for the user to select a threshold, and the user can set the thresholds L1 to L3 in advance using the operation unit. . Further, when initial synchronization cannot be achieved within a predetermined time at a preset threshold value (for example, L1), the threshold value setting unit 51 automatically uses another threshold value (for example, L3) instead of the threshold value (L1). Set. Information on the thresholds L1 to L3 set by the threshold setting unit 51 is output to the signal arrival setting unit 53 as a threshold signal L.

  The baseband decoding unit 52 shown in FIG. 2 detects the presence or absence of the pulse P within the detection period with the center of the synthesis period of the two integration periods synchronized by the synchronization unit 50 as the center of the detection period, The data contained in is decrypted. Specifically, the baseband decoding unit 52 determines “1” if the addition value AD0 output from the adder 4 is equal to or greater than a certain value, and “0” if the addition value AD0 is less than the certain value. The signal is demodulated by determination and output to the outside as a decoded signal Dout.

Next, the initial synchronization operation in the wireless reception device of this embodiment will be described. Here, the case of using the first integration block 3 ₁ and only the second integration block 3 _2. In the initial state where the reception of the radio signal by the antenna 1 is started, the timing of the pulse P (see FIG. 4) of the detection signal K output from the detector 22 and the _first and _second integration circuits 30 ₁ and 30 ₂ Since the timing of the integration period is not synchronized, when the continuous pulse train F11 is received in the communication frame F1 of the wireless signal (see FIG. 3A), the _first and _second integration circuits 30 ₁ and 30 ₂ It is necessary to perform an initial synchronization process for synchronizing the timing with the timing of the pulse P of the detection signal K.

  First, in response to the control signal SIG4 from the synchronization control unit 502, the phase control unit 7 gradually changes the integration period simultaneously with the pulse P in the advance direction. The timing of the digital signals AD1 and AD2 in FIG. 5 moves from left to right. As the two integration periods change in the advance direction with respect to the pulse P, the first digital signal AD1 increases, and then the second digital signal AD2 also increases. However, since the first and second digital signals AD1 and AD2 are less than the threshold value L3, the timings of the two integration periods are directly changed in the advance direction with respect to the timing of the pulse P. Thereafter, when the first digital signal AD1 becomes equal to or greater than the threshold value L3, when the first digital signal AD1 is larger than the second digital signal AD2, the two integration periods change in the advance direction with respect to the pulse P. When the second digital signal AD2 is larger than the first digital signal AD1, the two integration periods are changed in the delay direction with respect to the pulse P. After that, when the first digital signal AD1 and the second digital signal AD2 become equal, it is determined that synchronization is established between the timing of the two integration periods and the timing of the pulse P, and the initial synchronization processing is terminated.

  Next, a case where the two integration periods are gradually changed in the delay direction with respect to the pulse P will be described. The digital signals AD1 and AD2 in FIG. 5 move from right to left. When the two integration periods are changed in the delay direction with respect to the pulse P, since the second digital signal AD2 is distorted, the first digital signal AD1 first increases, and then the second digital signal AD2 is getting bigger. However, since the first and second digital signals AD1 and AD2 are less than the threshold value L3, the two integration periods are changed in the delay direction with respect to the pulse P as they are. After that, when the magnitude relationship between the first and second digital signals AD1 and AD2 is reversed and the second digital signal AD2 is greater than or equal to the threshold L3, the second digital signal AD2 is greater than the first digital signal AD1. The two integration periods change in the delay direction with respect to the pulse P, and when the first digital signal AD1 is larger than the second digital signal AD2, the two integration periods are moved in the advance direction with respect to the pulse P. Change. After that, when the first digital signal AD1 and the second digital signal AD2 become equal, it is determined that synchronization is established between the timing of the two integration periods and the timing of the pulse P, and the initial synchronization processing is terminated.

  On the other hand, when the initial synchronization cannot be achieved within a predetermined time, the wireless reception device of the present embodiment resets the threshold in the threshold setting unit 51 and performs the initial synchronization again.

In the initial synchronization processing, the example in which the initial synchronization is performed by changing the timing of the integration period of the integration blocks 3 ₁ and 3 ₂ has been described. However, the n synchronization blocks 3 _{1 to} 3 _n are used to perform n synchronization. / Initial synchronization may be performed by changing the timing of two sets of integration periods. In this case, the processing time of the initial synchronization processing can be reduced to about 2 / n compared to the case where the initial synchronization is performed while shifting one set of integration periods.

  Next, an operation for tracking signals while maintaining synchronization after the initial synchronization processing is performed in the wireless reception device of the present embodiment will be described. The period of the pulse P of the detection signal K (the pulse of the radio signal) and the period of the two integration periods due to a deviation of the period of the crystal transmission circuit of the radio transmission device (not shown) or the intermittent drive gate generation unit 6 Since there may be a difference between them, the timing of the two integration periods is shifted with respect to the timing of the pulse P of the detection signal K (the pulse of the radio signal), and this timing shift increases with time. It becomes impossible to synchronize.

  Therefore, in the wireless receiver of the present embodiment, two digital signals AD1, AD2 are included in the bit synchronization pulse array F12, the unique word F13, and the data portion F14 in the communication frame F1 (see FIG. 3A) of the wireless signal. Is used to adjust the timing of the two integration periods to be synchronized with the timing of the pulse P.

  Specifically, in the normal state, the synchronization control unit 502 controls the timing of the two integration periods to shift in the delay direction (or advance direction), for example, by 1 nanosecond. At this time, the difference (AD1-AD2) between the two digital signals AD1, AD2 is calculated, and the polarity of the difference (AD1-AD2) is detected. If it is determined that the polarity of the difference (AD1-AD2) has been reversed, the timing of the two integration periods is shifted in the opposite direction, for example, by 2 nanoseconds. By repeating these operations, synchronization between the timing of the two integration periods and the timing of the pulse P of the detection signal K is maintained.

As described above, according to this embodiment, the digital signals (integrated values) AD1 and AD2 of any of the integration blocks 3 ₁ and 3 ₂ are distorted, and the magnitude relationship between the two digital signals AD1 and AD2 is not originally assumed. Even in the case of inversion in a part, by resetting the threshold value used in the synchronization unit 50, initial synchronization is performed in a range excluding the part where the inversion of the magnitude relationship between the two digital signals AD1 and AD2 is not originally assumed. And pulse loss can be prevented. That is, a plurality of threshold values L1 to L3 can be set in the threshold setting unit 51, and an optimum threshold value is selected for the two digital signals AD1 and AD2, and the integration circuits 30 ₁ to 30 _n have a range that is _equal to or greater than the threshold value. By setting the integration period, pulse lost due to a determination error immediately after signal acquisition can be prevented.

(Embodiment 2)
By the way, in the wireless reception device of the first embodiment, since the threshold level is set based on the normal state, as shown in FIG. 6B, when the digital signal is extremely larger than the normal state, If there is a large variation in the timing difference between the integration periods of the two integration circuits, the magnitude inversion of the two digital signals occurs twice within a range that is larger than all the preset threshold values. May change the direction of the change, and as a result, pulse lost may occur.

  Therefore, in the wireless reception device according to the second embodiment, the threshold setting unit 51 uses two digital signals (integrations) when the synchronization control unit 502 changes the timings of the two integration periods as illustrated in FIG. Value) A value obtained by multiplying the maximum value of either AD1 or AD2 by a predetermined ratio (for example, any of 50% or more and 99% or less) is automatically set to the threshold level (L4 in FIG. 6A). Set to. In addition, about the component similar to Embodiment 1, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  In the wireless reception device of the present embodiment, the synchronization control unit 502 changes the timing of the integration period before initial synchronization, the signal arrival determination unit 500 detects the digital signals AD1 and AD2 at each timing, and the threshold value The setting unit 51 obtains the maximum value of the digital signals AD1, AD2 from these digital signals AD1, AD2. Then, the threshold value setting unit 51 automatically sets the threshold value by multiplying the maximum value of the digital signals AD1 and AD2 by a predetermined ratio.

  By the way, as shown in FIG. 7, a threshold lower limit value MIN is preset in the threshold setting unit 51. The threshold value setting unit 51 compares the automatically set threshold value with the lower limit value MIN. When the automatically set threshold value is greater than or equal to the lower limit value MIN as shown in FIG. 7, the threshold value L5 is used as it is. When the automatically set threshold value is lower than the lower limit value MIN as in the threshold value L6, the lower limit value MIN is set as the threshold value instead of the automatically set threshold value L6.

As described above, according to the present embodiment, it is possible to determine a threshold corresponding to the magnitudes of the digital signals (integrated values) AD1 and AD2 of the integration blocks 3 ₁ and 3 ₂ . As a result, the number of inversions of the two digital signals AD1 and AD2 above the threshold can be reduced to one, and the initial synchronization can be normally performed.

  In addition, since the threshold value is not set lower than the lower limit value, it is possible to prevent erroneous recognition of noise as a pulse, so that the problem that initial synchronization cannot be performed with the pulse can be solved.

  As a modification of the second embodiment, the digital signal AD1 acquired in the previous initial synchronization is not obtained by changing the timing of the integration period before the initial synchronization, but by obtaining the maximum value of the digital signals AD1 and AD2. , AD2 may be stored, and the stored maximum values of the digital signals AD1, AD2 may be used.

(Embodiment 3)
By the way, in the radio receiving apparatus of the second embodiment, the digital signal AD1 as shown in FIG. 8B due to the influence of the temperature environment and the jitter of the gate signals G1 and G2 with respect to the maximum value of the digital signals AD1 and AD2. If the digital signal AD1 or AD2 is inverted twice at a threshold value L7 or more that is set by multiplying the maximum value of AD2 by a preset ratio, the change direction of the integration period is wrong and initial synchronization is taken. The possibility of pulse loss increases.

  Therefore, in the wireless reception device according to the third embodiment, the threshold setting unit 51 can variably set the ratio by which the maximum values of the digital signals AD1 and AD2 are multiplied. In addition, about the component similar to Embodiment 2, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  In the threshold setting unit 51 of the present embodiment, for example, a value of 50% or more and 99% or less can be selected and set as a threshold with respect to the maximum value of the digital signals AD1 and AD2. That is, as shown in FIG. 8A, the range between the threshold value L8 and the threshold value L10 can be set continuously or stepwise with the threshold values L7, L8, L9, and L10. In addition, when initial synchronization cannot be achieved within a predetermined time at a preset threshold value, the threshold value setting unit 51 automatically changes the threshold value to another rate instead of the previous rate, thereby changing the threshold value. Can be set again.

  As described above, according to the present embodiment, the optimum threshold value can be set by changing the ratio of multiplying the maximum values of the digital signals (integrated values) AD1 and AD2. As a result, the number of times the magnitude relationship between the two digital signals AD1 and AD2 is inverted when the threshold value is exceeded can be set to one, and pulse lost can be avoided.

It is a block diagram which shows the structure of the radio | wireless receiver of Embodiment 1-3. It is a block diagram which shows the structure of the signal processing part in a radio | wireless receiver same as the above. It is a figure which shows the radio signal received with the radio | wireless receiver same as the above. It is a figure for demonstrating the synchronization in a radio | wireless receiver same as the above. FIG. 3 is a diagram illustrating a relationship between reception energy and a threshold value in the wireless reception device according to the first embodiment. 6 is a diagram illustrating a relationship between received energy and a threshold value in the wireless reception device of Embodiment 2. FIG. It is a figure which shows the relationship between the reception energy and threshold value in a wireless receiver same as the above. FIG. 10 is a diagram illustrating a relationship between reception energy and a threshold in the wireless reception device according to the third embodiment. It is a figure which shows the relationship between the reception energy and threshold value in the basic composition of the radio | wireless receiver of this invention.

Explanation of symbols

1 Antenna 2 detection block ₃ 1 to 3 _n integration block ₃₀ 1 to 30 _n integration circuit 5 the signal processing unit 7 the phase controller

Claims (4)

A radio reception apparatus that receives a pulse composed of a plurality of ultrashort pulses intermittently in a predetermined cycle in synchronization with a radio signal and demodulates data contained in the radio signal,
Receiving means for receiving the radio signal;
Detecting the envelope received from the signal received by the receiving means, and outputting a detection signal including a pulse that is an envelope of the plurality of ultrashort pulses;
A pair of integration blocks each having an integration circuit for integrating a detection signal output from the detection means in an integration period of the same length and outputting an integration value;
Timing control means for simultaneously changing the timings of the two integration periods in a state in which the timing of one integration period of the pair of integration blocks is shifted in the advance direction from the timing of the other integration period;
Comparison means for comparing each integrated value of the pair of integration blocks with a threshold each time the timing of the two integration periods is changed by the timing control means;
The timing of the two integration periods is changed with respect to the pulse timing of the detection signal so that the two integration values are equal in a range where at least one of the two integration values is equal to or greater than the threshold value. Synchronization means for synchronizing the timing of the two integration periods with the timing of the pulse of the detection signal by controlling the timing control means;
The center of the synthesis period of the two integration periods synchronized by the synchronization means is set as the center of the detection period, and the presence or absence of the pulse in the detection period is detected to decode the data included in the radio signal Decryption means;
A radio receiving apparatus comprising: threshold setting means for setting the threshold level.   The threshold setting means sets a value obtained by multiplying a maximum value of any one of the two integral values when the timing control means changes the timing of the two integration periods by a predetermined ratio as the threshold level. The wireless reception device according to claim 1, wherein:   The radio reception apparatus according to claim 2, wherein the threshold value setting means can set the ratio variably.   The radio reception apparatus according to claim 2 or 3, wherein the threshold value setting means sets a lower limit value of the threshold value.

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