JP4461982B2 - Receiver - Google Patents

Description

  The present invention relates to a communication method for ultra-wideband communication. And it is related with the receiver which utilizes such a communication method.

  In recent years, attention has been paid to an ultra wide band (UWB) communication system that performs ultra-wideband communication using a pulse signal sequence composed of pulse signals synchronized with a predetermined cycle timing as one of high-speed wireless transmission systems. Yes. In one aspect of UWB communication, communication is performed using a pulse signal sequence composed of extremely fine pulse signals such as a pulse width of 1 nsec or less without using a carrier wave. As a modulation method used in such UWB communication, pulse position modulation (PPM) expressing “0” and “1” information by using a signal in which the pulse generation timing is slightly shifted back and forth is used. It is known (for example, refer to Patent Document 1). In addition, as another modulation method, on-off keying (OOK) representing “1” and “0” information depending on the presence / absence of a pulse signal, and “0” and “1” information depending on a change in pulse phase. Bi-phase modulation that expresses the above is known.

  FIG. 18 is a block diagram showing a UWB communication receiving apparatus 100 according to the background art. A receiving apparatus 100 illustrated in FIG. 18 includes an antenna 101 that receives a UWB communication signal transmitted from a transmitting apparatus using UWB communication, an amplifier 102 that amplifies the UWB communication signal received by the antenna 101, and a UWB that uses the transmitting apparatus. A decoder source 103 for generating a decode control signal corresponding to the same known PN (Pseudorandom Noise) code used to generate the communication signal, and a waveform substantially equivalent to each pulse of the received signal; An adjustable time base 104 for generating a periodic timing signal including a pulse train of a template signal, and a decoding time modulator for generating a decoded signal temporally coincident with a known PN code of a transmission apparatus based on the decoding control signal and the periodic timing signal 105 and the correlation between the received signal amplified by the amplifier 102 and the decoded signal A cross-correlator 106 that generates a correlation voltage, a low-pass filter 107 that feeds back the correlation voltage to the adjustable time base 104, and a sub-carrier demodulator 108 that removes the sub-carrier from the correlation voltage and restores the received data. It has.

Then, the cross-correlator 106 correlates the received signal amplified by the amplifier 102 and the decoded signal temporally matched with the known PN code of the transmitting apparatus, so that every bit from the received signal. The data of can be acquired.
Japanese National Patent Publication No. 10-508725

  By the way, in the receiving apparatus 100 as described above, in order to acquire 1-bit data from the received signal, it is necessary to generate a correlation value between the received signal and the PN code. In order to do this, it is necessary to receive a UWB communication signal that is longer than the length of the PN code, which is a signal pattern that represents a unit of data, and there is a disadvantage in that the communication speed decreases.

  Further, for example, if a part of the receiving apparatus 100 such as the amplifier 102 or the cross correlator 106 fails, data cannot be acquired from the UWB communication signal, and it is determined whether communication is not performed or the receiving apparatus 100 is faulty. Since it cannot be determined, there is a disadvantage that a failure of the receiving apparatus 100 cannot be detected.

The present invention aims to provide such an invention der was made in view of the problems it is, detecting and receiving device that can be made to improve the reliability of communication failures RECEIVER .

  In order to achieve the above-mentioned object, a communication method according to the first means of the present invention is a communication method for performing communication using a communication frame having a pulse train for data representing data by a pulse train modulated by an on-off keying method. In the data pulse train, a channel is assigned to each time slot obtained by subdividing a pulse section which is a time given to a signal pattern as a unit representing data into a plurality of time slots, and the signal pattern Is characterized in that it represents multiple bits of data depending on the presence or absence of a pulse in each channel of the pulse interval.

  The receiving apparatus according to the second means of the present invention comprises a data pulse train representing data by a pulse train modulated by an on-off keying method, and the data pulse train is applied to a signal pattern as a unit representing data. A channel is assigned to each time slot obtained by subdividing a pulse period, which is a time period, into a plurality of time slots, and the signal pattern represents a communication frame representing data of a plurality of bits depending on the presence or absence of a pulse in each channel of the pulse period. A receiving unit that receives the communication frame, and a plurality of bits of data based on the presence or absence of a pulse in each channel of the pulse section in the data pulse train of the communication frame received by the receiving unit A data acquisition unit for acquiring It is a symptom.

  Further, in the above-described receiving apparatus, the communication frame represents a plurality of bits of data depending on the number of pulses included in the pulse section in the data pulse train, and the data acquisition unit includes the data pulse train. A first integration circuit that integrates a pulse in the pulse interval, and a first integration value determination unit that generates data of a plurality of bits from an integration value obtained by the first integration circuit.

  In the above-described receiving device, the communication frame represents data of a plurality of bits by an arrangement pattern of pulses in each channel of the pulse interval in the data pulse train, and the data acquisition unit includes the pulse interval And a plurality of second integration circuits for integrating the plurality of channels respectively, and a second integration value determination unit for generating a plurality of bits of data from the integration values obtained by the plurality of second integration circuits. It is said.

  A communication method according to the third means of the present invention is a communication method for performing communication using a communication frame having a data pulse train representing data by a pulse train modulated by an on-off keying method, In the pulse train, a channel is assigned to each time slot obtained by subdividing a pulse interval, which is a time given to a signal pattern as a unit representing data, into a plurality of time slots, and the signal pattern is a first in the pulse interval. Bit data “0” is represented by having a pulse in one channel, and bit data “1” is represented by having a pulse in a second channel different from the first channel in the pulse section. .

  The receiving apparatus according to the fourth means of the present invention comprises a data pulse train representing data by a pulse train modulated by an on-off keying method, and the data pulse train is applied to a signal pattern as a unit representing data. A channel is assigned to each time slot obtained by subdividing a pulse section, which is a time period, into a plurality of time slots, and the signal pattern has bit data “0” by having a pulse in the first channel in the pulse section. And a receiving device for receiving a communication frame representing bit data “1” by having a pulse in a second channel different from the first channel in the pulse period, and receiving the communication frame And the data of the communication frame received by the receiving unit. A pulse detector for detecting presence / absence of pulses in the first and second channels in the pulse section of the pulse train, and pulses in the first and second channels detected from the pulse section by the pulse detector When a pulse is detected in both the first and second channels in the pulse interval by the data acquisition unit that acquires 1-bit data from the pulse interval based on the presence or absence of the pulse, and the pulse detection unit, a failure occurs. And a failure determination unit that determines that occurrence has occurred.

  Furthermore, in the above-described receiving device, the pulse detection unit includes a third integration circuit that integrates the first channel in the pulse interval, a fourth integration circuit that integrates the second channel in the pulse interval, When the integration value by the third integration circuit exceeds a preset threshold value, it is determined that there is a pulse in the first channel, and the integration value by the fourth integration circuit exceeds a preset threshold value And a first presence / absence determining unit that determines that there is a pulse in the second channel.

  In the above-described receiving device, the pulse detection unit may include a fifth integration circuit that sequentially integrates the first channel and the second channel in the pulse period, and the fifth integration circuit. When the integral value of one channel exceeds a preset threshold value, it is determined that there is a pulse in the first channel, and the integral value of the second channel by the fifth integrating circuit is a preset threshold value. And a second presence / absence determining unit that determines that the second channel has a pulse when the second channel is exceeded.

Receiving device configuration as this, the data pulse train representing the data, in each time slot obtained by dividing the pulse period is the time given to the signal pattern to be one unit representing data into a plurality of time slots Each channel is assigned, and the signal pattern represents bit data “0” by having a pulse in the first channel in the pulse interval, and has a pulse in a second channel different from the first channel in the pulse interval. Therefore, the communication is performed using the communication frame representing the bit data “1”, so that the first and second channels in the pulse section in the data pulse train of the communication frame received by the receiving unit by the pulse detecting unit. The presence or absence of pulses in the Ri 1-bit data from the pulse interval based on the presence or absence of a pulse in the first and second channels that are detected from the pulse interval is obtained. The failure determination unit determines that a failure has occurred when a pulse is detected in both the first and second channels in the pulse interval by the pulse detection unit. Communication reliability can be improved.

  Embodiments according to the present invention will be described below with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted.

(First embodiment)
FIG. 1 is a diagram illustrating an example of a communication frame used in a communication method according to an embodiment of the present invention. First, signals used in a communication method according to an embodiment of the present invention will be described. A communication frame 21 shown in FIG. 1 is modulated by an on / off keying method, and a pulse synchronization pulse train 22 for synchronizing pulse positions in the communication frame 21 and a bit position in communication frame 21 after pulse synchronization are synchronized. For this purpose, and a data pulse train 24 representing data.

  FIG. 2 is a waveform diagram showing an example of the details of the pulse synchronization pulse train 22 shown in FIG. 2 is a pulse train in which, for example, a pulse P1 having a pulse width of 1 nsec is continuous with a minimum pulse period, for example, a pulse period T1 of 10 nsec. In the receiving apparatus 1 shown in FIG. 6 to be described later, pulse synchronization is performed based on the pulse synchronization pulse train 22 by a pulse synchronization circuit (not shown), and a clock signal CK that is synchronized with the pulse P1 of the pulse synchronization pulse train 22 is generated. The

  FIG. 3 is a waveform diagram showing an example of the details of the bit synchronization pulse train 23 shown in FIG. In the pulse sequence for bit synchronization 23, a pulse interval T2, which is a time given to a signal pattern as a unit representing data, is set to, for example, four times the pulse period T1, and the pulse sequence for bit synchronization 23 is, for example, a pulse P1. The pulse section T2 including four consecutive pulses and the pulse section T2 having no pulse P1 are alternately repeated. In the receiving apparatus 1 shown in FIG. 6, the bit synchronization is performed based on the bit synchronization pulse train 23 by a not-illustrated bit synchronization circuit, and the pulse section T2 is divided into, for example, four channels based on the clock signal CK. Channel numbers 1, 2, 3, and 4 are assigned from the beginning of the pulse period T2. As a result, the communication frame 21 received by the receiving apparatus 1 shown in FIG. 6 is synchronized with the pulse interval T2 and the channel.

  4A is a waveform diagram showing the channel number and the clock signal CK, and FIGS. 4B to 4E are waveform diagrams showing an example of the configuration of the data pulse train 24. FIG. The data pulse train 24 shown in FIG. 6 is divided into a plurality of pulse sections T2, and a plurality of pulse sections T2, for example, 127 pulse sections T2, form a bit section T3 representing 2-bit data. Further, each pulse section T2 is divided into a plurality of time slots, for example, four time slots, and channels 1, 2, 3, 4 are assigned to the respective time slots.

  Then, a synchronization pulse P2 for synchronizing the pulse position is arranged in a predetermined channel, for example, channel 1, by modulation by the on / off keying method. Also, as shown in FIG. 4B, in the data pulse train 24, when the bit section T3 represents 2-bit binary data “11”, for example, the pulse P1 is arranged in the channels 2, 3 and 4, That is, the pulse period T2 includes three pulses P1. Similarly, when the bit section T3 represents 2-bit binary data “10”, as shown in FIG. 4 (c), for example, the pulse P1 is arranged in the channels 2 and 3, that is, the pulse P1 in the pulse section T2. 2 and the bit interval T3 represents 2-bit binary data “01”, for example, the pulse P1 is arranged in the channel 2 as shown in FIG. 4D, that is, the pulse interval T2 has a pulse P1. When one P1 is included and the bit interval T3 represents 2-bit binary data “00”, for example, the pulse interval T2 does not include the pulse P1 as shown in FIG.

  Note that the bit period T3 is not limited to the example representing 2-bit data, and may represent data of 3 bits or more by increasing the number of channels for arranging the pulse P1 in the pulse period T2. The pulse section T2 may be configured without the synchronization pulse P2. The number of channels allocated to the pulse section T2 is determined according to the number of bits represented by the bit section T3 and the presence or absence of the synchronization pulse P2, and is not limited to four channels. Further, the number of pulse sections T2 included in the bit section T3 is determined according to, for example, the degree of reliability required for communication, and is not limited to an example in which the bit section T3 is configured by 127 pulse sections T2. .

  Next, a transmission device and a reception device that perform communication using such signals will be described. FIG. 5 is a block diagram showing an example of a transmission apparatus that transmits the data pulse train 24 shown in FIG. FIG. 6 is a block diagram showing an example of a receiving apparatus according to the first embodiment of the present invention. 5 includes, for example, a transmission clock generation unit 12 that outputs a transmission clock signal CKS having a pulse period T1, and a control signal for converting transmission data into a pulse signal pattern in a data pulse train 24 by two bits. A signal pattern generation unit 13 that outputs SP, an AND circuit 14 that outputs a logical product of the transmission clock signal CKS and the control signal SP as a signal pattern PP1, and a pulse signal generation that generates a pulse signal of, for example, 1 nsec from the signal pattern PP1 Unit 15, a bandpass filter 16 that limits the band of the pulse generated by the pulse signal generation unit 15, and a transmission antenna 17 that radiates the transmission signal PP 3 output from the bandpass filter 16. Yes.

  A receiving apparatus 1 shown in FIG. 6 includes a receiving antenna 2 that is an example of a receiving unit, an amplifier 3 that amplifies a received signal, a detector 4 that detects the received signal, and a low-pass filter that removes high-frequency noise. (LPF) 5, a data integrator 6 that is an example of a first integration circuit, an integration value determination unit 7 that is an example of a first integration value determination unit, and a synchronization pulse included in the data pulse train 24 And a synchronization correction unit 8 that detects P2 and corrects the pulse synchronization timing. The data integrator 6 and the integral value determination unit 7 constitute a data acquisition unit.

  The synchronization correction unit 8 integrates the pulse section T2 in the data pulse train 24 output from the low-pass filter 5 with respect to the channel in which the synchronization pulse P2 is arranged, for example, channel 1, based on the clock signal CK. 81, a progress integrator 82 that integrates the pulse section T2 at a timing advanced from the channel where the synchronization pulse P2 is arranged, for example, a timing advanced by a pulse period T1 from the channel 1, and a synchronization pulse P2 are arranged A delay integrator 83 that integrates the pulse interval T2 at a timing advanced from the channel to be transmitted, for example, a timing delayed by a pulse period T1 from the channel 1, a synchronization integrator 81, a progress integrator 82, and a delay integrator 83. The timing of the clock signal CK is adjusted according to the integrated value of the data integrator 6 and Output to a separatory value determination unit 7 for, and a synchronization timing detecting section 84 for correcting the pulse synchronization timing.

  The data integrator 6 integrates the pulse section T2 in the data pulse train 24 output from the low-pass filter 5 with respect to the channels where the pulse P1 is arranged in synchronization with the clock signal CK, for example, channels 2, 3, and 4. Then, the integration value SI is output to the integration value determination unit 7.

  The integral value determination unit 7 includes comparators 71, 72, 73 that compare the integral value SI obtained by the data integrator 6 with preset reference values Ref1, Ref2, Ref3, and comparators 71, 72, 73. A data determination unit 74 is provided that acquires 2-bit data for each bit interval T3 according to the comparison result and outputs the received data as received data RD to the outside. The reference values Ref1, Ref2, Ref3 are set so that the values increase in this order. When the integral value SI is less than or equal to the reference value Ref1, the data value represented by the integral value SI is “00”, and the integral value SI is When the reference value Ref1 exceeds the reference value Ref2 and below, the data value represented by the integral value SI is “01”, and when the integral value SI exceeds the reference value Ref2 and below the reference value Ref3, the data represented by the integral value SI When the value is “10” and the integral value SI exceeds the reference value Ref3, the reference values Ref1, Ref2, and Ref3 are set so that the data value represented by the integral value SI is “11”.

  Next, the transmission / reception operation of the data pulse train 24 by the transmission device 11 and the reception device 1 configured as described above will be described. The transmission of the pulse synchronization pulse train 22 and the pulse synchronization using the same, and the transmission of the bit synchronization pulse train 23 and the bit synchronization using the same are the same as those in the prior art, and the description thereof will be omitted. First, the transmission operation of the data pulse train 24 by the transmitter 11 will be described. FIG. 7 is a timing chart for explaining the operation of the transmission apparatus 11 shown in FIG. First, the transmission clock generator 12 outputs the clock signal CKS to the AND circuit 14 at a cycle of the pulse cycle T1. Next, transmission data to be transmitted is received by the signal pattern generation unit 13.

  Then, the signal pattern generation unit 13 outputs a control signal SP for converting the transmission data into a pulse signal pattern in the data pulse train 24 by 2 bits to the AND circuit 14. As illustrated in FIG. 7, the control signal SP is set to a high level for a period of four pulses in the clock signal CKS by the signal pattern generation unit 13 if the transmission data is “11”, for example, the transmission data is “10”. If the transmission data is “01”, for example, if the transmission data is “01”, the transmission signal is set to the high level for two pulses in the clock signal CKS. For example, the transmission data is “00”. For example, the clock signal CKS is set to the high level for one pulse.

  Next, the AND circuit 14 outputs a signal pattern PP <b> 1 obtained by ANDing the transmission clock signal CKS and the control signal SP to the pulse signal generation unit 15. As a result, the signal pattern PP1 is synchronized with the transmission clock signal CKS, the pulse P11 is provided in the channel in which the synchronization pulse P2 is arranged, for example, the channel 1, and the channel in which the pulse P1 representing the data is arranged in the channel 2, for example 3 and 4 are provided with the number of pulses P12 corresponding to the transmission data.

  Next, a signal PP2 obtained by converting each pulse of the signal pattern PP1 into a pulse signal of 1 nsec, for example, is output to the bandpass filter 16 by the pulse signal generation unit 15, and the bandpass filter 16 band-limits the signal PP2 for transmission. The signal PP3 is radiated from the antenna 17. Thereby, transmission data representing the data pulse train 24 is radiated from the antenna 17 as a UWB communication signal.

  Next, the reception operation of the data pulse train 24 by the receiving apparatus 1 shown in FIG. 6 will be described. First, the data pulse train 24 radiated from the transmission antenna 17 of the transmission apparatus 11 is received by the antenna 2, amplified by the amplifier 3, and detected by the detector 4 by, for example, envelope detection or peak detection. Furthermore, the noise component in the high frequency band is removed from the signal detected by the detector 4 by the low-pass filter 5 and output to the data integrator 6 and the synchronization correction unit 8 as a data pulse train 24.

  The data pulse train 24 received by the synchronization correction unit 8 is integrated by the synchronization integrator 81 in the channel 1 where the synchronization pulse P2 is arranged in synchronization with the clock signal CK, and the progress integrator 82 supplies the clock signal. The channel 1 is integrated at a timing advanced by the pulse cycle T1 from the CK, and the channel 1 is integrated by the delay integrator 83 at a timing delayed by the pulse cycle T1 from the clock signal CK.

  Further, the synchronization timing detector 84 synchronizes the clock signal CK so that the integration timing of the integrator having the largest integration value among the synchronization integrator 81, the progress integrator 82, and the delay integrator 83 is synchronized with the clock signal CK. And the clock signal CK having the adjusted timing is output to the data integrator 6 and the integrated value determination unit 7.

  In this case, since the synchronization pulse P2 is provided for each pulse section T2 in the data pulse train 24, the pulse synchronization timing can be corrected while receiving the data pulse train 24. Thereby, for example, the frequency of the transmission clock signal CKS generated by the transmission clock generation unit 12 of the transmission device 11 and the frequency of the clock signal CK in the reception device 1 are, for example, an accuracy error of the crystal oscillator that generates these clock signals. Even if it is slightly different due to the influence or the like, after the pulse synchronization is obtained based on the pulse synchronization pulse train 22 by a pulse synchronization circuit (not shown), the synchronization correction unit 8 further sets the pulse synchronization timing based on the data pulse train 24. Correction is made, and deviation of the pulse synchronization timing is reduced.

  On the other hand, FIG. 8 is an explanatory diagram for explaining operations of the data integrator 6 and the integrated value determination unit 7. In FIG. 8, the vertical axis indicates the signal level, the horizontal axis indicates time, and in the data pulse train 24, one vertical line corresponds to the pulse interval T2. The data pulse train 24 received by the data integrator 6 is a channel in which the pulse P1 is arranged by the data integrator 6 in synchronization with the clock signal CK for each pulse interval T2 in the bit interval T3, for example, channel 2 , 3 and 4 are integrated, and the integrated value SI is output to the integrated value determination unit 7. Then, the comparators 71, 72, 73 compare the integral value SI with the reference values Ref1, Ref2, Ref3.

  The data integrator 6 is not limited to a configuration that integrates only the channel on which the pulse P1 is arranged, and may be configured to integrate the bit interval T3 including the pulse P2.

  When the bit interval T3 integrated by the data integrator 6 represents binary data “11”, three pulses P1 are arranged in each pulse interval T2 as shown in FIG. 4B. Therefore, as shown in FIG. 8, the integration value SI exceeds the reference values Ref1, Ref2, Ref3, and the output signals CP1, CP2, CP3 of the comparators 71, 72, 73 become high level. Similarly, when the bit interval T3 integrated by the data integrator 6 represents binary data “10”, two pulses P1 are arranged in each pulse interval T2 as shown in FIG. 4C. Therefore, as shown in FIG. 8, the integrated value SI is smaller than that of the binary data “11”, exceeds the reference values Ref1, Ref2, and becomes equal to or less than the reference value Ref3. As a result, the output signals CP1, CP2 becomes high level, and the output signal CP3 of the comparator 73 becomes low level.

  When the bit interval T3 integrated by the data integrator 6 represents binary data “01”, one pulse P1 is arranged in each pulse interval T2 as shown in FIG. Therefore, as shown in FIG. 8, the integrated value SI decreases from the binary data “10”, exceeds the reference value Ref1, and becomes lower than the reference values Ref2, Ref3. As a result, the output signal CP1 of the comparator 71 becomes high level. The output signals CP2 and CP3 of the comparators 72 and 73 become low level. When the bit interval T3 integrated by the data integrator 6 represents binary data “00”, the pulse P1 is not arranged in each pulse interval T2 as shown in FIG. 4 (e). As shown in FIG. 8, the integral value SI is smaller than that of the binary data “01” and does not exceed any of the reference values Ref1, Ref2, Ref3. As a result, the output signals CP1, CP2, CP2 of the comparators 71, 72, 73 CP3 goes low.

  Next, the data determination unit 74 generates reception data RD for 2 bits based on the output signals CP1, CP2, CP3 of the comparators 71, 72, 73 and outputs them to the outside. Specifically, when the output signals CP1, CP2, CP3 of the comparators 71, 72, 73 are all at the high level, the reception data RD is “11”, and the output signals CP1, CP2 of the comparators 71, 72 are at the high level. When the output signal CP3 of the comparator 73 is low level, the reception data RD is “10”, and when the output signal CP1 of the comparator 71 is high level and the output signals CP2 and CP3 of the comparators 72 and 73 are low level, the reception data The RD is set to “01”, and the received data RD is set to “00” when the output signals CP1, CP2 and CP3 of the comparators 71, 72 and 73 are all at the low level.

  As a result, data of a plurality of bits can be received from the bit interval T3 in accordance with the number of pulses P1 included in the pulse interval T2, so that the communication speed can be increased.

(Second Embodiment)
Next, a receiving apparatus according to the second embodiment of the present invention will be described. FIG. 9 is a block diagram showing an example of the configuration of the receiving device 1a according to the second embodiment of the present invention. The receiving apparatus 1a shown in FIG. 9 differs from the receiving apparatus 1 shown in FIG. 6 in the following points. That is, in the receiving apparatus 1a shown in FIG. 9, the data integrator 6a includes integrators 61, 62, and 63, which are examples of a plurality of second integration circuits. The integrator 61 integrates the pulse P1 of the channel 4 for each pulse period T2 in the bit period T3. The integrator 62 integrates the pulse P1 of the channel 3 for each pulse period T2 in the bit period T3. The integrator 63 integrates the pulse P1 of the channel 2 for each pulse period T2 in the bit period T3.

  The comparators 71, 72, 73 in the integral value determination unit 7a, which is an example of the second integral value determination unit, are preset with the integral values SI1, SI2, SI3 output from the integrators 61, 62, 63, respectively. Compared with the reference value Ref4, output signals CP1, CP2 and CP3 indicating the comparison result are output to the data determination unit 74a.

  FIG. 10 is a waveform diagram showing an example of the configuration of the data pulse train 24a received by the receiving device 1a shown in FIG. 10A shows the channel number and the clock signal CK, and FIGS. 10B to 10I show the 3-bit binary data “111”, “110”, “101”, “100”, “011”. , “010”, “001”, “000”, a data pulse train 24a is shown. In the data pulse train 24a shown in FIG. 10, the synchronization pulse P2 is indicated by a thin line, and the pulse P1 representing data is indicated by a thick line. In the data pulse train 24a shown in FIG. 10, the channel in which the pulse P1 representing data in the pulse section T2 is arranged, for example, each channel of channels 2, 3, and 4, corresponds to one digit of binary data. As shown in FIG. 10C, in the pulse period T2 of the bit period T3 representing the binary data “110”, for example, the channels 2 and 3 include the pulse P1, and the channel 4 does not include the pulse P1. Similarly, for example, the pulse period T2 of the bit period T3 representing the binary data “101” includes the pulse P1 in the channels 2 and 4 and does not include the pulse P1 in the channel 3 as illustrated in FIG.

  Similarly to the data pulse train 24 shown in FIG. 4, a synchronization pulse P2 for synchronizing the pulse position is arranged in a predetermined channel of the pulse interval T2 in the data pulse train 24a, for example, channel 1. .

  Since the other configuration is the same as that of the receiving apparatus 1 shown in FIG. 6, the description thereof will be omitted, and the receiving operation of the data pulse train 24a by the receiving apparatus 1a will be described below. First, similarly to the receiver 1 shown in FIG. 6, the data pulse train 24 a received by the antenna 2 is output to the data integrator 6 a and the synchronization correction unit 8, and the pulse synchronization timing is corrected by the synchronization correction unit 8. Is done.

  FIG. 11 is an explanatory diagram for explaining the operations of the integrators 61, 62, 63 and the integral value determination unit 7a. In FIG. 11, the vertical axis indicates the signal level, the horizontal axis indicates time, and one vertical line in the data pulse train 24a corresponds to the pulse interval T2. In the data pulse train 24a received by the integrators 61, 62, and 63, the pulse P1 of the channel 4 is integrated by the integrator 61 and the pulse P1 of the channel 3 is integrated by the integrator 62 for each pulse period T2 in the bit period T3. Integration is performed, and the pulse P1 of the channel 2 is integrated by the integrator 63, and the integration values are output to the comparators 71, 72, 73 as integration values SI1, SI2, SI3, respectively.

  Next, the integrated values SI1, SI2, and SI3 are compared with the reference value Ref4 by the comparators 71, 72, and 73. The reference value Ref4 is, for example, ½ of the maximum value of the integral values SI1, SI2, and SI3 in order to determine the presence or absence of the pulse P1 in each channel.

  When the bit section T3 represents 3-bit binary data “111”, the pulse P1 is arranged in the channels 2, 3 and 4 in each pulse section T2 as shown in FIG. 10B. As shown in FIG. 11, the integration values SI1, SI2, SI3 exceed the reference value Ref4, and the output signals CP1, CP2, CP3 of the comparators 71, 72, 73 all become high level. Further, when the bit section T3 represents 3-bit binary data “101”, the pulse P1 is arranged in the channels 2 and 4 in each pulse section T2 as shown in FIG. As shown in FIG. 11, the integration values SI1 and SI3 exceed the reference value Ref4, and the output signals CP1 and CP3 of the comparators 71 and 73 become high level.

  When the bit section T3 represents 3-bit binary data “011”, the pulse P1 is arranged in the channels 3 and 4 in each pulse section T2 as shown in FIG. As shown in FIG. 11, the integration values SI1 and SI2 exceed the reference value Ref4, and the output signals CP1 and CP2 of the comparators 71 and 72 become high level. Further, when the bit interval T3 represents 3-bit binary data “001”, the pulse P1 is arranged in the channel 4 in each pulse interval T2 as shown in FIG. As shown, the integral value SI1 exceeds the reference value Ref4, and the output signal CP1 of the comparator 71 becomes high level.

  Next, based on the output signals CP1, CP2, and CP3 of the comparators 71, 72, and 73, the data determination unit 74 generates reception data RD for 3 bits and outputs it to the outside. Specifically, the high / low of the output signals CP1, CP2 and CP3 correspond to 1/0 of 1 bit, respectively. For example, if the output signals CP1, CP2 and CP3 are high, low and high, the received data RD Is output as “101”.

  As a result, a plurality of bits of data can be received from the bit interval T3 according to the arrangement pattern of the pulse P1 in the pulse interval T2, and the number of channels provided in the pulse interval T2 is the same as shown in FIG. Since the number of bits that can be acquired from the bit section T3 can be increased as compared with the receiving apparatus 1, the communication speed can be increased.

(Third embodiment)
Next, a receiving apparatus according to the third embodiment of the present invention will be described. FIG. 12 is a block diagram showing an example of the configuration of the receiving device 1b according to the third embodiment of the present invention. The receiving apparatus 1b shown in FIG. 12 and the receiving apparatus 1 shown in FIG. 6 differ in the configuration of the data pulse train 24b used for communication.

  FIG. 13 is a timing chart showing an example of the configuration of the data pulse train 24b received by the receiving device 1b shown in FIG. FIG. 13A shows the channel number and the clock signal CK. In the pulse synchronization pulse train 22a shown in FIG. 13B, the synchronization pulse P2 is provided in the channel 1 in each pulse section T2, and the pulses are not provided in the other channels 2, 3 and 4.

  FIG. 13C is a waveform diagram showing an example of a data pulse train 24b indicating data “1”, and includes a predetermined channel, for example, channel 1 with a synchronization pulse P2 and channel 2 with a pulse P1. FIG. 13D is a waveform diagram showing an example of a data pulse train 24b indicating data “0”. The synchronization pulse P2 is provided in the same channel as that indicating data “1”, for example, channel 1, and the pulse P1 Is provided in a channel different from that indicating data “1”, for example, channel 4.

  In the receiving apparatus 1b shown in FIG. 12, the data integrator 6b includes integrators 61 and 62. The integrator 61 integrates the pulse P1 of the channel 2 for each pulse interval T2 in the bit interval T3, and outputs the integration value SI1 to the comparator 71. The integrator 62 integrates the pulse P1 of the channel 4 for each pulse interval T2 in the bit interval T3, and outputs the integration value SI2 to the comparator 72. Then, the comparators 71 and 72 in the integral value determination unit 7b compare the integral values SI1 and SI2 output from the integrators 61 and 62 with a preset reference value Ref4, respectively, and output signals CP1 and CP2 indicating the comparison results. CP2 is output to the data determination unit 74b. In this case, the data integrator 6b and the comparators 71 and 72 correspond to an example of the pulse detection unit, the integrators 61 and 62 correspond to an example of the third and fourth integration circuits, and the comparators 71 and 72 correspond to the first detector. This corresponds to an example of the presence / absence determination unit.

  The data determination unit 74b acquires 1-bit data from the bit interval T3 based on the output signals CP1 and CP2 from the comparators 71 and 72, and outputs the data as reception data RD to the outside. Furthermore, the receiving device 1b illustrated in FIG. 12 includes a failure determination unit 9 that detects a failure of the receiving device 1b based on the output signals CP1 and CP2 from the comparators 71 and 72.

  Since the other configuration is the same as that of the receiving apparatus 1 shown in FIG. 6, the description thereof will be omitted, and the operation of the present embodiment will be described below. FIG. 14 is a timing chart for explaining the operation when the transmission apparatus 11 shown in FIG. 5 transmits the data pulse train 24b shown in FIGS. 13 (c) and 13 (d). First, the transmission clock generator 12 outputs the clock signal CKS to the AND circuit 14 at a cycle of the pulse cycle T1. Next, transmission data to be transmitted is received by the signal pattern generation unit 13.

  Then, the signal pattern generation unit 13 outputs a control signal SP for converting the transmission data into a pulse signal pattern in the data pulse train 24 bit by bit to the AND circuit 14. As shown in FIG. 14, the control signal SP is sent from the signal pattern generation unit 13 to the channel 1 to arrange the synchronization pulse P2 on the channel 1 and the pulse P1 on the channel 2 if the transmission data is “1”, for example. , 2 at a high level. On the other hand, for example, if the transmission data is “0”, the control signal SP is sent by the signal pattern generation unit 13 at the timing of channels 1 and 4 so as to arrange the synchronization pulse P2 on channel 1 and the pulse P1 on channel 4. High level.

  Next, the AND circuit 14 outputs a signal pattern PP <b> 1 obtained by ANDing the transmission clock signal CKS and the control signal SP to the pulse signal generation unit 15. As a result, the signal pattern PP1 is synchronized with the transmission clock signal CKS, the pulse P11 is provided in the channel in which the synchronization pulse P2 is arranged, for example, the channel 1, and if the data is “1”, the signal pattern PP1 is in the channel 2. If the data is “0”, a pulse P12 is provided in the channel 4 to arrange the pulse P1.

  Next, a signal PP2 obtained by converting each pulse of the signal pattern PP1 into a pulse signal of 1 nsec, for example, is output to the bandpass filter 16 by the pulse signal generation unit 15, and the bandpass filter 16 band-limits the signal PP2 for transmission. The signal PP3 is radiated from the antenna 17. Thus, transmission data representing the data pulse train 24b is radiated from the antenna 17 as a UWB communication signal.

  Next, the receiving operation of the data pulse train 24b by the receiving device 1b shown in FIG. 12 will be described. First, similarly to the receiver 1 shown in FIG. 6, the data pulse train 24 b received by the antenna 2 is output to the data integrator 6 b and the synchronization correction unit 8, and the pulse synchronization timing is corrected by the synchronization correction unit 8. Is done.

  FIG. 15 is an explanatory diagram for explaining the operations of the integrators 61 and 62 and the integrated value determination unit 7b in the data integrator 6b. In FIG. 15, the vertical axis indicates the signal level, the horizontal axis indicates time, and one vertical line in the data pulse train 24b corresponds to the pulse interval T2. In the data pulse train 24b, the pulse P1 of the channel 2 is integrated by the integrator 61 and the pulse P1 of the channel 4 is integrated by the integrator 62 for each pulse period T2 in the bit period T3. It is output to the comparators 71 and 72 as SI1 and SI2.

  Next, the comparators 71 and 72 compare the integration values SI1 and SI2 with the reference value Ref4. The reference value Ref4 is set, for example, to ½ of the maximum value of the integral values SI1 and SI2 in order to determine the presence or absence of the pulse P1 in each channel.

  When the bit interval T3 represents data “1”, the pulse P1 is arranged in the channel 2 in each pulse interval T2 as shown in FIG. 13C, so that the integration as shown in FIG. The value SI1 exceeds the reference value Ref4, and the integral value SI2 is equal to or less than the reference value Ref4. Then, the output signal CP1 of the comparator 71 becomes high level, while the output signal CP2 of the comparator 72 becomes low level.

  On the other hand, when the bit interval T3 represents data “0”, since the pulse P1 is arranged in the channel 4 in each pulse interval T2 as shown in FIG. 13 (d), the integration as shown in FIG. The value SI1 is less than or equal to the reference value Ref4, and the integral value SI2 exceeds the reference value Ref4. Then, the output signal CP1 of the comparator 71 becomes low level, while the output signal CP2 of the comparator 72 becomes high level.

  As described above, if the data integrator 6b and the comparators 71 and 72 are operating normally, both the output signals CP1 and CP2 are at a high level regardless of whether the received data is “1” or “0”. Or it is made not to become a low level.

  Next, based on the output signals CP1 and CP2 of the comparators 71 and 72, the data determination unit 74b generates 1-bit reception data RD and outputs it to the outside. Specifically, when the signal levels of the output signals CP1 and CP2 are high and low by the data determination unit 74b, the reception data RD is output as “1”, and the signal levels of the output signals CP1 and CP2 are low and high. In this case, the reception data RD is output as “0”. Note that the data determination unit 74b may be configured to generate the reception data RD for one bit using, for example, one of the output signals CP1 and CP2.

  In addition, when the failure determination unit 9 receives the output signals CP1 and CP2 of the comparators 71 and 72, the signal levels of the output signals CP1 and CP2 are both low, or the signal levels of the output signals CP1 and CP2 are both high. For example, it is determined that a failure has occurred in the receiving device 1b such as the data integrator 6b and the comparators 71 and 72, and a failure notification signal indicating the occurrence of the failure is output from the failure determination unit 9 to the outside.

  Thereby, since the failure of the receiver 1b can be detected, the reliability of communication can be improved.

  For example, when the integrators 61 and 62 and the comparators 71 and 72 fail, it is considered that the signal levels of the output signals CP1 and CP2 are likely to be fixed to high or low. For example, when the integrator 61 fails and the integration value SI1 is fixed at a high level or a low level, the output signal CP1 of the comparator 71 is fixed at a high level or a low level. For example, when the comparator 72 fails, there is a high possibility that the signal level of the output signal CP2 is fixed to a high level or a low level.

  Therefore, the failure determination unit 9 monitors the output signals CP1 and CP2 for a predetermined time set in advance, for example, a plurality of pulse sections T2 or a period of the bit section T3, and the output signals CP1 and CP2 within the monitoring period. When it is detected that one of the signal levels is fixed to high or low, it is desirable to output a failure signal notification signal indicating an output signal whose signal level is fixed to the data determination unit 74b.

  When the data determination unit 74b receives the failure signal notification signal from the failure determination unit 9, the data determination unit 74b uses an output signal different from the output signal indicated by the failure signal notification signal among the output signals CP1 and CP2 for 1 bit. The reception data RD may be generated. Specifically, when receiving a failure signal notification signal indicating that the signal level of the output signal CP1 is fixed, for example, the data determination unit 74b receives the received data based on the low and high signal levels in the output signal CP2. For example, when a failure signal notification signal indicating that the signal level of the output signal CP2 is fixed is received by setting RD to “1” and “0”, the received data is based on the high and low signal levels in the output signal CP1. The RD may be output as “1” and “0”.

  In this case, the channel in which the pulse P1 is arranged to represent the data “1”, for example, the integrator 61 and the comparator 71 that generate the output signal CP1 from the channel 2, and the channel in which the pulse P1 is arranged to represent the data “0”. For example, when one of the integrator 62 and the comparator 72 that generates the output signal CP2 from the channel 4 fails, the data determination unit 74b receives the error from the other normal integrator and comparator. Since the reception data RD can be generated based on the output signal, the reliability of communication can be improved.

  16, for example, the data integrator 6c is configured using one integrator 61, and the integrator 61 is the first half of the bit interval T3 as illustrated in FIG. 17. The pulse P1 is integrated for the channel in which the pulse P1 is arranged to represent the data “1” for the period T31, for example, the channel 2 and the pulse P1 is arranged to represent the data “0” for the period T32 which is the second half of the bit period T3. For example, the pulse P1 may be integrated with respect to a channel, for example, the channel 4, and the integration value may be sequentially output as the integration value SI1. In this case, the integrator 61 corresponds to an example of a fifth integration circuit, and the comparator 71 corresponds to an example of a second presence / absence determination unit.

  Then, the data determination unit 74c and the failure determination unit 9a use the output signal CP1 of the comparator 71 in the period T31 as the output signal CP1 in the receiving device 1b shown in FIG. 12, and the output signal CP1 of the comparator 71 in the period T32 in FIG. By using it as the output signal CP2 in the receiving device 1b shown, it functions in the same manner as the data judging unit 74b and the failure judging unit 9 shown in FIG.

  As a result, the integrating circuit 62 is not required, so that the circuit can be simplified as compared with the receiving apparatus 1b shown in FIG.

It is a figure which shows an example of the communication frame used for the communication method which concerns on one Embodiment of this invention. It is a wave form diagram which shows an example of the detail of the pulse train for pulse synchronization shown in FIG. FIG. 2 is a waveform diagram showing an example of details of a bit synchronization pulse train shown in FIG. 1. (A) is a wave form diagram which shows a channel number and the clock signal CK, (b)-(e) is a wave form diagram which shows an example of a structure of the pulse train for data shown in FIG. FIG. 5 is a block diagram illustrating an example of a transmission device that transmits the data pulse train illustrated in FIG. 4. It is a block diagram which shows an example of the receiver which concerns on the 1st Embodiment of this invention. 6 is a timing chart for explaining the operation of the transmission apparatus shown in FIG. 5. It is explanatory drawing for demonstrating operation | movement of the integrator for data shown in FIG. 6, and an integral value determination part. It is a block diagram which shows an example of a structure of the receiver which concerns on the 2nd Embodiment of this invention. FIG. 10 is a waveform diagram illustrating an example of a configuration of a data pulse train received by the receiving device illustrated in FIG. 9. (A) shows a channel number and a clock signal CK, and (b) to (i) show a data pulse train. It is explanatory drawing for demonstrating operation | movement of the integrator and integral value determination part which are shown in FIG. It is a block diagram which shows an example of a structure of the receiver which concerns on the 3rd Embodiment of this invention. 13 is a timing chart illustrating an example of a configuration of a data pulse train received by the receiving device illustrated in FIG. 12. It is a timing chart for demonstrating operation | movement when the transmitter 11 shown in FIG. 5 transmits the pulse train for data shown in FIG. It is explanatory drawing for demonstrating operation | movement of the integrator in the data integrator shown in FIG. 12, and an integral value determination part. It is a block diagram which shows the modification of the receiver shown in FIG. FIG. 17 is an explanatory diagram for explaining an operation of the reception device illustrated in FIG. 16. It is a block diagram which shows the receiver which concerns on background art.

Explanation of symbols

1, 1a, 1b, 1c Receiver 3 Amplifier 4 Detector 5 Low-pass filter 6, 6a, 6b, 6c Data integrator 7, 7a, 7b Integration value determination unit 8 Synchronization correction unit 9, 9a Failure determination unit 11 Transmission device 12 Transmission clock generation unit 13 Signal pattern generation unit 14 AND circuit 15 Pulse signal generation unit 16 Band pass filter 17 Transmission antenna 21 Communication frame 22, 22a Pulse synchronization pulse train 23 Bit synchronization pulse train 24, 24a, 24b For data Pulse train 61, 62, 63 Integrator 71, 72, 73 Comparator 74, 74a, 74b, 74c Data determination unit 81 Synchronization integrator 82 Progression integrator 83 Delay integrator 84 Synchronization timing detection unit CK Clock signal CKS Transmission clock signal P1 Pulse P2 Synchronization pulse SI, SI1, SI2, SI3 Integral value T1 Pulse period T2 Pulse period T3 Bit period

Claims (3)

A pulse train for data representing data by a pulse train modulated by an on-off keying method is provided, and the pulse train for data subdivides a pulse section, which is a time given to a signal pattern as a unit representing data, into a plurality of time slots. A channel is assigned to each time slot, and the signal pattern represents bit data “0” by having a pulse in the first channel in the pulse interval, and is different from the first channel in the pulse interval. A receiving device for receiving a communication frame representing bit data “1” by having a pulse in two channels;
A receiving unit for receiving the communication frame;
A pulse detector for detecting the presence or absence of pulses in the first and second channels in the pulse interval in the data pulse train of the communication frame received by the receiver;
A data acquisition unit for acquiring 1-bit data from the pulse interval based on the presence or absence of pulses in the first and second channels detected from the pulse interval by the pulse detection unit;
A failure determination unit that determines that a failure has occurred when a pulse is detected by both of the first and second channels in the pulse interval by the pulse detection unit;
A receiving apparatus comprising: The pulse detector
A third integrating circuit for integrating the first channel in the pulse interval;
A fourth integrating circuit for integrating the second channel in the pulse interval;
When the integration value by the third integration circuit exceeds a preset threshold value, it is determined that there is a pulse in the first channel, and the integration value by the fourth integration circuit exceeds a preset threshold value A first presence / absence determination unit that determines that there is a pulse in the second channel,
The receiving apparatus according to claim 1, further comprising: The pulse detector
A fifth integrating circuit that sequentially integrates the first channel and the second channel in the pulse period;
When the integration value of the first channel by the fifth integration circuit exceeds a preset threshold value, it is determined that there is a pulse in the first channel, and the second channel by the fifth integration circuit is determined. A second presence / absence determining unit that determines that there is a pulse in the second channel when the integral value of the second channel exceeds a preset threshold;
The receiving apparatus according to claim 1, further comprising:

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