JP4345613B2 - COMMUNICATION METHOD, PULSE SYNCHRONIZATION CIRCUIT, RECEPTION DEVICE - Google Patents

Description

  The present invention relates to a communication method for ultra-wideband communication. And it is related with the receiver which utilizes such a communication method, and a pulse synchronization circuit.

  In recent years, attention has been paid to an ultra wide band (UWB) communication system that performs ultra-wideband communication using a pulse signal sequence composed of pulse signals synchronized with a predetermined cycle timing as one of high-speed wireless transmission systems. Yes. In one aspect of UWB communication, communication is performed using a pulse signal sequence made up of extremely fine pulse signals having a pulse width of 1 nsec or less, for example, without using a carrier wave. As a modulation method used in such UWB communication, a pulse position modulation (PPM) that expresses “0” and “1” information using a signal in which the pulse generation timing is slightly shifted back and forth is used. It is known (for example, refer to Patent Document 1). In addition, as another modulation method, on-off keying (OOK) expressing “1” and “0” information depending on the presence / absence of a pulse signal, and “0” and “1” information according to a change in pulse phase. Bi-phase modulation that expresses the above is known.

  FIG. 16 is a block diagram showing a UWB communication receiving apparatus 101 according to the background art. FIG. 17 is a signal waveform diagram for explaining the operation of the receiving apparatus 101 shown in FIG. The receiving apparatus 101 shown in FIG. 16 includes an antenna 102 that receives a UWB communication signal transmitted from a transmitting apparatus using UWB communication, and the same known PN used by the transmitting apparatus to generate a UWB communication signal. A decoder source 103 that generates a decoding control signal corresponding to a (Pseudorandom Noise) code, and an adjustable time for generating a periodic timing signal including a pulse train of a template signal 110 having a waveform substantially equivalent to each pulse of the received signal. A base 104; a decode time modulator 105 that generates a decode signal that temporally matches a known PN code of the transmission device based on the decode control signal and the periodic timing signal; and a reception signal 111 and a decode signal received by the antenna 102 A cross-correlator 106 that generates a correlation voltage 112 by taking a correlation with It includes a low-pass filter 107 is fed back to the adjustable time base 104 a correlation voltage 112, and a sub-carrier demodulator 108 to recover the received data to remove subcarrier from the correlation voltage 112.

Then, the cross-correlator 106 obtains a correlation between the received signal 111 received by the antenna 102 and the decoded signal temporally matched with the known PN code of the transmitting apparatus, and based on the correlation value. Pulse synchronization is performed to synchronize the receiving apparatus 101 at a timing at which a reception target pulse signal included in the reception signal 111 can be acquired, so that the reception signal 111 can be demodulated.
Japanese National Patent Publication No. 10-508725

  By the way, in the receiving apparatus 101 as described above, in order to demodulate the received signal 111, a correlation is obtained between the pulse signal of the received signal 111 and the decoded signal generated from the PN code, thereby receiving the received signal 111. Since the target pulse signal is recognized and pulse synchronization is established, a PN code is required to achieve pulse synchronization, and the circuit scale of the decoder source 103 that generates the PN code increases. It was. In addition, due to the accuracy error of the clock signal that generates the timing on the transmitter side and the receiver side, the timing between the received signal and the decoded signal will shift as time passes, resulting in loss of pulse synchronization. There was a disadvantage that it was difficult to restore the signal.

  The present invention is an invention made in view of such problems, and provides a receiving device, a pulse synchronization circuit, and a communication method used therefor that can maintain a pulse synchronization state with a simple circuit. The purpose is to do.

  In order to achieve the above object, a communication method according to a first means of the present invention is a communication method for performing communication using a pulse train modulated by an on-off keying method, and synchronizes pulse positions in the pulse train. Data is transmitted and received using a communication frame including a pulse synchronization pulse train for obtaining data and a data pulse train representing data, and the data pulse train is synchronized with the pulse position at predetermined intervals. It is characterized by comprising a synchronization correction pulse train for correcting the above.

  In the communication method described above, the synchronization correction pulse train is determined in advance among channels assigned to each time slot obtained by subdividing a pulse interval, which is a time given for each pulse, into a plurality of time slots. It is characterized in that it is provided with a pulse in a given channel.

  A pulse synchronization circuit according to the second means of the present invention includes a pulse synchronization pulse train for synchronizing with a pulse in a pulse train modulated by an on-off keying method, and a data pulse train representing data, the data The pulse train includes a synchronization correction pulse train for correcting synchronization with the pulse at predetermined intervals, and the synchronization correction pulse train is a pulse interval that is a time given for each pulse. A pulse synchronization circuit that receives a communication frame having a pulse in a predetermined designated channel among the channels assigned to each time slot divided into a plurality of time slots and performs pulse synchronization, The synchronization correction pulse train is a period that corresponds to the designated channel and a progress that has advanced the standard period And an integration circuit for integrating the delay period obtained by delaying the standard period, and when the integration value for the standard period by the integration circuit is the maximum, the timing of the pulse synchronization is maintained and the progress is performed. The pulse synchronization timing is advanced by advancing the pulse synchronization timing when the integral value for the period is maximum, and the pulse synchronization timing is delayed when the integral value for the delay period is maximum. And a synchronization timing correction unit for correcting.

  The pulse synchronization circuit further includes an integration value storage unit that stores an integration value obtained by the integration circuit, and the integration circuit includes the synchronization correction pulse train, the standard period, the progress period, and the delay period. For each of the above, the integration is performed sequentially and the integration value is stored in the integration value storage unit.The synchronization timing correction unit is based on the integration value for each period stored in the integration value storage unit, The correction is performed.

  In the above-described pulse synchronization circuit, the integration circuit includes a standard integration circuit that integrates the synchronization correction pulse train for the standard period, a progress integration circuit that integrates the synchronization correction pulse train for the progress period, and A delay integration circuit that integrates the synchronization correction pulse train for the delay period, and the synchronization timing correction unit integrates an integration value for the standard period by the standard integration circuit and an integration for the progress period by the progress integration circuit. The correction is performed based on the value and the integration value for the delay period by the delay integration circuit.

  In the above-described pulse synchronization circuit, the synchronization timing correction unit is configured to perform the pulse synchronization based on the integral value for the standard period, the integral value for the progression period, and the integral value for the delay period. It is characterized in that the correction amount for correcting the timing is changed.

  Further, in the above-described pulse synchronization circuit, the synchronization timing correction unit performs the correction using a part of the synchronization correction pulse train, and then the other pulses of the synchronization correction pulse train are the standard after the correction. A timing located at the center position in the period is searched, and the pulse synchronization timing is further corrected based on the searched timing.

  The receiving apparatus according to the third means of the present invention provides a pulse synchronization between a receiving unit that receives a communication signal using a pulse train modulated by an on-off keying method and a communication signal received by the receiving unit. And a data restoration unit that restores data from the communication signal received by the reception unit based on pulse synchronization by the pulse synchronization circuit, and the pulse synchronization circuit includes the pulse synchronization circuit described above It is characterized by being.

  The communication method having such a configuration uses a communication frame including a synchronization correction pulse train for correcting synchronization of pulse positions at predetermined intervals in a data pulse train representing data. In addition, it is easy to maintain the state in which the image is removed, and the circuit for obtaining pulse synchronization can be simplified.

  The pulse synchronization circuit and the receiving device having such a configuration include a communication frame including a synchronization correction pulse train for correcting synchronization of pulse positions at predetermined intervals in a data pulse train representing data. Are integrated by the integration circuit for the standard period, the progress period, and the delay period, respectively, and when the integral value for the standard period is maximum by the synchronization timing correction unit, the pulse synchronization timing is maintained, and the progress period is When the integral value is the maximum, the pulse synchronization timing is advanced, and when the integral value for the delay period is the maximum, the pulse synchronization timing is delayed, so the pulse synchronization can be achieved with a simple circuit. The state can be maintained.

  Embodiments according to the present invention will be described below with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted.

(First embodiment)
FIG. 1 is a diagram illustrating an example of a communication frame used in a communication method according to an embodiment of the present invention. A communication frame P1 shown in FIG. 1 is modulated by an on / off keying method, and a pulse synchronization pulse train P2 for synchronizing pulse positions in the communication frame P1 and a bit position in communication frame P1 after pulse synchronization are synchronized. A bit synchronization pulse train P3 for data and a data pulse train P4 representing data.

  FIG. 2 is a diagram illustrating an example of a section configuration of the data pulse train P4. In the data pulse train P4 shown in FIG. 2, a data section P5 which is a portion representing data, and a synchronization section P6 corresponding to an example of a synchronization correction pulse train for correcting the synchronization of the pulse position so as to maintain the pulse synchronization state, Are alternately arranged at regular intervals.

  FIG. 3 is a diagram showing an example of a pulse arrangement in the data section P5 shown in FIG. A data section P5 shown in FIG. 3 is a minimum interval between pulses and is divided into a pulse section P51 which is a fixed time given for each pulse, and a plurality of pulse sections P51, for example, 127 pulses. A 1-bit section P52 representing 1-bit data is configured by the section P51. Further, each pulse section P51 is divided into a plurality of time slots, for example, n time slots, and channels 1, 2, 3,..., N are assigned to the respective time slots.

  When a pulse is arranged in a predetermined channel, for example, channel 1 by modulation by the on / off keying method, and the 1-bit section P52 indicates “1”, the pulse section P51 included in the 1-bit section P52. When there is a pulse in channel 1 and the 1-bit section P52 indicates “0”, there is no pulse in the pulse section P51 included in the 1-bit section P52.

  FIG. 4 is a diagram illustrating an example of a pulse arrangement in the synchronization period P6 illustrated in FIG. A synchronization interval P6 shown in FIG. 4 is a minimum interval between pulses, and is divided into a pulse interval P51, which is a fixed time given for each pulse, and a plurality of pulse intervals P51, for example, 99 pulse intervals. A synchronization section P6 is configured by P51. Further, each pulse section P51 is subdivided into a plurality of time slots, for example, n sections, and channels 1, 2, 3,..., N are assigned to the respective time slots.

  Each pulse section P51 in the synchronization section P6 has a pulse in a predetermined channel, for example, channel 1. The period of the pulse interval P51 is determined according to the degree of reliability required for communication. For example, the pulse interval P51 is 100 nsec (nanosecond), the time of one channel is 10 nsec (nanosecond), and the number of channels n May be 10. In this case, for example, assuming that the accuracy of an oscillator for generating a reception timing in the receiving apparatus 2 described later is 40 ppm, in order to maintain the deviation of the pulse synchronization timing to ½ or less of one channel, in the data pulse train P4 The data section P5 is preferably set to 125 μsec or less, and the synchronization section P6 is preferably arranged at an interval of 125 μsec or less.

  In the data section P5 and the synchronization section P6, the pulse is arranged in the channel 1 of the pulse section P51. However, the pulse may be arranged in a channel other than the channel 1, A configuration may be employed in which pulses are arranged in different channels in the data interval P5 and the synchronization interval P6.

  FIG. 5 is a block diagram illustrating an example of a transmission apparatus that transmits the communication frame P1 as described above. 5 includes a data generator 11 that generates transmission data, a pulse generator 12 that generates a pulse based on the transmission data generated by the data generator 11, and generates a communication frame P1, A band pass filter (BPF) 13 that limits the band of the pulse generated by the pulse generator 12 and a transmission antenna 14 that radiates a transmission pulse output from the band pass filter 13 are configured.

  FIG. 6 is a block diagram illustrating an example of a configuration of the receiving device 2 according to the first embodiment of the present invention and receiving devices 2b and 2c described later. The receiving apparatus 2 shown in FIG. 6 includes a receiving antenna 21 that is an example of a receiving unit, an amplifier 22 that amplifies the received signal, a detector 23 that detects the received signal, and a low-pass filter (LPF) that removes high-frequency noise. 24 and a pulse synchronization circuit 25. The pulse synchronization circuit 25 includes an integrator 201 (integration circuit), a timing control unit 202, a pulse position information storage unit 203, an AD converter 204 corresponding to an example of a data restoration unit, and an integration value storage unit 205. Yes.

  The integrator 201 integrates the signal output from the low-pass filter 24 in the integration interval corresponding to the control signal from the timing control unit 202, and outputs the integration signal SD to the timing control unit 202 and the AD converter 204. To do.

  The pulse position information storage unit 203 is a storage unit configured by, for example, a ROM (Read Only Memory), and in accordance with the format of the communication frame P1, the pulse synchronization pulse train P2, the bit synchronization pulse train P3, and the data pulse train P4 in the communication frame P1. , And position information indicating the positions of the data section P5 and the synchronization section P6 in the data pulse train P4 are stored in advance.

  The AD converter 204 converts the integrated signal output from the integrator 201 into a digital value, outputs the digital signal to the outside as a demodulated signal received by the receiving device 2, and outputs the digitally converted integrated value to the timing control unit 202. Is stored in the integrated value storage unit 205 configured by using, for example, a register in accordance with the control signal from.

  The timing control unit 202 includes, for example, a sequential circuit that controls a sequence operation for obtaining synchronization, a comparator for obtaining synchronization timing from an integration signal obtained from the integrator 201, and the like. A pulse synchronization control unit 206 that performs the bit synchronization, a bit synchronization control unit 207 that performs bit synchronization, and a pulse synchronization correction control unit 208 that is an example of a synchronization timing correction unit that corrects the timing of pulse synchronization are provided.

  Next, the operation of the receiving apparatus 2 configured as described above will be described. First, a signal radiated from the antenna 14 of the transmission apparatus 1, for example, the communication frame P1, is received by the antenna 21, amplified by the amplifier 22, and detected by the detector 23 by, for example, envelope detection or peak detection. Further, the signal detected by the detector 23 has a high-frequency band noise component removed by the low-pass filter 24 and is output to the integrator 201 in the pulse synchronization circuit 25.

  In the pulse synchronization circuit 25, a control signal for detecting the pulse synchronization pulse train P <b> 2 is output to the integrator 201 by the pulse synchronization control unit 206 in order to achieve pulse synchronization with the received signal, and the integrator 201 performs pulse synchronization control. The reception signal output from the low-pass filter 24 is integrated at a timing according to the control signal from the unit 206. Then, the integration signal SD is fed back to the pulse synchronization control unit 206, and the pulse synchronization control unit 206 detects the pulse synchronization pulse train P2 based on the integration signal SD. A pulse synchronization timing that is a timing for identifying a pulse to be obtained is acquired.

  The pulse synchronization timing is a timing at which a pulse is arranged by modulation by the on / off keying method in the data section P5, for example, a channel 1 timing. Then, the timing of the designated channel, for example, channel 1 in the synchronization period P6 is detected, and based on the detected timing, the pulse synchronization timing, that is, the time of channel 1 is set as the integration period of the integrator 201, whereby the pulse Synchronization is taken.

  Next, based on the pulse synchronization timing synchronized by the pulse synchronization control unit 206, the bit synchronization control unit 207 outputs a control signal for detecting the bit synchronization pulse train P <b> 3 to the integrator 201. The reception signal output from the low-pass filter 24 is integrated at a timing according to the control signal from the bit synchronization control unit 207. Then, the integration signal SD is fed back to the bit synchronization control unit 207, and the bit synchronization control unit 207 detects the bit synchronization pulse train P3 based on the integration signal SD. The timing of the bit period P52 is acquired, and bit synchronization is ensured.

  Next, the following operation is performed by the pulse synchronization correction control unit 208 to restore data and correct the pulse synchronization timing based on the data pulse train P4. FIG. 7 is an explanatory diagram for explaining an example of the integration signal SD output from the integrator 201 when the data pulse train P4 is received. In FIG. 7, with respect to the data section P5, the waveform A indicates that the integrated signal SD exceeds a certain threshold value by “H”, and the integrated signal SD does not satisfy the certain threshold value by “L”. In the section P6, the voltage waveform of the integration signal SD is shown. In FIG. 7, the data section P5 represents the bit data “1” when the waveform A changes from L to H in the bit section P52 by treating the integration signal SD as a Manchester code, and in the bit section P52. An example is shown in which the bit data “0” is represented when the waveform A changes from H to L. The data section P5 does not use the Manchester code, and represents other bit data “0” when the waveform A is L, for example, and bit data “1” when the waveform A is H. It may represent data.

  First, the pulse synchronization correction control unit 208 reads the position information of the data section P5 and the synchronization section P6 from the pulse position information storage unit 203. When the pulse synchronization correction control unit 208 detects the data section P5 based on the position information, the pulse synchronization timing acquired by the pulse synchronization control unit 206 and the bit synchronization timing acquired by the bit synchronization control unit 207 Is output to the integrator 201. The integrator 201 integrates the received signal output from the low-pass filter 24 and outputs the integrated signal to the AD converter 204. The AD converter 204 converts the received signal to a digital value. A demodulated signal that has been converted and whose data has been restored is output to the outside.

  In this case, first, when the bit section P52 indicates “1”, for example, channel 1 is integrated during the period of the bit section P52 by the AD converter 204 in accordance with the control signal from the pulse synchronization correction control unit 208. Since the integration signal SD rises from the waveform A in the L state and exceeds a predetermined threshold value set in advance, the waveform A changes to the H state, so that “1” is detected from the bit interval P52. On the other hand, when the bit period P52 indicates “0”, the integration signal is obtained by integrating, for example, channel 1 during the period of the bit period P52 by the AD converter 204 in accordance with the control signal from the pulse synchronization correction control unit 208. When SD decreases and falls below a predetermined threshold value set in advance, the waveform A changes from H to L, and “0” is detected from the bit interval P52.

  Further, since bit information “0” and “1” can be acquired from the bit section P52 in this way, an RN code generation circuit is not required, and the circuit of the receiving device 2 can be simplified.

  FIG. 8 is a flowchart for explaining the pulse synchronization correction processing at the timing position of the synchronization section P6. First, in step S1, when the pulse synchronization correction control unit 208 detects that the synchronization interval P6 has been entered based on the position information of the synchronization interval P6 read from the pulse position information storage unit 203 (step S1). YES), the pulse synchronization correction control unit 208 sets the integration timing of the integrator 201 (step S2).

  Specifically, first, the pulse synchronization correction control unit 208 calculates a progress period E obtained by advancing the standard period P that is a period corresponding to the designated channel, for example, channel 1 by, for example, half the standard period P. It is set as the integration period of the vessel 201. In this case, the standard period P corresponds to the current pulse synchronization timing, and the progress period E corresponds to a time advanced by ½ time of one channel from the current pulse synchronization timing.

  Then, the integrator 201 integrates the received signal for a predetermined period, for example, a period of 1/3 of the synchronization period P6, and the progress period E, and the integration signal SD is AD-converted by the AD converter 204 to obtain an integration. The value is stored in the integral value storage unit 205 as an integral value for the progress period E (step S3).

  Next, the process proceeds again to step S <b> 2 (NO in step S <b> 4), and the standard period P is set as the integration period of the integrator 201 by the pulse synchronization correction control unit 208. Then, the integrator 201 integrates the received signal for a standard period P, for example, a period of 1/3 of the synchronization period P6, and the integrated value obtained by AD conversion of the integrated signal SD by the AD converter 204 is a standard value. The integral value for the period P is stored in the integral value storage unit 205 (step S3).

  Next, the process proceeds to step S2 again (NO in step S4), and the pulse synchronization correction control unit 208 causes the pulse synchronization correction control unit 208 to set a standard period P that is a period corresponding to the designated channel, for example, channel 1, for example A delay period L that is delayed by a half of the standard period P is set as the integration period of the integrator 201. Then, for example, the integrator 201 integrates the received signal for the delay period L for a period of 1/3 of the synchronization period P6, and the integrated value obtained by AD conversion of the integrated signal SD by the AD converter 204 is a delay. The integral value for the period L is stored in the integral value storage unit 205 (step S3).

  Next, since the integral values for the standard period P, the progress period E, and the delay period L are stored in the integral value storage unit 205, the process proceeds to step S5 (YES in step S4), and the pulse synchronization correction control unit 208 performs integration. The integrated values for the standard period P, the progress period E, and the delay period L are read from the value storage unit 205, and the maximum value is determined (step S5).

  In this case, it is considered that the timing at which the integral value is maximized among the standard period P, the progress period E, and the delay period L is the current pulse position. Therefore, in order to match the pulse synchronization timing with the maximum timing, The following processing is executed by the pulse synchronization correction control unit 208.

  First, the pulse synchronization correction control unit 208 maintains the current pulse synchronization timing when the integral value of the standard period P is the maximum (step S6), and the current value when the integral value of the progress period E is the maximum. Since the pulse synchronization timing is estimated to be delayed from the proper pulse synchronization timing (the timing at which the pulse to be received exists), the pulse synchronization timing is advanced by changing to a timing corresponding to the traveling period E, for example. (Step S7) When the integral value of the delay period L is the maximum, it is estimated that the current pulse synchronization timing is advanced from the appropriate pulse synchronization timing, so the pulse synchronization timing corresponds to the delay period L, for example. The timing is delayed by changing the timing (step S8), and the processing of steps S1 to S8 is repeated again. It is returned.

  As described above, the pulse synchronization timing can be corrected by using the synchronization interval P6 provided at regular intervals in the data pulse train P4 by the processing of steps S1 to S8, so that the pulse synchronization can be achieved for a long time. Can be maintained. In addition, an RN code generation circuit is not required to correct the pulse synchronization timing, and the integration for the standard period P, the progress period E, and the delay period L is sequentially executed by one integrator 201. It is simple.

(Second Embodiment)
Next, a receiving apparatus according to the second embodiment of the present invention will be described. FIG. 9 is a block diagram showing an example of the configuration of the receiving device 2a according to the second embodiment of the present invention. The receiving apparatus 2 shown in FIG. 6 is different from the receiving apparatus 2a shown in FIG. 9 in the following points. That is, the receiving device 2a shown in FIG. 9 further includes a synchronization progress integrator 209 and a synchronization delay integrator 210, and does not include the integral value storage unit 205. Since the other configuration is the same as that of the receiving apparatus 2 shown in FIG. 6, the description thereof is omitted, and the operation of the receiving apparatus 2a shown in FIG. 9 will be described below.

  First, since the reception operation in the data section P5 in the pulse synchronization control unit 206, the bit synchronization control unit 207, and the pulse synchronization correction control unit 208a is the same as that of the reception device 2 shown in FIG. Next, in the synchronization section P6, the pulse synchronization correction control unit 208a causes the progress period E, the standard period P, and the delay period L to be transferred to the synchronization progress integrator 209, the integrator 201, and the synchronization delay integrator 210, respectively. Set as the integration period.

  FIG. 10 is a diagram illustrating an example of the integration signals SP, SE, and SL output from the integrator 201, the synchronization progress integrator 209, and the synchronization delay integrator 210. As shown in FIG. 10, in the synchronization period P6, the received signal output from the low-pass filter 24 is integrated in parallel by the synchronization progress integrator 209, the integrator 201, and the synchronization delay integrator 210, The integration signals SE, SP, and SL are output to the AD converter 204.

  The integrated signals SE, SP, SL are AD-converted by the AD converter 204, and the integrated values for the progress period E, the standard period P, and the delay period L are output to the pulse synchronization correction control unit 208a.

  Further, the pulse synchronization correction control unit 208a maintains the current pulse synchronization timing when the integral value of the standard period P is maximum, as in steps S5 to S8 in FIG. Is the maximum, the current pulse synchronization timing is estimated to be delayed from the appropriate pulse synchronization timing, so that the pulse synchronization timing is advanced to a timing corresponding to the progress period E, for example, and the delay When the integral value of the period L is the maximum, it is estimated that the current pulse synchronization timing is advanced from an appropriate pulse synchronization timing, so that the pulse synchronization timing is changed to a timing corresponding to the delay period L, for example. Delayed by

  As a result, in the data pulse train P4, the pulse synchronization timing can be corrected using the synchronization interval P6 provided at regular intervals, so that the pulse synchronization state can be maintained for a long time. Further, since the integration for the progress period E, the standard period P, and the delay period L is executed in parallel by the synchronization progress integrator 209, the integrator 201, and the synchronization delay integrator 210, the progress period E, standard Compared with the receiving apparatus 2 shown in FIG. 6 that sequentially executes integration for the period P and the delay period L, the pulse synchronization timing correction processing can be speeded up.

(Third embodiment)
Next, a reception device 2b according to a third embodiment of the present invention will be described. The receiving device 2b according to the third embodiment of the present invention is configured in the same manner as the receiving device 2 shown in FIG. 6, and is shown in FIG. The receiving device 2b shown in FIG. 6 is different from the receiving device 2 in the operation of the pulse synchronization correction control unit 208b. Since the other configuration is the same as that of the receiving apparatus 2 shown in FIG. 6, the description thereof will be omitted, and the operation of the receiving apparatus 2b shown in FIG. 6 will be described below.

  In the receiving apparatus 2 shown in FIG. 6, it is estimated that the timing at which the integral value for the progress period E, the standard period P, and the delay period L is maximum is the current pulse position, and the timing corresponding to the corresponding period is pulse-synchronized. By adjusting the timing, the pulse synchronization timing is corrected.

  On the other hand, in the receiving device 2b according to the present embodiment illustrated in FIG. 6, the pulse synchronization correction control unit 208b sequentially performs the progression period E, the standard period P, and the delay period L, for example, one third of the synchronization period P6. Fine adjustment of the pulse synchronization timing is performed by changing the correction amount for correcting the pulse synchronization timing according to the level of the progress integration value Se, the standard integration value Sp, and the delay integration value S1, which are integration values obtained by the integration. Is to do. For example, the correction amount is set in advance according to the combination pattern of the level of the progress integration value Se, the standard integration value Sp, and the delay integration value S1, so that the progress integration value Se, the standard integration value Sp, and the delay integration value are set. A correction amount of the pulse synchronization timing according to the level of the value S1 is obtained.

  FIG. 11 is an explanatory diagram in the form of a table showing an example of the correction amount of the pulse synchronization timing according to the levels of the progress integration value Se, the standard integration value Sp, and the delay integration value Sl. In FIG. 11, the level of the progressive integration value Se, the standard integration value Sp, and the delay integration value S1 in the “integration value” column is set to a high threshold level by comparing with, for example, three levels of threshold values: high, medium, and low. The above integral values are double circles, the integral values above the middle threshold level and below the high threshold level are circled, the integral values below the low threshold level and below the middle threshold level are triangular, and the integral values below the low threshold level are × It is represented by The “timing” column indicates an integration period in which the integral value is maximized. In the “direction” column, “−” indicates that the pulse synchronization timing is corrected in the advance direction, and “+” indicates that the pulse synchronization timing is corrected in the delay direction.

  Further, the column “change amount × Δt” indicates how many times the correction amount is the minimum unit Δt of timing correction. In this case, the minimum unit Δt is set to a period shorter than the standard period P, for example, 1/6 of the standard period P, that is, 1/6 of one channel time slot. 11 indicates an integral value when the pulse P61 is at the central position of the standard period P, and reference numeral C indicates an integral value when the pulse P61 is at the central position of the traveling period E. Reference symbol D indicates an integral value when the pulse P61 is at the center position of the delay period L.

  FIG. 12 is a timing chart for explaining the operation of the receiving device 2b shown in FIG. FIG. 12A shows a case where the pulse P61 is shifted in the delay direction from the center position of the standard period P, that is, a case where the pulse synchronization timing is ahead of the actual pulse. In FIG. 12, an example in which the progress period E is set to be advanced from the standard period P by ½ of the standard period P, and the delay period L is set to be delayed from the standard period P by ½ of the standard period P. Show.

  Then, in the synchronization section P6, for example, as shown in FIG. 12A, when the pulse P61 is shifted in the delay direction from the center position of the standard period P, the pulse synchronization correction is performed as shown by the reference symbol E in FIG. The control unit 208b obtains an integral value (x mark) less than the low threshold level as the progress integral value Se, and obtains an integral value (double circle mark) above the high threshold level as the standard integral value Sp. As a result of obtaining an integral value (circle) that is greater than or equal to the middle threshold level and less than the higher threshold level as Sl, as shown in FIG. 12B, the pulse synchronization timing is set in the “+” direction by the pulse synchronization correction control unit 208b. That is, correction is made in the delay direction for a time of Δt × 1.

  As a result, the correction amount of the pulse synchronization timing is increased or decreased based on the level of the progress integration value Se, the standard integration value Sp, and the delay integration value Sl, so that the correction accuracy of the pulse synchronization timing can be improved.

(Fourth embodiment)
Next, a reception device 2c according to a fourth embodiment of the present invention will be described. The receiving device 2c according to the fourth embodiment of the present invention is configured in the same manner as the receiving device 2 shown in FIG. 6, and is shown in FIG. 6 is different from the receiving apparatus 2 in the operation of the pulse synchronization correction control unit 208c. Since the other configuration is the same as that of the receiving apparatus 2 shown in FIG. 6, the description thereof will be omitted, and the operation of the receiving apparatus 2c shown in FIG. 6 will be described below.

  FIG. 13 is an explanatory diagram for explaining the operation of the receiving device 2c shown in FIG. In the receiving device 2c shown in FIG. 6, the pulse synchronization correction control unit 208c corrects the pulse synchronization timing in the same manner as the receiving device 2 shown in FIG. After being performed, a fine adjustment mode F for finely adjusting the pulse synchronization timing is further provided.

  FIG. 14 is an explanatory diagram for explaining the control operation of the pulse synchronization correction control unit 208c in the fine adjustment mode F. In the fine adjustment mode F, the integration period ts that is a period corresponding to, for example, the channel 1 is set in the integrator 201 by the pulse synchronization correction control unit 208c, and the integration signal SD for the integration period ts is pulse-synchronized by the integrator 201. It is output to the control unit 208c. Then, the pulse synchronization correction control unit 208 determines whether or not the integration signal SD exceeds a predetermined determination threshold for determining the presence or absence of a preset pulse. Thereby, the pulse synchronization correction control unit 208c determines whether or not there is a pulse P61 in the integration period ts.

First, in the initial state shown in FIG. 14A, the integration period ts coincides with the standard period P. Next, in order to search for the position of the pulse P61 by the pulse synchronization correction control unit 208c, the integration signal SD by the integrator 201 is equal to or less than a determination threshold, that is, the timing of the integration period ts is, for example, the advance direction until the pulse P61 disappears in the integration period ts Changed to In the example shown in FIG. 14B, the timing of the integration period ts is changed, for example, in the advance direction by the unit time Δt ₂ . The unit time Δt ₂ is a minimum unit time for finely adjusting the pulse synchronization timing, and is set to, for example, the integration period ts, that is, 1 / n of the time slot of each channel. In the example shown in FIG. 14, the integration period ts 1/3 of that.

When the pulse synchronization correction control unit 208c detects that the pulse P61 disappears in the integration period ts, the pulse synchronization correction control unit 208c calculates the number obtained by rounding up n / 2 to an integer and the unit time Δt ₂ . The integration period ts is changed in the opposite direction to that in FIG. 14B, that is, in the delay direction, by the multiplied time, Δt ₂ × 2 in FIG. 14C. Then, since the pulse P61 is positioned at the center position of the integration period ts, the pulse synchronization correction control unit 208c changes the pulse synchronization timing to coincide with the integration period ts.

  Accordingly, the timing at which the pulse P61 is located at the center position of the standard period P is searched, and the pulse synchronization timing is corrected based on the searched timing, so that the correction accuracy of the pulse synchronization timing can be improved.

Although FIG. 14 shows an example in which the pulse P61 is searched in one direction, as shown in FIG. 15, the search may be made alternately in two directions of advance and delay. In FIG. 15, first, in the initial state shown in FIG. 15A, the pulse P61 is present within the integration period ts, but the pulse P61 may be shifted from the center position of the integration period ts. Therefore, for example, as shown in FIG. 15B, the pulse synchronization correction control unit 208c first advances the integration period ts by the time of Δt ₂ × 1. In the timing of FIG. 15B, since the pulse P61 is present within the integration period ts, as shown in FIG. 15C, the integration period ts is delayed by the time of Δt ₂ × 2 by the pulse synchronization correction control unit 208c. That is, the time is delayed by Δt ₂ × 1 from the initial state shown in FIG.

Next, since there is a pulse P61 within the integration period ts at the timing shown in FIG. 15C, the integration period ts is set to Δt ₂ × 3 by the pulse synchronization correction control unit 208c as shown in FIG. 15D. In other words, the timing is advanced by a time of Δt ₂ × 2 from the initial state shown in FIG. Then, since there is no pulse P61 within the integration period ts, the pulse synchronization correction control unit 208c detects that the pulse P61 has disappeared during the integration period ts, and the number obtained by rounding up n / 2 to an integer and unit time Δt ₂ The integration period ts is changed in the delay direction by a time multiplied by, that is, Δt ₂ × 2. Then, since the pulse P61 is positioned at the center position of the integration period ts, the pulse synchronization correction control unit 208c changes the pulse synchronization timing to coincide with the integration period ts.

  Accordingly, the timing at which the pulse P61 is located at the center position of the standard period P is searched, and the pulse synchronization timing is corrected based on the searched timing, so that the correction accuracy of the pulse synchronization timing can be improved. In addition, since the timing of the pulse P61 is alternately searched for the two directions of advance and delay, the pulse P61 is substantially the same regardless of whether the pulse P61 advances from the center position of the standard period P or is delayed. It is possible to search for the timing of the pulse P61 at the time.

  In the pulse synchronization correction control units 208b and 208c shown in FIG. 6, the integrator 201 sequentially integrates the progress period E, the standard period P, and the delay period L, and the progress integration value Se, the standard integration value Sp, and the delay Although an example in which the integration value S1 is acquired has been shown, the progress integration value Se, standard using the integrator 201, the synchronization progress integrator 209, and the synchronization delay integrator 210, as in the receiver 2a shown in FIG. The integral value Sp and the delay integral value S1 may be acquired at the same time.

It is a figure which shows an example of the communication frame used for the communication method which concerns on one Embodiment of this invention. It is a figure which shows an example of the area structure of the pulse train for data shown in FIG. It is a figure which shows an example of the pulse arrangement | sequence in the data area shown in FIG. It is a figure which shows an example of the pulse arrangement | sequence in the synchronous area shown in FIG. It is a block diagram which shows an example of the transmitter which transmits the communication frame shown in FIG. It is a block diagram which shows an example of a structure of the receiver which concerns on 1st, 3rd and 4th embodiment of this invention. It is explanatory drawing for demonstrating operation | movement of the integrator shown in FIG. It is a flowchart for demonstrating operation | movement of the pulse synchronous correction control part shown in FIG. It is a block diagram which shows an example of a structure of the receiver which concerns on the 2nd Embodiment of this invention. FIG. 10 is an explanatory diagram for explaining an operation of the integrator shown in FIG. 9. It is explanatory drawing of a table | surface form which shows an example of the correction amount of the pulse synchronous timing according to the level of the progress integral value, standard integral value, and delay integral value which concerns on the 3rd Embodiment of this invention. It is explanatory drawing for demonstrating operation | movement of the receiver which concerns on the 3rd Embodiment of this invention. It is explanatory drawing for demonstrating operation | movement of the receiver which concerns on the 4th Embodiment of this invention. It is explanatory drawing for demonstrating operation | movement of the receiver which concerns on the 4th Embodiment of this invention. It is explanatory drawing for demonstrating operation | movement of the receiver which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the receiver which concerns on background art. It is explanatory drawing for demonstrating operation | movement of the receiver which concerns on background art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Transmission apparatus 2, 2b, 2c Reception apparatus 21 Antenna 22 Amplifier 23 Detector 24 Low-pass filter 25 Pulse synchronous circuit 201 Integrator 202 Timing control part 203 Pulse position information storage part 204 AD converter 205 Integration value storage part 206 Pulse Synchronization control unit 207 Bit synchronization control unit 208, 208a, 208b, 208c Pulse synchronization correction control unit 209 Synchronization progress integrator 210 Synchronization delay integrator C Fine adjustment mode P1 Communication frame P2 Pulse synchronization pulse train P3 Bit synchronization pulse train P4 Data pulse train P5 Data section P51 Pulse section P52 Bit section P6 Synchronization section P61 Pulse

Claims (8)

A communication method for performing communication using a pulse train modulated by an on-off keying method,
Sending and receiving data using a communication frame comprising a pulse synchronization pulse train for synchronizing the pulse position in the pulse train, and a data pulse train representing data,
The data pulse train includes a synchronization correction pulse train for correcting synchronization of the pulse positions at predetermined intervals. The synchronization correction pulse train is provided with a pulse in a predetermined channel among channels assigned to each time slot obtained by subdividing a pulse section which is a time given for each pulse into a plurality of time slots. The communication method according to claim 1, wherein: A pulse synchronization pulse train for synchronizing with a pulse in a pulse train modulated by an on-off keying method, and a data pulse train representing data, wherein the data pulse train includes the pulse at predetermined intervals. The synchronization correction pulse train is assigned to each time slot obtained by subdividing a pulse section, which is a time given for each pulse, into a plurality of time slots. A pulse synchronization circuit that performs pulse synchronization by receiving a communication frame having a pulse in a predetermined designated channel among channels,
An integration circuit that integrates the synchronization correction pulse train with respect to a standard period that is a period corresponding to the designated channel, a progress period in which the standard period is advanced, and a delay period in which the standard period is delayed;
When the integration value for the standard period by the integration circuit is maximum, the timing of the pulse synchronization is maintained, and when the integration value for the progress period is maximum, the timing of the pulse synchronization is advanced. A synchronization timing correction unit that corrects the pulse synchronization timing by delaying the pulse synchronization timing when the integral value for the delay period is maximum;
A pulse synchronization circuit comprising: An integral value storage unit for storing an integral value obtained by the integrating circuit;
The integration circuit sequentially integrates the synchronization correction pulse train for the standard period, the advance period, and the delay period, and stores the integration values in the integration value storage unit, respectively.
4. The pulse synchronization circuit according to claim 3, wherein the synchronization timing correction unit performs the correction based on an integration value for each period stored in the integration value storage unit. The integration circuit includes:
A standard integration circuit for integrating the synchronization correction pulse train for the standard period;
A progress integration circuit that integrates the synchronization correction pulse train for the progress period;
A delay integration circuit that integrates the synchronization correction pulse train for the delay period;
With
The synchronization timing correction unit performs the correction based on an integration value for a standard period by the standard integration circuit, an integration value for a progress period by the progress integration circuit, and an integration value for a delay period by the delay integration circuit. 4. The pulse synchronization circuit according to claim 3, wherein the pulse synchronization circuit is performed. The synchronization timing correction unit changes a correction amount for correcting the timing of the pulse synchronization based on an integral value for the standard period, an integral value for the advance period, and an integral value for the delay period. 6. The pulse synchronization circuit according to claim 3, wherein the pulse synchronization circuit is one.   The synchronization timing correction unit performs the correction using a part of the synchronization correction pulse train, and then determines the timing at which the other pulses of the synchronization correction pulse train are located at the center position in the standard period after the correction. The pulse synchronization circuit according to any one of claims 3 to 6, wherein the pulse synchronization circuit further searches and corrects the pulse synchronization timing based on the searched timing. A receiving unit that receives a communication signal using a pulse train modulated by an on-off keying method;
A pulse synchronization circuit that performs pulse synchronization with the communication signal received by the receiver;
A data restoration unit for restoring data from a communication signal received by the reception unit based on pulse synchronization by the pulse synchronization circuit;
The receiving apparatus according to claim 3, wherein the pulse synchronization circuit is the pulse synchronization circuit according to claim 3.

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