RU2542669C1 - Method for code cycle synchronisation of information units for fixed link operating speed range - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: method comprises first performing parallel processing of signals of a code sequence with N PCRU (phase correction and registration unit) devices; transmitting signals from each PCRU to inputs of corresponding N FS (frame synchroniser), which analyse the input sequence; in each FS, decoding PM (phase marker), based on which, in error-free words and words containing errors, the number of BCH code words is decoded and said numbers are recorded in corresponding counters; with each clock signal, increasing by one the numbers recorded in counters, the status of which is analysed at time instances corresponding to boundaries of codewords, determining the number of counters which, at the end of receiving the last message bit, are overfilled, and generating a FSS (frame synchronisation signal) for information units. The output of each PCRU is connected to the corresponding Data input of RAM. The FSS signal, generated in the FS, in which the frequency of clock signals matches the transmission speed of signals in the link, switches the corresponding RAM from Write mode to Read mode, wherein the data output of the RAM and the Information Attribute signal output is switched by a switch to the inputs of the decoder of a telecode communication receiver.

EFFECT: higher reliability of received information in high-noise level links.

3 cl

Description

The invention relates to discrete information transmission systems and can be used in code cycle synchronization for a range of fixed operating speeds in a communication channel in error-correcting information transmission systems that use corrective, in particular, cascade codes.

When developing methods of code cycle synchronization for communication channels with a high level of interference, an urgent task is to increase the reliability of the received information.

There is a method of cyclic synchronization of information blocks for a range of fixed operating speeds in a communication channel, in which a telecode information receiver without first setting a working speed value performs parallel processing of signals of a code sequence of information blocks arriving from a communication channel at any speed from a fixed operating speed range, N devices phase correction and registration (UVKR), after processing, signals from each UVKR are fed to the inputs of N corresponding devices cycle synchronization (DSC), which simultaneously analyze the input code sequence, consisting of code words generated on the transmitting side in the form of a sum modulo two three sequences: an information sequence encoded by a Bose-Chowdhury-Hockingham cyclic code (BCH), numbering sequence, providing numbering of code words in the transmitted block of information, and a phasing sequence, while in each DCS the phase sign (DPR) is decoded - a sign of receiving the end of the codes of the word BCH, according to the DPR signal in error-free words, decode the number of the BCH code word and write into the counters the numbers defining the numbers of the BCH code words, the capacity of the counters is chosen equal to the product of the number of code words in the information block and the number of bits in the code word, with each clock signal, the repetition rate of which is equal to the speed of receipt from the communication channel, produce an increase by one unit of numbers recorded in the counters, analyze the number of counters that are recorded at the moments corresponding to the boundaries of the code words, and determine dividing the number of counters that showed overflow by the end of reception of the last bit of the information block, generate a cyclic synchronization signal (SCC) of information blocks if the number of counters showing overflow turns out to be greater than the selected threshold determined by the parameters of the communication channel, error-correcting code, and requirements for the probability of synchronization, to the output of each UVKR connect the input "Data" of the corresponding random access memory (RAM), all RAM set to "Record", and the clock inputs of RAM apply signals with frequencies equal to the gradations of the corresponding working speeds of receiving signals from the communication channel, the SCC signal generated in the CCS, in which the frequency of the clock signals coincided with the transmission speed of the signals in the communication channel, switch the corresponding RAM to the "Read" mode, while a clock signal with a read frequency is connected to the RAM clock input, when reading from the RAM, a “Sign of Information” signal is generated with a duration from the beginning to the end of the read, also with this SCS signal the RAM information output and output the generated signal "Information Sign" by the switch is switched to the inputs of the decoder of the receiving device telecode communication [RF Patent No. 2342795, IPC ⁷ H04L 7/08. Kukharev A.D., Grishin Yu.K., Filimonov Yu.F. The method of cyclic synchronization of information blocks for a range of fixed speeds in the communication channel, prior. 02/26/2007, publ. 12/27/2008].

The above method is the closest to the proposed method and adopted as a prototype.

The disadvantage of the prototype is the low reliability of the function in the channels with a high level of interference, since synchronization uses only error-free code words.

The purpose of the invention is to increase the reliability of the received information for the method of code cyclic synchronization of information blocks for a range of fixed speeds in the communication channel and, as a result, ensuring the possibility of its operation in communication channels with a high level of interference.

To achieve the goal, a code-based cycle synchronization of information blocks is proposed for a range of fixed operating speeds in a communication channel, in which a telecode information receiver without first setting a working speed value performs parallel processing of signals of a code sequence of information blocks coming from a communication channel with any speed from a fixed-speed range work, N UVKR devices. After processing, the signals from each UVCR are fed to the inputs of the N corresponding DSCs, in which the input sequence is analyzed in parallel, consisting of code words formed on the transmitting side in the form of a sum modulo two three sequences: an information sequence encoded by a cyclic BCH code, numbering sequence, providing numbering of code words in the transmitted block of information, and a phasing sequence. In this case, in each DCS, the DPR is decrypted, and in error-free words and words containing a certain number of errors, the number of the BCH code word is decrypted. According to the DPR, the numbers that determine the numbers of the BCH codewords are recorded in the corresponding counters. The capacity of the counters is chosen equal to the product of the number of code words in the information block and the number of bits in the code word. With each clock signal, the repetition rate of which is equal to the speed of receipt from the communication channel, produce an increase of one unit of numbers recorded in the counters. At the moments corresponding to the boundaries of the code words, they analyze the state of the counters and determine the number of counters that showed an overflow by the end of reception of the last bit of the information block. The SCC signals for information blocks are formed if the number of counters that have shown overflow turns out to be greater than the selected threshold determined by the parameters of the communication channel, the error-correcting code, and the requirements for the probability of synchronization. To the output of each UVKR connect the input "Data" of the corresponding RAM. All RAMs are set to the “Record” mode, and the clock inputs of the RAM supply signals with frequencies equal to the gradations of the corresponding working speeds of receiving signals from the communication channel. The SCC signal generated in the SCC, in which the frequency of the clock signals coincided with the transmission speed of the signals in the communication channel, switch the corresponding RAM into the “Read” mode. At the same time, a clock signal with a read frequency is connected to the clock input of RAM. When reading from RAM, a “Information Sign” signal is generated with a duration from the beginning to the end of reading. Also, with this SCS signal, the information output of RAM and the output of the generated signal “Information Sign” are switched by the switch to the inputs of the decoder of the receiver of the telecode communication device.

What is new is that the numbers of the BCH code words are decrypted not only in error-free words, but also in words containing a certain number of errors.

комбинацию синдрома, а для исправления в них всех двойных ошибок требуется дешифрировать $$C_{31}^2=465$$

комбинаций синдрома. Для дешифрирования номеров кодовых слов БЧХ с учетом исправления возможных ошибок в пределах корректирующей способности кода составляется таблица, адресом которой является значение синдрома, а выходом корректирующая комбинация, которая учитывает исправляемую ошибку и суммируемую фазирующую последовательность. В практических схемотехнических решениях истинные номера кодовых слов БЧХ получаются суммированием по модулю два выделяемой фильтром Хаффмена комбинации искаженного номера с корректирующей комбинацией. Одним из примеров такого практического решения является устройство кодовой цикловой синхронизации, в котором возможные ошибки исправляются в пределах корректирующей способности кода [Патент РФ №2383104, МПК⁷ H04L 7/08. Забабурин А.Н., Квашенников В.В., Третьяков А.Н., Трушин С.А. Устройство кодовой цикловой синхронизации, приор. 1308.2008, опубл. 27.02.2010].The operation of the proposed method of code cyclic synchronization of information blocks for a range of fixed operating speeds in a communication channel will be considered using a specific example of an information block consisting of a code sequence of thirty one-bit code words, which is a bitwise sum modulo two three sequences: an information sequence formed by a BCH code word with the generating polynomial X ¹⁵ + X ¹¹ + X ¹⁰ + X ⁹ + X ⁸ + X ⁷ + X ⁵ + X ¹⁵ + X ³ + X ² + X + 1, the numbering sequence of the generatrix the polynomial X ⁵ + X ² +1 and providing numbering of code words in the information block, and a constant phasing sequence formed by the generating polynomial X ⁵ + X ⁴ + X ² + X + 1 and violating the cyclic properties of the information and numbering sequences. Two code sequences differ from each other in certain positions, the number of which is called the code distance and is denoted by d. The smallest value of d for all pairs of code sequences is denoted by d _min and is called the minimum code distance. The number of errors t, corrected in such code sequences is t = (d _min -1) / 2 and determines the corrective ability of the code. For the codewords shown in the example, the minimum code distance is five, which allows us to correct no more than two errors within the corrective capacity of this code. For error-free codewords, only a combination of one syndrome needs to be decoded. For the given example, when correcting only single errors in code words, you need to decrypt $$C_{31}^{\mathrm{one}}=31$$

a combination of the syndrome, and to correct all double errors in them, you need to decrypt $$C_{31}^2=465$$

combinations of the syndrome. To decode the numbers of the BCH code words, taking into account the correction of possible errors within the correcting ability of the code, a table is compiled whose address is the value of the syndrome, and the output is a corrective combination that takes into account the corrected error and the summed phasing sequence. In practical circuit solutions, the true numbers of the BCH codewords are obtained by adding modulo two combinations of the distorted number and the correcting combination allocated by the Huffman filter. One example of such a practical solution is a code cycle synchronization device in which possible errors are corrected within the correcting ability of the code [RF Patent No. 2383104, IPC ⁷ H04L 7/08. Zababurin A.N., Kvashennikov V.V., Tretyakov A.N., Trushin S.A. Code cyclic synchronization device, prior. 1308.2008, publ. 02/27/2010].

Cyclic synchronization with tough decisions can be performed not only by code words with errors that are within the corrective ability of the code, but also by sequences of code words with errors that are outside the corrective ability of the code. The information sequence formed by the BCH codeword with the generating polynomial X ¹⁵ + X ¹¹ + X ¹⁰ + X ⁹ + X ⁸ + X ⁷ + X ⁵ + X ¹⁵ + X ³ + X ² + X + 1 has a minimum code distance equal to seven, which allows you to correct up to three errors. The codewords transmitted to the channel have a minimum code distance of five. Therefore, each version of the triple error corresponds to five variants of numbers, and four of them are false numbers. To determine the true numbers in this case, it is necessary to use the regularity that the number of each previous codeword in the block is one less than the next codeword in this block, that is, the true codeword number with three errors can be determined by continuous chains of codewords . Examples in which possible errors are corrected beyond the corrective ability of the code are the following code cycle synchronization devices [RF Patent No. 2302701, IPC ⁷ H04L 7/08. Zababurin A.N., Kvashennikov V.V., Tretyakov A.N., Trushin S.A. Code cyclic synchronization device, prior. November 17, 2008, publ. 07/10/2007], [RF Patent No. 2383104, IPC ⁷ H04L 7/08. Zababurin A.N., Kvashennikov V.V., Tretyakov A.N., Trushin S.A. Code cyclic synchronization device, prior. 08/13/2008, publ. 02/27/2010].

To further increase the reliability of the received information by correcting errors outside the corrective ability of the code, it is necessary to use soft decision methods. A popular method with soft solutions is Chase's algorithm 2 [Clark, J. Jr., Kane, J. Coding with error correction in digital communication systems / Transl. from English, p. 160-162. R. Morelos-Zaragoza. The art of noiseless coding. Methods, algorithms, applications. - M .: Technosphere, 2006, p.210-213]. One example in which the Chase 2 soft decision method is used to correct possible errors outside the correcting ability of the code is a code-clock synchronization device [RF Patent No. 2450464, IPC ⁷ H04L 7/00. Kvashennikov V.V., Trushin S.A. Code cyclic synchronization device with integrated soft and hard solutions, prior. 02.24.2011, publ. 05/10/2012]. The application of soft decision methods in the proposed method makes it possible to determine the numbers in the information sequence formed by the BCH code word with the generating polynomial X ¹⁵ + X ¹¹ + X ¹⁰ + X ⁹ + X ⁸ + X ⁷ + X ⁵ + X ¹⁵ + X ³ + X ² + X + 1, with the number of errors not more than d _min - 1, that is, up to six errors.

In the proposed method of code cyclic synchronization of information blocks for a range of fixed speeds in the communication channel, unlike the prototype, the numbers of the BCH code words are decrypted not only in error-free words, but also in words containing a certain number of errors, which increases the reliability of the received information and, as a result, provides the ability to work in communication channels with a high level of interference.

Achievable technical result of the proposed method of code cyclic synchronization of information blocks for a range of fixed operating speeds in a communication channel is to increase the reliability of received information for communication channels with a high level of interference with automatic code cyclic synchronization of information blocks for any transmission speed of signals from a range of fixed operating speeds and ensuring automatic operation of the receiver of telecode equipment without first setting the speed and work in the communication channel.

Claims (3)

1. A method of code cyclic synchronization of information blocks for a range of fixed operating speeds in a communication channel, in which a telecode information receiver without first setting a working speed value performs parallel processing of signals of a code sequence of information blocks coming from a communication channel at any speed from a fixed operating speed range, N phase correction and registration devices (UFKR), after processing, signals from each UFKR are fed to the inputs of N corresponding devices cycle synchronization (DSC), in which the input sequence consisting of code words generated on the transmitting side in the form of a sum modulo two three sequences is simultaneously analyzed: an information sequence encoded by the Bose-Chowdhury-Hockingham cyclic code (BCH), numbering the sequence, providing the numbering of code words in the transmitted message and the phasing sequence, while in each DCS the phase sign (FGTR) is decoded - a sign of receiving the end of the code word CH, according to the DPR signal in error-free words, decode the number of the BCH code word and write to the counters the numbers defining the numbers of the BCH code words, the capacity of the counters is chosen equal to the product of the number of code words in the message and the number of bits in the code word, with each clock signal, the repetition rate of which equal to the speed of receipt from the communication channel, produce an increase by one unit of numbers recorded in the counters, then analyze the number of counters that are recorded at the moments corresponding to the boundaries of the code words, and determine a set of counters that showed an overflow by the end of reception of the last bit of the information block, generate a cyclic synchronization signal (SCC) of information blocks if the number of counters showing overflow turns out to be greater than the selected threshold determined by the parameters of the communication channel, error-correcting code, and requirements for the probability of synchronization, the output of each UVKR connect the input "Data" of the corresponding random access memory (RAM), all RAM are set to "Record", and the clock inputs of RAM are fed Ala with frequencies equal to the gradations of the corresponding working speeds of receiving signals from the communication channel, the SCS signal formed in the CCS, in which the frequency of the clock signals coincided with the transmission speed of the signals in the communication channel, switch the corresponding RAM to the "Read" mode, while a clock signal with a read frequency is connected to the RAM input, when reading from the RAM, a “Sign of Information” signal is generated with a duration from the beginning to the end of the read, also with this SCS signal the information output of the RAM and the output of the nnogo signal "Symptom information" switch is switched to the inputs of a decoder receiving telecode communication device, characterized in that, for determining numbers BCH codewords decrypted not only error-free word, but also decrypted BCH codewords with a number of errors not exceeding
(d ₁ -1) / 2, where d ₁ is the minimum code distance of an input sequence consisting of code words formed on the transmitting side in the form of a sum modulo two three sequences: information, numbering and phasing. 2. The method according to claim 1, characterized in that to determine the numbers of the BCH codewords, the BCH codewords are further decoded with the number of errors not exceeding (d ₂ -1) / 2, where d ₂ is the minimum code distance of the BCH information code sequence. 3. The method according to claim 2, characterized in that to determine the numbers of the BCH codewords, the BCH codewords are further decrypted with the number of errors not exceeding (d ₂ -1), for which soft decision methods are used.