GB2263609A

GB2263609A - Clock extract circuit

Info

Publication number: GB2263609A
Application number: GB9120724A
Authority: GB
Inventors: Simon Guy Packer
Original assignee: GPT Ltd; Plessey Telecommunications Ltd
Current assignee: GPT Ltd; Plessey Telecommunications Ltd
Priority date: 1991-09-30
Filing date: 1991-09-30
Publication date: 1993-07-28
Anticipated expiration: 2011-09-30
Also published as: GB9120724D0; GB2263609B

Abstract

A data clock extraction circuit comprises two digital monostables each arranged to have applied to the trigger input thereof an input data stream, the output of each monostable being connected to the reset input of a respective counter, each counter dividing by N, the outputs of the counters being connected to the inputs of an OR-gate, the output of which is the extracted data clock and means for providing a sample clock signal having true and inverse signals of a frequency which is an N times multiple of the data clock frequency, the true signal being connected to the timing input of one of said monostables and the counter input of one of said counters and the inverse signal being connected similarly to the other of said monostables and the counters. <IMAGE>

Description

CLOCK EXTRACT CIRCUIT It is usual in digital data transmission to extract the transmitted clock frequency from the data stream at the receiving terminal for use at the receiving terminal.

A typical prior art circuit is shown in Figure 1 and the waveforms are shown in Figure 2.

The input data stream, having a nominal rate of A bit/sec is applied to a trigger input of a D-type flip flop 1 operating as a digital monostable and a nominal frequency NA bit/sec is applied to the second input of the flip-flop 1, N being an integer. The flip-flop 1 produces a reset pulse, having a pulse width of one period of the sample clock SCK starting on the first rising edge of SCK after a rising edge of the input data stream. It is also possible to use the falling edge or both edges of the input data stream to trigger the flip-flop 1.

The reset pulse from the flip-flop 1 is used to reset a counter 2 having a division ratio of N and a nominal free-running output frequency of A Hz. An appropriate phase of the counter output is chosen, normally the one for which the rising edge is nominally half-way through the data period. The counter output is thus aligned with the data to provide the clock. In the absence of data transitions the counter will continue to free-run.

The waveforms produced by the circuit of Figure 1 as shown in Figure 2. The sample clock rate NA is shown as having N=8, but the actual value required is dependent on the circuit requirements.

The reset signal, the output of the flip-flop 1, is a pulse having the width of the time between two pulses of the clock SCK and has its rising edge on the first clock pulse after the rising edge of the data stream. The reset signal resets the counter 2, and hence aligns the counter output with the data stream.

Timing errors may arise for the following reasons :1) The sample clock frequency is not exactly NA bit/sec so that a phase error will build up where there are few data transitions; 2) Jitter on the data timing will modify the data period and produce timing errors; 3) The timing quantisation of the recovered clock is necessarily limited to the period of the sample clock. The higher the value of N, the smaller the phase error in the recovered clock.

According to the present invention there is provided a data clock extraction circuit comprising two digital monostables each arranged to have applied to the trigger input thereof an input data stream, the output of each monostable being connected to the reset input of a respective counter, each counter dividing by N, the outputs of the counters being connected to the inputs of an OR-gate, the output of which is the extracted data clock and means for providing a sample clock signal having true and inverse signals of a frequency which is an N times multiple of the data clock frequency the true signal being connected to the timing input of one of said monostables and the counter input of one of said counters and the inverse signal being connected similarly to the other of said monostables and the counters.

The present invention will now be described by way of example, with reference to the accompanying drawings, in which : Figure 1 is a block diagram of a prior art clock extract circuit; Figure 2 shows the signal waveforms occuring in the circuit of Figure 1; Figure 3 shows a block diagram of first embodiment of a clock extract circuit according to the present invention; Figure 4 shows the signal waveforms occurring in the circuit of Figure 3; Figure 5 shows a block diagram of a second embodiment of a clock extract circuit according to the present invention; and Figure 6 shows the signal waveforms occurring in the circuit of Figure 5.

The feature of the present invention is a circuit configuration which achieves an accuracy of recovered clock timing quantisation equal to one half of the period of the sample clock.

This accuracy is achieved only on one edge of the extract clock.

This is advantageous where there are practical limitations on the speed of the sample clock or the speed of the digital clock extract circuitry and a more accurate extract clock is required to deliver adequate or improved performance. The circuit is shown in Figure 3 in a first embodiment and comprises two circuits somewhat similar to those shown in Figure 1 connected in parallel, each having a respective flip-flop 3, 4 and counter 5, 6.

The flip-flops 3, 4 have a sample clock having a moninal frequency NA bit/sec applied to the second inputs thereof, the true signal SCK being applied to the flip-flop 3 and the inverse or not signal SCK being applied to the flip-flop 4. The input data stream having a bit-rate of A bit/sec is applied to the trigger inputs of the flip-flops 3, 4 as before.

The counters 5, 6 are preferably ring counters in which the outputs of the respective flip-flops 3, 4 are connected to inputs so as to provide reset signals and the sample clock signals SCK and SCK are connected to the inputs of counters 5, 6 respectively.

The outputs of the counters 5, 6 are connected to the inputs of an OR-gate 7. If required a fixed delay 8 may be connected to the output of the OR-gate 7.

As shown in Figure 4, similarly to the circuit of Figure 1, the outputs of the flip-flops 3, 4 are pulses having a pulse width of the time between two pulses of the sample clock, the pulses being in phase with SCK and SCK respectively. These pulses are then applied to reset the counters 5, 6 which produce outputs differing by half the sample clock pulse (SCK) spacing, due to the use of the SCK, SCK inputs. The outputs of the OR-gate 7 is then as shown.

Alternatively, as shown in Figure 5, by interchanging the SCK, SCK inputs to the counters 5, 6 the nominal offset of the clock alignment can be offset by one-half of a period of SCK.

Further, by the use of ring counters for counters 5, 6 it is possible to change the tapping point for the counter output and further adjust the alignment by this means. A similar result could be achieved with counters such as a bistable chain, but it would then be necessary to decode the state of the bistables to determine a particular count state.

A final means of adjusting the alignment of the extract clock would be the use of a delay (not shown) connected to the output of the OR-gate 7.

Claims

1. A data clock extraction circuit comprising two digital monostables each arranged to have applied to the trigger input thereof an input data stream, the output of each monostable being connected to the reset input of a respective counter, each counter dividing by N, the outputs of the counters being connected to the inputs of an OR-gate, the output of which is the extracted data clock and means for providing a sample clock signal having true and inverse signals of a frequency which is an N times multiple of the data clock frequency, the true signal being connected to the timing input of one of said monostables and the counter input of one of said counters and the inverse signal being connected similarly to the other of said monostables and the counters.

2. A data clock extraction circuit as claimed in Claim 1, wherein the true signal is connected to the timing input of one of the monostables and the counter input of the respective counter.

3. A data clock extraction circuit as claimed in Claim 1 or 2, wherein the counters are ring counters.

4. A data clock extraction circuit as claimed in any preceding claim, the counters including means for varying the alignment of the counter output in relation to the input data stream.

5. A data clock extraction circuit as claimed in any preceding claim, further including a delay connected to the OR-gate output.

6. A data clock extraction circuit, substantially as hereinbefore described, with reference to and as illustrated in Figures 3 to 6 of the accompanying drawings.