US5650649A - Floating gate type field effect transistor having control gate applied with pulses for evacuating carriers from p-type semiconductor floating gate - Google Patents
Floating gate type field effect transistor having control gate applied with pulses for evacuating carriers from p-type semiconductor floating gate Download PDFInfo
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- US5650649A US5650649A US08/650,049 US65004996A US5650649A US 5650649 A US5650649 A US 5650649A US 65004996 A US65004996 A US 65004996A US 5650649 A US5650649 A US 5650649A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
Definitions
- This invention relates to a floating gate type field effect transistor and, more particularly, to a floating gate type field effect transistor having a control gate applied with pulses for evacuating carriers from a floating gate electrode.
- a standard floating gate type field effect transistor has a source region and a drain region spaced from one another by a channel region formed in a surface portion of a semiconductor substrate and a gate structure provided on the channel region, and the gate structure is implemented by a first gate oxide film, a floating gate electrode, a second gate oxide film and a control gate electrode.
- the floating gate type field effect transistor changes the threshold level depending upon the amount of electric charge accumulated in the floating gate electrode, and is available for a memory cell of a non-volatile semiconductor memory device such as an electrically programmable read only memory device or a flush write memory device.
- the high and low threshold levels are corresponding to the two logic levels, and a data bit is written into the memory cell by injecting and evacuating electrons into the floating gate electrode.
- FIG. 1 illustrates the prior art floating gate type field effect transistor.
- the prior art floating gate type field effect transistor is fabricated on a p-type silicon substrate 1, and a thick field oxide layer 2 is selectively grown for defining an active area. Beneath the thick field oxide layer 2 is formed a heavily-doped p-type channel stopper 3 which isolates the floating gate type field effect transistor from adjacent circuit components.
- An n-type source region 4a and an n-type drain region 4b are formed in the active area, and are spaced by a channel region 4c.
- a gate structure 5 is provided on the channel region 4c, and is implemented by a lamination of a lower gate oxide film 5a, a floating gate electrode 5b, an upper gate oxide film 5c and a control gate electrode 5d.
- the floating gate electrode is formed of n-type polysilicon doped with phosphorous.
- the prior art floating gate type field effect transistor If hot electrons are injected into the floating gate electrode 5b, the prior art floating gate type field effect transistor enters into write-in state. On the other hand, if the accumulated electrons are evacuated from the floating gate electrode 5b, the prior art floating gate type field effect transistor enters into erased state.
- the write-in state and the erased state are usually featured by a large amount of accumulated electrons and a small amount of accumulated electrons, and the following description is made in accordance with the usual relation between the state and the amount of accumulated electrons. However, the relation is opposite to the above in some papers.
- the negative bias is applied between the control gate electrode 5d and the p-type silicon substrate 1.
- the negative bias may be applied between the control gate electrode 5d and the source region 4a so as to evacuate the accumulated electrons from the floating gate electrode 5a to the source region 4a.
- the high electric field created by the negative bias between the control gate electrode 5d and the p-type silicon substrate 1 deteriorates the lower gate oxide film 5a, and a large number of trapping centers take place therein.
- the floating gate type field effect transistors are changed between the write-in state and the erased state, and electrons pass through the lower gate oxide film 5a during the write-in operation and the erasing operation. Then, the electrons are trapped by the trapping centers, and the lower gate oxide film 5a is gradually charged. The charged lower gate oxide film 5a affects the threshold, and finally makes the floating gate type field effect transistor disabled.
- the prior art floating gate type field effect transistor disclosed in the Japanese Patent Publication is fabricated on a silicon substrate 21, and a thick field oxide layer 22 is selectively grown so as to define an active area.
- N-type source and drain regions 21a and 21b are formed in the silicon substrate 21, and are spaced from each other by a channel region 21c.
- a gate structure 23 is provided on the channel region 21c, and has a floating gate electrode 23a, a first control gate electrode 23b, a second control gate electrode 23c and an insulator 23d isolating these electrodes 23a to 23c from one another.
- the floating gate electrode 23a is formed of polysilicon partially doped with n-type dopant impurity and partially doped with p-type dopant impurity 23f, and the n-type section 23e and the p-type section 23f form a p-n junction 23g in the floating gate electrode 23a.
- the second prior art floating gate type field effect transistor is changed to the write-in state through the similar manner to the first prior art floating gate type field effect transistor shown in FIG. 1.
- the p-n junction 23g is reversely biased by controlling the first control gate electrode 23b capacitively coupled to the n-type section 23e and the second control gate electrode 23c also capacitively coupled to the p-type section 23f.
- Avalanche breakdown takes place at the reversely biased p-n junction 23g, and generates electron-hole pairs.
- the electrons are partially evacuated to the first control gate electrode 23b, and the holes are left in the floating gate electrode 23a, thereby extinguishing the accumulated electrons.
- the erasing does not deteriorate the insulator 23d between the floating gate electrode 23a and the silicon substrate 21.
- the second prior art floating gate type field effect transistor is free from the deterioration of the insulator 23d beneath the floating gate electrode 23a.
- the second prior art floating gate type field effect transistor encounters a problem in a complex structure due to the second control gate electrode 23c and the p-n junction 23g formed in the floating gate electrode 23a.
- the present invention proposes to dope a floating gate electrode with p-type dopant impurity.
- a floating gate type field effect transistor fabricated on a semiconductor substrate, comprising: a source region formed in a surface portion of the semiconductor substrate; a drain region formed in another surface portion of the semiconductor substrate, and spaced from the source region; a channel region located between the source region and the drain region; and a gate structure provided on the channel region, and having a first gate insulating layer covering the channel region, a floating gate electrode formed of p-type semiconductor material patterned on the first gate insulating layer, and accumulating electrons in an write-in operation, a second gate insulating layer covering the floating gate electrode, and a control gate electrode formed on the second gate insulating layer and applied with an erasing pulse signal in an erasing operation for drifting the electrons in a depletion layer produced in the floating gate electrode toward the first gate insulating layer, thereby evacuating parts of the electrons.
- FIG. 1 is a cross sectional view showing the structure of the first prior art floating gate type field effect transistor
- FIG. 2 is a graph showing the pulse applied to the control gate electrode of the first prior art floating gate type field effect transistor in the erasing operation
- FIG. 3 is a cross sectional view showing the structure of the second prior art floating gate type field effect transistor
- FIG. 4 is a cross sectional view taken along line A--A of FIG. 3;
- FIG. 5 is a cross sectional view showing the structure of a floating gate type field effect transistor according to the present invention.
- FIG. 6 is a graph showing the waveform of a pulse signal applied to a control gate electrode of the floating gate type field effect transistor in an erasing operation
- FIG. 7 is a graph showing variation of the threshold between the floating gate type field effect transistor according to the present invention and the first prior art floating gate type field effect transistor;
- FIGS. 8A to 8D are cross sectional views showing a process sequence for fabricating the floating gate type field effect transistor according to the present invention.
- FIG. 9 is a cross sectional view showing the structure of another floating gate type field effect transistor according to the present invention.
- FIG. 10 is a cross sectional view showing the structure of yet another floating gate type field effect transistor according to the present invention.
- a floating gate type field effect transistor embodying the present invention is fabricated on a p-type silicon substrate 31, and a thick field oxide layer 32 defines an active region in a surface portion of the p-type silicon substrate 31.
- a heavily doped p-type channel stopper 33 is formed beneath the thick field oxide layer 32, and isolates the active region from adjacent active regions (not shown) together with the thick field oxide layer 32.
- a heavily doped n-type source region 31a and a heavily doped n-type drain region 31b are formed in the active region, and are spaced from one another by a channel region 31c.
- a gate structure 34 is provided on the channel region 31c, and has a first gate insulating film 34a, a floating gate electrode 34b, a second gate insulating film 34c and a control gate electrode 34d.
- the gate structure 34 is wrapped in an inter-level insulating layer, and the control gate electrode 34 is connected to a variable voltage source.
- the first gate insulating film 34a and the second gate insulating film 34c are formed of silicon oxide.
- the floating gate electrode 34b is formed of p-type polysilicon, and the control gate electrode 34d is formed of n-type polysilicon.
- the floating gate type field effect transistor is changed between the write-in state and the erased state as follows.
- the write-in operation is similar to that of the prior art floating gate type field effect transistor. Namely, hot electrons are attracted toward the floating gate electrode 34b in high electric field created in the first gate insulating film 34a, and are accumulated in the floating gate electrode 34b. The accumulated electrons decrease the majority carrier of the p-type polysilicon, i.e., holes, and increase the minority carrier, i.e., electrons. As a result, the floating gate electrode 34b is changed to a negative potential level, and changes the dopant level of the channel region 31c.
- the floating gate type field effect transistor is changed to the erased state by evacuating the accumulated electrons to the p-type silicon substrate 31.
- a negative voltage level with respect to the p-type silicon substrate 31 is applied from the variable voltage source (not shown) to the control gate electrode 34d, and a depletion layer extends from the boundary between the first gate insulating layer 34a and the floating gate electrode 34b for hundreds milli-seconds upon application of the negative voltage level.
- the depletion layer consumes most of the potential difference between the control gate electrode 34d an the p-type silicon substrate 31, and only a small amount of electric stress is applied to the first gate insulating layer 34a. In other words, the depletion layer restricts the generation of the trapping centers.
- the minority carrier or the electrons in the floating gate electrode 34b are drifted toward the first insulating layer 34a, and obtains high kinetic energy in the high electric field created in the depletion layer.
- the electrons thus accelerated impact against the silicon crystal, and generate electron-hole pairs.
- the electrons produced in the silicon crystal are also accelerated in the electric field, and further generate electron-hole pairs.
- the cumulative multiplication of electrons is referred to as avalanche, and the electrons cross the potential barrier of the first insulating layer 34a at a certain probability.
- the holes equal to the electrons crossing the potential barrier are left in the floating gate electrode 34b, and urge the floating gate electrode 34b to be neutral.
- the floating gate electrode 34b in the vicinity of the first insulating layer 34a is inverted, and the minority carrier or electrons are generated. As a result, the depletion layer is shrunk, and the avalanche process is terminated. This means that the number of electrons evacuating into the silicon substrate 31 is rapidly decreased.
- the potential difference is directly applied to the first insulating layer 34a, and the first insulating layer 34a is subjected to the electric stress. In order to prevent the first insulating layer 34a from the electric stress, the negative potential is removed from the control gate electrode 34d before the inversion, and is repeated at intervals.
- a negative pulse signal is applied to the control gate electrode 34d in the erasing operation, and is shorter than a time constant for the generation of the inverted layer.
- the time constant is determined on the basis of properties of the doped polysilicon such as the dopant concentration.
- the dopant concentration of the floating gate electrode 34b is high, the avalanche breakdown is effectively produced under a relatively low negative voltage applied to the control gate electrode 34d. For this reason, the dopant concentration of the floating gate electrode 34a is equal to or greater than 5 ⁇ 10 16 cm -3 , and the negative voltage is equal to or less than -20 volts on the assumption that the p-type silicon substrate 31 is grounded.
- the present inventor evaluated the floating gate type field effect transistor according to the present invention.
- the floating gate type field effect transistor of the present invention was changed from the write-in state to the erased state, and the threshold was measured in both states.
- the pulse signal was continuously applied to the gate electrode 34d until most of the injected electrons were evaluated.
- the measured threshold was plotted in FIG. 7 as indicative by dots.
- the pulse signal had the pulse width of the order of 10 micro-second.
- the undesirable inversion layer was not produced until the pulse width of the order of 100 milli-second.
- the first prior art floating gate type field effect transistor was changed between the write-in state and the erased state, and the threshold was measured.
- the measured threshold was also plotted in FIG. 7 as indicative by small triangle.
- the threshold of the first prior art floating gate type field effect transistor tends to converge, but the floating gate type field effect transistor of the present invention keeps the threshold. Therefore, it is understood that the first insulating layer 34a is less deteriorated through the erasing operation.
- the floating gate electrode 34b of the p-type polysilicon is effective against the electric stress, and prolongs the service time period of the floating gate type field effect transistor.
- the floating gate type field effect transistor according to the present invention does not require a p-n junction in the floating gate electrode and a second control electrode, and, for this reason, the structure is simpler than the second prior art floating gate type field effect transistor.
- the process sequence starts with preparation of the p-type silicon substrate 31.
- P-type dopant impurity is selectively ion implanted into the p-type silicon substrate 31, and the thick field oxide layer 32 is selectively grown on the p-type silicon substrate 31. While the thick field oxide layer 32 is being grown, the p-type dopant impurity forms the channel stopper 33.
- the active region is exposed by removing an oxide film, and the first gate insulating layer 34a is thermally grown to 10 nanometers on the active region.
- the resultant structure is illustrated in FIG. 8A.
- Polysilicon is deposited over the entire surface of the structure to 600 nanometers by using a chemical vapor deposition, and boron is ion implanted into the polysilicon layer 41.
- the dose and accelerating energy are regulated in such a manner that the boron concentration is not less than 5 ⁇ 10 16 cm -3 upon completion of the fabrication process.
- the resultant structure is illustrated in FIG. 8B.
- Silicon oxide is deposited to 20 nanometers over the doped polysilicon layer 41, and the doped polysilicon layer is overlain by the silicon oxide layer 42. Subsequently, polysilicon is deposited to 400 nanometers over the silicon oxide layer 42, and the silicon oxide layer 42 is overlain by the polysilicon layer 43. The resultant structure is placed in phosphorus oxychloride atmosphere, and is heated therein. Then, the polysilicon layer 43 becomes n-type conductivity type, and the boron implanted into the polysilicon layer 41 is activated.
- Photo-resist solution is spun onto the polysilicon layer 43, and a mask layer 44 is patterned through a lithographic process as shown in FIG. 8C.
- the polysilicon layer 43, the silicon oxide layer 42 and the polysilicon layer 41 are partially etched away, and the floating gate electrode 34b, the second insulating layer 34c and the control gate electrode 34d are formed on the first insulating layer 34a.
- n-type dopant impurity such as arsenic or phosphorous is ion implanted into the active region in a self-aligned manner with the gate structure 34. Then, the n-type source region 31a and the heavily-doped n-type drain region 31b are formed in the active region on both side of the channel region 31c. Finally, the resultant structure is placed in nitrogen atmosphere, and is heated for activating the n-type dopant impurity.
- the fabrication process is simple, because a p-n junction of the floating gate electrode and a second control gate are not necessary for the floating gate type field effect transistor according to the present invention.
- FIG. 9 of the drawings another floating gate type field effect transistor is fabricated on a p-type silicon substrate 51.
- the floating gate type field effect transistor shown in FIG. 9 is similar to the floating gate type field effect transistor shown in FIG. 5 except for a first insulating layer 52. For this reason, layers and regions of the floating gate type field effect transistor shown in FIG. 9 are labeled with the same references designating the corresponding layers and regions of the first embodiment without detailed description.
- the first insulating layer 52 is formed of silicon nitride, and is effective against undesirable diffusion of the boron from the floating gate electrode 34b into the channel region 31c. Therefore, the channel doping level of the second embodiment is stable rather than the first embodiment.
- the first insulating layer of silicon nitride is formed as follows. First, the exposed active region is thermally oxidized for growing a silicon oxide to 8 nanometers, and the silicon oxide is heated to 1000 degrees in centigrade in ammonia atmosphere by suing a lamp heater, thereafter heating in a dry oxygen to 1050 degrees in centigrade by using the lamp heater.
- the floating gate type field effect transistor implementing the second embodiment achieves all the advantages of the first embodiment.
- FIG. 10 of the drawings yet another floating gate type field effect transistor embodying the present invention is fabricated on a p-type silicon substrate 61.
- the floating gate type field effect transistor shown in FIG. 10 is similar to the floating gate type field effect transistor shown in FIG. 5 except for a heavily doped source region 62. For this reason, layers and regions of the floating gate type field effect transistor shown in FIG. 10 are labeled with the same references designating the corresponding layers and regions of the first embodiment without detailed description.
- the heavily doped n-type source region 62 is partially overlapped with the gate structure 34, and the control gate electrode 34d is negatively biased with respect to the heavily doped n-type source region 62. As a result, electrons are evacuated to the heavily doped n-type source region in the erasing operation.
- the pulse signal shown in FIG. 6 is available for the erasing operation on the floating gate type field effect transistor shown in FIG. 10.
- the floating gate type field effect transistor according to the present invention is equipped with a floating gate electrode formed of p-type semiconductor material, and the p-type semiconductor material allows the bias between the control gate electrode and the substrate or the source region to drift accumulated electrons in the depletion layer for evacuating the electrons thereinto. Most of the bias voltage is consumed by the depletion layer, and only negligible electric stress is applied to the first insulating layer. As a result, the first insulating layer is not deteriorated, and the floating gate type field effect transistor serves as a memory cell for long time.
- an erasing pulse signal may be changed between the ground voltage level and the positive voltage level.
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US08/650,049 US5650649A (en) | 1993-12-14 | 1996-05-16 | Floating gate type field effect transistor having control gate applied with pulses for evacuating carriers from p-type semiconductor floating gate |
Applications Claiming Priority (4)
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JP5-313091 | 1993-12-14 | ||
JP5313091A JPH07169861A (ja) | 1993-12-14 | 1993-12-14 | 不揮発性半導体記憶装置 |
US35428694A | 1994-12-12 | 1994-12-12 | |
US08/650,049 US5650649A (en) | 1993-12-14 | 1996-05-16 | Floating gate type field effect transistor having control gate applied with pulses for evacuating carriers from p-type semiconductor floating gate |
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JP3319975B2 (ja) * | 1997-05-08 | 2002-09-03 | 株式会社日立製作所 | 半導体素子及びそれを用いた液晶表示装置 |
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