US5382505A - Method of making a laminated structure with shear force delamination resistance - Google Patents

Method of making a laminated structure with shear force delamination resistance Download PDF

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Publication number
US5382505A
US5382505A US07/854,884 US85488492A US5382505A US 5382505 A US5382505 A US 5382505A US 85488492 A US85488492 A US 85488492A US 5382505 A US5382505 A US 5382505A
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Prior art keywords
metal
layer
openings
protuberances
photoresist
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Expired - Lifetime
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US07/854,884
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English (en)
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Walter Schmidt
Marco Martinelli
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Dyconex AG
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Dyconex AG
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C37/00—Component parts, details, accessories or auxiliary operations, not covered by group B29C33/00 or B29C35/00
    • B29C37/0078—Measures or configurations for obtaining anchoring effects in the contact areas between layers
    • B29C37/0082—Mechanical anchoring
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B3/00—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form
    • B32B3/26—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer
    • B32B3/30—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer characterised by a layer formed with recesses or projections, e.g. hollows, grooves, protuberances, ribs
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/02—Local etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/383—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by microetching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/384—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2311/00—Metals, their alloys or their compounds
    • B32B2311/12—Copper
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • B32B2457/08—PCBs, i.e. printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0373—Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0323—Working metal substrate or core, e.g. by etching, deforming
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists

Definitions

  • the invention relates to the field of connection carriers for electronic components and specifically relates to the structuring of the surface of a metal foil in conjunction with a method for the production of a multilayer, laminated printed circuit board, as well as to a printed circuit board produced by this method.
  • Printed circuit boards for producing electronic circuits carry and connect electronic components, compactness and high interconnection density being sought. It therefore forms part of the prior art to directly solder onto the surface connection layer of printed circuit boards integrated circuits in the form of surface mounted devices (abbreviated SMD) or leadless chip carriers (abbreviated LCC).
  • SMD surface mounted devices
  • LCC leadless chip carriers
  • the printed circuit boards generally have a multilayer construction, i.e. they have several conductor layers.
  • Standard measures for reducing the thermal expansion of printed circuit boards are the fitting of cores or intermediate layers of thermally stable materials.
  • metal sheets or foils formed from a combination of copper and an alloy sold under the trademark INVARTM (an alloy of nickel and iron with a very low expansion coefficient), of molybdenum (with a thermal expansion coefficient of approximately 5 ppm/° C.) or cores with a carbon fiber reinforcement are known. Further information on this problem are provided by EP-A-393312 which is assigned to the assignee of this application.
  • the composite of thermally stable reinforcement and conductor layers i.e. the printed circuit board
  • shear stresses act at the interface between the cores or intermediate layers of the thermally more stable materials and the remaining layers of the printed circuit board. This occurs because the cores or intermediate layers, due to their high mechanical strength, force the board to remain dimensionally stable, whereas the remaining layers of the board, having the tendency to expand or contract more with the temperature change, are subject to a restriction of their freedom of movement because of their adhesive attachment to the cores or intermediate layers.
  • An object of the invention is to find a measure for preventing the delamination of coatings having different thermal expansion characteristics in a laminated, multilayer printed circuit board, without having to accept the aforementioned inadequacies and disadvantages.
  • This object is achieved by a special structuring of the surface of metal foils and the assembly of the foils in the printed circuit boards.
  • the materials now used for cores or intermediate layers normally have an outermost coating of electrically and thermally conductive, electroplatable metal, particularly copper.
  • the invention therefore aims at improving the adhesion between the outer metal surface and the conductor layer to be applied thereto. This can be efficiently and inexpensive achieved in that the surface of the metal coating is given a fine structure by photochemical treatment.
  • the photochemical process makes it possible using per se known means in a few, relatively uncomplicated operations to obtain a fine and almost randomly selectable pattern of etched-out depressions and/or electrodeposited on protuberances.
  • the contact surface between the metal and the connecting material of the next, laminated-on layer is much larger than with the untreated metal coating, which increases the overall adhesiveness.
  • the largely freely selectable shape of the depressions and protuberances also makes it possible to effectively counteract on an overall basis the shear forces directed parallel to the surface.
  • the production of patterns for photomasks can take place in a very simple manner by providing a basic element of the pattern and then repeating it in a computer assisted manner. It is also easy to make different patterns in the same mask and in particular larger parts can be excluded from the patterning with random boundaries.
  • the invention has the advantage of being based on standard technology. It can be used in virtually any printed circuit board fabrication without special means having to be used. The process is also much less expensive than "treating" copper surfaces. The product is robust with respect to scratches and compressive loads and can be treated and further processed in the same way as a normal copper surface. Where it is possible to work with conventional-metal and in particular copper-coated foils, the etching out of depressions also has the positive effect of weakening the lateral cohesion of the outer metal coating, so that the inner, thermally more stable coating can better develop its dimensional stabilization action.
  • FIG. 1 is a side elevation, in section, of a portion of a multiple-layer printed circuit board
  • FIG. 2 is an enlarged partial view of detail A of FIG. 1 showing a "treatment" coating in accordance with the prior art
  • FIGS. 3a-3d are enlarged side elevations of layers of a printed circuit board showing steps of an embodiment of the invention referred to as a subtractive technique;
  • FIGS. 4a-4c are partial plan views of a portion of a surface produced in accordance with the method of FIGS. 3a-3d;
  • FIGS. 5a-5e are enlarged side elevations of layers of a printed circuit board showing steps of a further embodiment of the invention referred to as an additive technique.
  • FIG. 1 shows an example of a multilayer, laminated printed circuit board, whose thermal expansion is kept within limits by the incorporation of two metal foils 3 each having a low thermal expansion coefficient which is, as a function of the structure, approximately 1 to 6 ppm/° C.
  • Such foils can e.g. comprise a molybdenum or INVARTM coating with a copper or copper-nickel coatings of varying thickness rolled onto one or both sides.
  • a generally multilayer conductor 2 whose thermal expansion coefficient is between approximately 12 and 20 ppm/° C.
  • the average thermal expansion coefficient for the entire printed circuit board is then 7 to 10 ppm/° C.
  • There is a delamination risk in the case of temperature changes at the contact surface where the metal foil 3 and the conductor layer 2 are laminated together. To prevent this specific metal foil surface treatment measures are taken. These measures are shown at the larger scale detail A of FIG. 1.
  • FIG. 2 shows an enlarge view of detail A of FIG. 1 with a known surface treatment of the metal foil for improving the adhesion of the laminate.
  • FIG. 2 shows the prior art.
  • the upper part of the foil 3 is shown and comprises the Invar layer 4, the copper coating 5 and an electrodeposited "treatment" coating 6 with its rough surface.
  • the lower part of the laminated-on conductor layer 2 comprising the adhesive 7, the plastic carrier 8 and the electrically conductive connections 9 and this sequence can be repeated in the conductor layer 2.
  • Foils with a treatment coating are able to prevent delamination, but not in all cases.
  • "treating" can be used on copper coatings, molybdenum or INVARTM are too hard.
  • FIGS. 3a-3d show four successive steps in a method in accordance with the invention for producing a structured surface in the metal coating of one layer of a multilayer printed circuit board.
  • FIG. 3a shows the starting material, in this case a metal foil 3 having a core part 4 covered with the metal coating 5.
  • Such foils are commercially available and are typically formed from a composite of INVARTM or molybdenum in the core part 4 and rolled on copper as the metal coating 5.
  • a copper/INVARTM foil is used in the example described manner hereinafter.
  • the method steps are shown for one of the two copper coatings 5. However, the method can be readily used in the same operation on both sides. Considered individually, all the partial steps are known per se from other sequences for the production of printed circuit boards.
  • a photoresist coating 10 is applied to the copper coating 5.
  • the photoresist usually a polymer, under the action of light locally changes its resistance to certain chemicals used for development, so that recesses can be produced in the photoresist coating.
  • the photoresist is resistant to etchants for the metal which it covers.
  • FIG. 3b shows the copper coating covered by the already exposed and developed photoresist coating 10.
  • the latter has recesses 11 at the points where depressions are to be formed in the metal surface.
  • the shape of the recesses can be freely selected. The dimensions are preferably approximately 50 to 100 micrometers.
  • FIG. 3c shows the situation following this partial step.
  • the successive material removal commences at the surface uniformly over the entire opening in the photoresist.
  • progressive etching out depth there is a slight expansion of the depression.
  • This known undercutting leads in the case of the small depressions as produced here to a bulging cavity.
  • the etching depth is decisively determined by the running speed or residence time of the workpiece in the etching process. These are known, readily controllable processes. Preferred depths are between 10 and 50 micrometers.
  • the undercutting in the etched-out depression is desired for the sought structuring purpose.
  • the resin in the cavities hardens. This leads to a positive connection, which makes a separation of the coatings virtually impossible. Only the elasticity of the materials allows separation when very high forces are exerted by overcoming the pushbutton effect.
  • a further improvement regarding the shape of the depressions can be obtained by prior hardening of the surface of the copper coating with respect to the etchant.
  • nickel is applied to the copper and diffused in by a heat treatment.
  • the etching process through the top coating then initially takes place slowly until the hardened coating has been etched through and then there is a pronounced undercutting of the harder top coating.
  • the overhanging edges of the depressions are thicker and stronger than in the previously described variant.
  • the photoresist is stripped, i.e. removed again in known manner. What is left behind is the original metal foil 2 with the recesses 12 in the copper coating 5 as shown in FIG. 3d which represents the desired structuring of the surface as regards pattern and shape.
  • the copper coating is weakened, which must be taken into account for the electrical function if this is significant. This weakening has an advantageous effect with respect to the mechanical-thermal characteristics. As there is less copper with a comparatively high thermal expansion coefficient, the INVARTM can even better fulfil its dimension-stabilizing action. Moreover, in its broken-away form the copper coating is less stiff than in the form of a uniform thick foil. The method is not restricted to copper coatings. Uncovered INVARTM or molybdenum foils can also be appropriately structured in accordance with the above-described steps.
  • FIGS. 4a-4c are plan view of structured surfaces with possible patterns of the recesses 12 in three variants in an exemplified, but non-limitative manner.
  • protuberances of the material are electrodeposited on the metal coating 5, the associated steps being shown in FIG. 5.
  • FIG. 5a again shows the copper/INVARTM foil and
  • FIG. 5b the state following the application, exposure and development of the photoresist 10 on the copper coating 5.
  • the recesses 11 are here patterned and shaped in accordance with the protuberances applied at these locations. Otherwise the partial steps do not differ up to now from those of the subtractive method.
  • the copper is electroplated on.
  • Copper protuberances 15 are formed in the recesses 11, in the manner shown in FIG. 5c.
  • the thickness of the electroplated-on coating or islands, i.e. the protuberances 15, is determined by the duration and intensity of the electroplating process.
  • the pattern and shape of the protuberances can be freely selected. It has the major advantage that overhanging structures can be produced, as shown in FIG. 5d.
  • the electroplating process is continued beyond the state of FIG. 5c. Copper is not only deposited in the recesses 11, but also, starting from the protuberances 15, over the photoresist coating 10. As a result, collars 16 are formed on the protuberances 15, which therefore acquire a mushroom-shaped configuration.
  • the mushroom-shaped protuberances 15 with their collars 16 are left behind, as shown in FIG. 5e.
  • the collars 16 bring about an extremely favourable anchoring of the resin or adhesive on the metal surface.
  • electroplating can be stopped at the state of FIG. 5c and the photoresist stripped (not shown). This leads to similar structures and shapes to those of the subtractive method.
  • Metal foils of the described type can fulfil thermal, electrical and mechanical functions. If exclusively a depression and a limited thermal expansion is sought, it is sufficient to have foils of Invar, molybdenum, etc. Both methods can be used and plating-on can e.g. take place with nickel or copper. If additionally a good electrical conductivity is sought, in order to obtain a screening effect, a copper coating, structured according to the subtractive method, may well be the correct choice. However, if the main significance is attached to the heat conduction function, then a relatively thick copper coating is appropriate and the additive method should be used.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)
  • Manufacturing Of Printed Wiring (AREA)
US07/854,884 1991-04-10 1992-03-20 Method of making a laminated structure with shear force delamination resistance Expired - Lifetime US5382505A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH01063/91-0 1991-04-10
CH106391 1991-04-10

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US5382505A true US5382505A (en) 1995-01-17

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US (1) US5382505A (de)
EP (1) EP0508946B1 (de)
AT (1) ATE140658T1 (de)
CA (1) CA2063503A1 (de)
DE (1) DE59206797D1 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0893822A2 (de) * 1997-07-22 1999-01-27 Daimler-Benz Aktiengesellschaft Verfahren zum Einbetten von metallischen Leitern mikroelektrischer Bauelemente in eine Kunststoffmasse
WO1999035305A1 (de) * 1998-01-12 1999-07-15 Robert Bosch Gmbh Design- und herstellungsverfahren für eine mikromechanische vorrichtung
US6106923A (en) * 1997-05-20 2000-08-22 Fujitsu Limited Venting hole designs for multilayer conductor-dielectric structures
US6202316B1 (en) 1998-04-14 2001-03-20 Timothy J. Swift Coordinate measuring machine guideway composite structure and method of manufacture
US20030193548A1 (en) * 2002-04-15 2003-10-16 Emery Timothy R. Bonding structure and method of making
US20050019535A1 (en) * 2000-12-12 2005-01-27 Shri Diksha Corporation Lightweight circuit board with conductive constraining cores
WO2005011345A1 (de) * 2003-07-17 2005-02-03 Ksg Leiterplatten Gmbh Schichtanordnung für ein mit elektronischen bauelementen bestückbares trägerbauteil und verfahren zur herstellung
US20050257957A1 (en) * 2004-05-15 2005-11-24 Kaluk Vasoya Printed wiring board with conductive constraining core including resin filled channels
US20060063428A1 (en) * 2004-08-27 2006-03-23 Vasoya Kalu K Printed wiring boards possessing regions with different coefficients of thermal expansion
US20060104035A1 (en) * 2004-08-24 2006-05-18 Vasoya Kalu K Edge plated printed wiring boards
US20060231198A1 (en) * 2005-03-15 2006-10-19 Vasoya Kalu K Manufacturing process: how to construct constraining core material into printed wiring board
US20080011507A1 (en) * 2006-07-14 2008-01-17 Vasoya Kalu K Build-up printed wiring board substrate having a core layer that is part of a circuit
US20100304065A1 (en) * 2009-06-02 2010-12-02 Integran Technologies, Inc. Metal-clad polymer article
US20100304179A1 (en) * 2009-06-02 2010-12-02 Integran Technologies, Inc. Electrodeposited metallic materials comprising cobalt
US20100304171A1 (en) * 2009-06-02 2010-12-02 Integran Technologies, Inc. Metal-clad polymer article
US9004240B2 (en) 2013-02-27 2015-04-14 Integran Technologies Inc. Friction liner
USRE45637E1 (en) 2005-08-29 2015-07-28 Stablcor Technology, Inc. Processes for manufacturing printed wiring boards
US9332632B2 (en) 2014-08-20 2016-05-03 Stablcor Technology, Inc. Graphene-based thermal management cores and systems and methods for constructing printed wiring boards
US9942982B2 (en) 1997-08-04 2018-04-10 Continental Circuits, Llc Electrical device with teeth joining layers and method for making the same
US10414446B2 (en) 2016-04-22 2019-09-17 Honda Motor Co., Ltd. Lightweight vehicle pan assembly and method for attachment to vehicle frame via welding
US11351627B2 (en) 2017-01-31 2022-06-07 Eshfartech Ltd. Three-dimensional laminated metallic objects, method and system of making same
US12090728B2 (en) 2017-01-31 2024-09-17 Eshfartech Ltd. Three-dimensional laminated metallic objects with periodically-diffused marking material

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998010628A1 (de) * 1996-09-05 1998-03-12 Siemens Aktiengesellschaft Trägerelement für einen halbleiterchip
AU5407698A (en) * 1996-11-22 1998-06-10 Jerseyfield Limited A printed circuit board and a method for manufacturing the printed circuit board

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3177103A (en) * 1961-09-18 1965-04-06 Sauders Associates Inc Two pass etching for fabricating printed circuitry
US3791858A (en) * 1971-12-13 1974-02-12 Ibm Method of forming multi-layer circuit panels
US3832176A (en) * 1973-04-06 1974-08-27 Eastman Kodak Co Novel photoresist article and process for its use
US4086114A (en) * 1975-05-27 1978-04-25 International Business Machines Corporation Aluminum surface treatment to enhance adhesion in a given direction
EP0016952A1 (de) * 1979-04-06 1980-10-15 International Business Machines Corporation Verfahren zum Herstellen von mit Abdeckungen versehenen Leiterplatten
GB2080729A (en) * 1980-06-25 1982-02-10 Gen Electric A multi-layer metal core circuit board laminate with a controlled thermal coefficient of expansion and method for making same.
US4328298A (en) * 1979-06-27 1982-05-04 The Perkin-Elmer Corporation Process for manufacturing lithography masks
US4446188A (en) * 1979-12-20 1984-05-01 The Mica Corporation Multi-layered circuit board
US4456500A (en) * 1982-03-02 1984-06-26 Nippon Tenshashi Kabushiki Kaisha Method of manufacturing a polisher
US4745795A (en) * 1986-02-27 1988-05-24 Kraftwerk Union Aktiengesellschaft Apparatus for measuring gases dissolved in water
EP0393312A1 (de) * 1989-04-21 1990-10-24 Dyconex AG Mehrlagige Leiterplatte
EP0476664A2 (de) * 1990-09-20 1992-03-25 Dainippon Screen Mfg. Co., Ltd. Verfahren zur Herstellung von kleinen Durchgangslöchern in dünne Metallplatten

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3177103A (en) * 1961-09-18 1965-04-06 Sauders Associates Inc Two pass etching for fabricating printed circuitry
US3791858A (en) * 1971-12-13 1974-02-12 Ibm Method of forming multi-layer circuit panels
US3832176A (en) * 1973-04-06 1974-08-27 Eastman Kodak Co Novel photoresist article and process for its use
US4086114A (en) * 1975-05-27 1978-04-25 International Business Machines Corporation Aluminum surface treatment to enhance adhesion in a given direction
EP0016952A1 (de) * 1979-04-06 1980-10-15 International Business Machines Corporation Verfahren zum Herstellen von mit Abdeckungen versehenen Leiterplatten
US4328298A (en) * 1979-06-27 1982-05-04 The Perkin-Elmer Corporation Process for manufacturing lithography masks
US4446188A (en) * 1979-12-20 1984-05-01 The Mica Corporation Multi-layered circuit board
GB2080729A (en) * 1980-06-25 1982-02-10 Gen Electric A multi-layer metal core circuit board laminate with a controlled thermal coefficient of expansion and method for making same.
US4456500A (en) * 1982-03-02 1984-06-26 Nippon Tenshashi Kabushiki Kaisha Method of manufacturing a polisher
US4745795A (en) * 1986-02-27 1988-05-24 Kraftwerk Union Aktiengesellschaft Apparatus for measuring gases dissolved in water
EP0393312A1 (de) * 1989-04-21 1990-10-24 Dyconex AG Mehrlagige Leiterplatte
EP0476664A2 (de) * 1990-09-20 1992-03-25 Dainippon Screen Mfg. Co., Ltd. Verfahren zur Herstellung von kleinen Durchgangslöchern in dünne Metallplatten

Cited By (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6106923A (en) * 1997-05-20 2000-08-22 Fujitsu Limited Venting hole designs for multilayer conductor-dielectric structures
EP0893822A2 (de) * 1997-07-22 1999-01-27 Daimler-Benz Aktiengesellschaft Verfahren zum Einbetten von metallischen Leitern mikroelektrischer Bauelemente in eine Kunststoffmasse
EP0893822A3 (de) * 1997-07-22 2000-11-22 DaimlerChrysler AG Verfahren zum Einbetten von metallischen Leitern mikroelektrischer Bauelemente in eine Kunststoffmasse
US9942982B2 (en) 1997-08-04 2018-04-10 Continental Circuits, Llc Electrical device with teeth joining layers and method for making the same
WO1999035305A1 (de) * 1998-01-12 1999-07-15 Robert Bosch Gmbh Design- und herstellungsverfahren für eine mikromechanische vorrichtung
US6514670B1 (en) 1998-01-12 2003-02-04 Robert Bosch Gmbh Method for designing and manufacturing a micromechanical device
US6202316B1 (en) 1998-04-14 2001-03-20 Timothy J. Swift Coordinate measuring machine guideway composite structure and method of manufacture
US20050019535A1 (en) * 2000-12-12 2005-01-27 Shri Diksha Corporation Lightweight circuit board with conductive constraining cores
US20050019541A1 (en) * 2000-12-12 2005-01-27 Shri Diksha Corporation Lightweight circuit board with conductive constraining cores
US7667142B2 (en) 2000-12-12 2010-02-23 Stablcor, Inc. Lightweight circuit board with conductive constraining cores
US7635815B2 (en) 2000-12-12 2009-12-22 Stablcor, Inc. Lightweight circuit board with conductive constraining cores
US7550365B2 (en) 2002-04-15 2009-06-23 Hewlett-Packard Development Company, L.P. Bonding structure and method of making
US20030193548A1 (en) * 2002-04-15 2003-10-16 Emery Timothy R. Bonding structure and method of making
US20050151766A1 (en) * 2002-04-15 2005-07-14 Emery Timothy R. Printheads and printhead cartridges using a printhead
US7758169B2 (en) 2002-04-15 2010-07-20 Hewlett-Packard Development Company, L.P. Printheads and printhead cartridges using a printhead
US6871942B2 (en) * 2002-04-15 2005-03-29 Timothy R. Emery Bonding structure and method of making
US20050146565A1 (en) * 2002-04-15 2005-07-07 Emery Timothy R. Bonding structure and method of making
WO2005011345A1 (de) * 2003-07-17 2005-02-03 Ksg Leiterplatten Gmbh Schichtanordnung für ein mit elektronischen bauelementen bestückbares trägerbauteil und verfahren zur herstellung
US20090090465A1 (en) * 2004-05-15 2009-04-09 Vasoya Kalu K Printed wiring board with conductive constraining core including resin filled channels
US20050257957A1 (en) * 2004-05-15 2005-11-24 Kaluk Vasoya Printed wiring board with conductive constraining core including resin filled channels
US20060104035A1 (en) * 2004-08-24 2006-05-18 Vasoya Kalu K Edge plated printed wiring boards
US7301105B2 (en) 2004-08-27 2007-11-27 Stablcor, Inc. Printed wiring boards possessing regions with different coefficients of thermal expansion
US20060063428A1 (en) * 2004-08-27 2006-03-23 Vasoya Kalu K Printed wiring boards possessing regions with different coefficients of thermal expansion
US20060231198A1 (en) * 2005-03-15 2006-10-19 Vasoya Kalu K Manufacturing process: how to construct constraining core material into printed wiring board
USRE45637E1 (en) 2005-08-29 2015-07-28 Stablcor Technology, Inc. Processes for manufacturing printed wiring boards
US20080011507A1 (en) * 2006-07-14 2008-01-17 Vasoya Kalu K Build-up printed wiring board substrate having a core layer that is part of a circuit
US8203080B2 (en) 2006-07-14 2012-06-19 Stablcor Technology, Inc. Build-up printed wiring board substrate having a core layer that is part of a circuit
US9408314B2 (en) 2006-07-14 2016-08-02 Stablcor Technology Inc. Build-up printed wiring board substrate having a core layer that is part of a circuit
US20100304171A1 (en) * 2009-06-02 2010-12-02 Integran Technologies, Inc. Metal-clad polymer article
WO2010139053A1 (en) * 2009-06-02 2010-12-09 Integran Technologies, Inc. Metal-clad polymer article
US8394507B2 (en) 2009-06-02 2013-03-12 Integran Technologies, Inc. Metal-clad polymer article
US8545994B2 (en) 2009-06-02 2013-10-01 Integran Technologies Inc. Electrodeposited metallic materials comprising cobalt
US8906515B2 (en) 2009-06-02 2014-12-09 Integran Technologies, Inc. Metal-clad polymer article
US8911878B2 (en) 2009-06-02 2014-12-16 Integran Technologies Inc. Structural metal-clad polymer article
US20100304065A1 (en) * 2009-06-02 2010-12-02 Integran Technologies, Inc. Metal-clad polymer article
CN102574362A (zh) * 2009-06-02 2012-07-11 英特格兰科技公司 金属包覆的聚合物制品
US20100304179A1 (en) * 2009-06-02 2010-12-02 Integran Technologies, Inc. Electrodeposited metallic materials comprising cobalt
US9004240B2 (en) 2013-02-27 2015-04-14 Integran Technologies Inc. Friction liner
US9332632B2 (en) 2014-08-20 2016-05-03 Stablcor Technology, Inc. Graphene-based thermal management cores and systems and methods for constructing printed wiring boards
US10414446B2 (en) 2016-04-22 2019-09-17 Honda Motor Co., Ltd. Lightweight vehicle pan assembly and method for attachment to vehicle frame via welding
US11351627B2 (en) 2017-01-31 2022-06-07 Eshfartech Ltd. Three-dimensional laminated metallic objects, method and system of making same
US12090728B2 (en) 2017-01-31 2024-09-17 Eshfartech Ltd. Three-dimensional laminated metallic objects with periodically-diffused marking material

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EP0508946A1 (de) 1992-10-14
DE59206797D1 (de) 1996-08-29

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