GB2080729A - A multi-layer metal core circuit board laminate with a controlled thermal coefficient of expansion and method for making same. - Google Patents
A multi-layer metal core circuit board laminate with a controlled thermal coefficient of expansion and method for making same. Download PDFInfo
- Publication number
- GB2080729A GB2080729A GB8116236A GB8116236A GB2080729A GB 2080729 A GB2080729 A GB 2080729A GB 8116236 A GB8116236 A GB 8116236A GB 8116236 A GB8116236 A GB 8116236A GB 2080729 A GB2080729 A GB 2080729A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- circuit board
- laminate
- stabilizing
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/14—Layered products comprising a layer of metal next to a fibrous or filamentary layer
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B3/00—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar form; Layered products having particular features of form
- B32B3/26—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar form; Layered products having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer
- B32B3/266—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar form; Layered products having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer characterised by an apertured layer, the apertures going through the whole thickness of the layer, e.g. expanded metal, perforated layer, slit layer regular cells B32B3/12
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
- B32B7/04—Interconnection of layers
- B32B7/12—Interconnection of layers using interposed adhesives or interposed materials with bonding properties
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2305/00—Condition, form or state of the layers or laminate
- B32B2305/02—Cellular or porous
- B32B2305/028—Hollow fillers; Syntactic material
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2307/00—Properties of the layers or laminate
- B32B2307/30—Properties of the layers or laminate having particular thermal properties
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2457/00—Electrical equipment
- B32B2457/08—PCBs, i.e. printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
Abstract
A multi-layer circuit board laminate is disclosed having a controlled thermal coefficient of expansion which is particularly useful in conjunction with leadless components. The subject invention includes incorporating one or more stabilizing metal sheets (24) into a composite multi-layer circuit board laminate assembly (10). The stabilizing metal sheet(s) function(s) to significantly reduce the circuit board laminate's thermal coefficient of expansion, thereby enabling the laminate to be used in conjunction with leadless electronic components. In addition, a novel method is disclosed for fabricating one embodiment of the subject invention and includes a unique two-step lamination process which permits apertures (26) to be provided in the metal stabilizing layer (24) and allows the bonding epoxy resin (22) to solidify within the apertures (26), while simultaneously preventing the entrapment of air. In another embodiment of the subject invention the stabilizing layer is formed of a composite metal-dielectric laminate enabling the layer to be provided with a non-contiguous floating type pattern. Control circuit is then adjusted to increase the current in the foil or wires to increase the temperature thereof and melt the adhesive so that it flows into the material of the sheets. The current is terminated when the adhesive is fully melted so that the adhesive sets to bond the edge portions of the sheets to the tape. <IMAGE>
Description
SPECIFICATION
A multi-layer metal core circuit board laminate with a controlled thermal coefficient of expansion and method for making same
The subject invention relates to a multi-layer circuit board laminate which includes one or more stabilizing metal sheets for reducing the thermal coefficient of expansion of the laminate. In addition, a novel ,two-step fabrication method is disclosed which permits apertures to be provided in the metal stabilizing layer and prevents the entrapment of air in those apertures as they are filled with epoxy.
Background of the invention
In the prior art, printed circuit board laminates have been utilized as a convenient and low cost means for mounting and interconnecting discrete electrical components. More specifically, printed circuit boards, formed of a dielectric substrate, are provided with conductive metallic pathways which define electrical connections between discrete components mounted thereon. The metal leads of the components may be soldered to the conductive pathways to complete the electrical connections.
The dielectric substrate used to form the printed circuit board is generally glass fiber cloth which has been impregnated with a resin formulation, such as epoxy or polyimide. The thermal coefficient of expansion of the dielectric substrate is significantly greater than that of the discrete components. The dissimilarity between the thermal expansion coefficients has not presented an insurmountable problem heretofore, since the flexibility of the metal leads of the discrete components would compensate for the thermal mismatch.Even in situations where the circuit assemblies are subjected to frequent and great thermal changes or excursions, a manufacturear can compensate for the thermal mismatch by providing a circuit layout design which incorporates expansion loops in the component leads to absorb the varied expansions and contractions of the ele mentsthereby preventing stress on the solder joints which is a major cause of circuit failure.
Recently, manufacturers have developed leadless components such as chip resistors or chip capacitors. When the leadless chip components, generally formed from alumina, are directly affixed to a circuit board orto a conductive layer in a multi-layer laminate assembly, it has been found that the difference in thermal coefficients of expansion between the dielectric substrate and the alumina leadless chip components, has resulted in a high degree of circuit failures. More specifically, the thermal coefficient of expansion for a conventional epoxy glass laminate dielectric substrate is in the range of 15-20 x 10-6 inch per inch per degree
Celsius. In contrast, the alumina chip components have a much lower thermal coefficient of expansion, generally about 6 x 10-6 inch per inch per degree
Celsius.Thus, when a circuit board laminate having leadless components is subjected to high thermal excursions, solder joints between the components snd the laminate freauently failed since there was no flexibility between the components and the laminate to compensate for the varying amounts of expansion. Therefore, it is apparent that it would be desirable to provide a circuit board laminate having a thermal coefficient of expansion which more closely matches the thermal coefficient of expansion of the alumina chip components to prevent failures of the electrical connections. Further, it would be desirable to provide a circuit board laminate which continues to utilize glass epoxy substrates for the circuit board construction since the latter offers considerable cost advantages and are relatively easy to manufacture.
Brief description of the invention
In accordance with the above, a new and improved metal circuit board laminate is disclosed having a reduced thermal coefficient of expansion which is particularly suitable for use in conjunction with leadless components. More specifically, a circuit board laminate is disclosed having a plurality of planar layers which are adhesively connected in a laminate structure via bonding layers formed of epoxy impregnated glass cloth. In a preferred embodiment, the circuit board laminate of the subject invention includes an uppermost planar metallic conductive layerformed of copper foil and a stabilizing layer formed of a metal having a thermal coefficient of expansion less than thermal coefficient of expansion that the composite laminate structure alone would have.A printed circuit board layer, as used in conventional multi-layer applications, is provided and is disposed below the metal stabilizing layer. A lowermost planar metallic conductive layer, similar to the uppermost layer, is disposed below the printed circuit board layer. Both the uppermost and lowermost metallic conductive layers are adapted to accept leadless alumina components. Bonding sheets, formed of resin impregnated glass cloth, are interposed between each of the layers. In accordance with the new and improved method for producing the subject invention initially, the uppermost planar metallic conductive layer and the metal stabilizing layer are separately laminated to form a partial composite structure. Thereafter, the partial composite structure is laminated to the remaining layers to form a complete composite laminate.This unique two-step lamination process insures that through holes formed in the stabilizing layerwill be filled with resin thereby preventing air from becoming trapped therein, as more fully described hereinafter. The resulting circuit board laminate has a thermal coefficient of expansion which is significantly reduced enabling the laminate to be used with leadless components. In another embodiment of the subject invention, the stabilizing layer is formed of a composite metal-dielectric laminate enabling the layer to be provided with a non-contiguous, floating type pattern.
Further objects and advantages of the subject invention will become apparent when taken in conjunction with the detailed description and the accompanying drawings in which:
Figure 1 is an exploded view of the components of the multi-layer circuit board laminate of a first embodiment of the subject invention.
Figure 2 is a partial cross-sectional view of the partial composite laminate structure which results after the first step of the new and improved process for fabricating the subject invention.
Figure 3 is a partial view of the completed multi-layer circuit board laminate of the subject invention illustrating the mounting of both conventional and leadless components thereon.
Figure 4 is an exploded view, similar to Figure 1, illustrating a second embodiment of the multi-layer circuit board of the subject invention, illustrating an alternative form of the stabilizing layer wherein a composite metal-dielectric structure is utilized enabling the layer to be provided with a non-contiguous pattern.
Description of the preferred embodiment
Referring to Figure 1, an exploded view of the multi-layer circuit board laminate of the subject invention is illustrated and is referred to generally by the numeral 10. The laminate consists of an uppermost layer 20 of a conductive metallic material, preferably formed of a copper foil approximately 0.002 inches thick.
Underneath the metallic layer 20 a plurality of bonding sheets 22 are provided which are formed from conventional multi-laminate board material such as resin impregnated fiberglass cloth. The bonding sheets 22 serve as an adhesive and an electrical insulating dielectric material between the metallic layer 20 and the metal stabilizing layer 24 therebelow. The selection of the metal utilized in stabilizing layer 24, which has a lower thermal coefficient of expansion relative to the dielectric layers, is based on the desired coefficient of expansion of the final composite laminate. Priorto lamination, the stabilizing layer 24 is processed for profile and provided with enlarged apertures 26 to provide clearance in the later stages of fabrication when connective through holes are drilled and plated.In a preferred embodiment of the subject invention, the stabilizing layer 24 is copper-plated such that it is suitable for use as a ground or voltage plane, in addition to its primary function of stabilization. Both the upper and lower surfaces of the stabilizing layer 24 may be treated with copper oxide to promote adhesion to the bonding sheets above and below.
A conventional printed circuit board 28 is provided beneath the stabilizing layer 24, with a second bonding layer 30 being disposed therebetween. The printed circuit board is of conventional multi-layered design and is preferably formed of glass cloth which is impregnated with a polyimide or epoxy resin. The circuit board is provided with a plurality of electrical- ly conductive pathways 31 which define the circuit pathways to the components. It is to be understood that while an interior circuit board layer 28 is illustrated it is intended that the scope of the subject include any multilayer laminate structure, where for example, the circuit paths could be provided by etching the upper and/or lower metallic layers 20 and 32.
A lowermost conductive metallic layer 32 is provided with a third bonding layer 34 being interposed between the lowermost conductive layer 32 and the printed circuit board 28. Both the second and third bonding layers 30 and 34, similar to bonding layers 22, are formed from epoxy impregnated glass cloth.
The lowermost conductive layer 32, similar to the uppermost conductive layer 20, is preferably formed of copper foil which is 0.002 inches thick. The upper surface of the conductive layer 20 may be pretreate, with copper oxide to promote adhesion. Both the uppermost and lowermost conductive layers 20 and, 32 are adapted to be used in conjunction with leadless alumina components 34, as well as conven- tional components 36, as illustrated in Figure 3.
In accordance with the subject invention, a new fabrication process is disclosed for the manufacture of the multi-layer circuit board of the subject invention. More particularly, the prior art methods for fabricating multi-layer boards cannot be directly adapted to the subject invention, since the subject invention includes a metal stabilizing layer 24 having relatively large apertures 26 which must be completely filled with epoxy resin during the lamination process. Further, the procedure must prevent any entrapment of air in the apertures.Accordingly, applicant's new method includes a tworstep fabrication process wherein the uppermost metallic layer 20 and the metal stabilizing layer 24 are initially heated and bonded to provide a partial laminate structure, and thereafter the remaining layers are combined and heated to produce a complete laminate structure. More specifically, in the first lamination step, one or more bonding layers 22, formed of resin-impregnated glass cloth, are interposed between the upper metallic layer 20 and the metal stabilizing layer 24. A relatively large amount of epoxy resin is required to completely fill all the apertures 26 in the metal plane. The metallic and stabilizing layers 20, 22 are then laminated such that the resin in the bonding sheets 22 fill up apertures 26, thereby forming a partial laminate structure.This separate, initial lamination step permits the resin to freely flow into apertures 26 without the risk of entrapping air therein, as illustrated in Figure 2.
In the second lamination step, the remaining layers are united with the partial lamination structure and laminated to produce a complete laminate structure, as illustrated in Figure 3. Conventional methods are used to complete the final fabrication 2 such as the drilling and plating of through holes which facilitate the formation of the electrical connections. Thereafter, the metallic layers 20, 22 may be etched and provided with termination pads for leadless components in accordance with standard multi-layer circuit board fabrication.
Test results of the multi-layer circuit board laminate of the subject invention, as illustrated in Figures 1-3, utilizing metal stabilizing layers having thicknesses ranging from 0.005 to 0.015 inches, produced an average thermal coefficient of expansion of approximately 8.9 x 10-6 inch per inch per degree Celsius over a range of -55 to 125 degrees Celsius. The multi-layer circuit board laminaees, asaembled with leadless chip carrier compOflents#3 & t#hstOod more than 400 thermal stress cyclesps il Stri 2132 (thermal cycling of assembie5{#}r:t#i#t#1i{#;b##een 55;##,-#- and 125 degrees Celsius) with no failures in 2000
solder joints.
Referring to Figure 4, there is illustrated a second
embodiment of the subject invention, which, similar- ly to the first embodiment, includes a plurality of
layers which may be laminated to form a multi-layer
metal core circuit board having a controlled thermal coefficient of expansion. More particularly, circuit board 110 includes upper and lowercopperfoil layers 120 and 132 having a thickness of approxi ,mately 0.002 inch. A circuit board layer 128 may be
provided which is formed of a dielectric substrate,
and includes electrically conductive pathways 131
formed thereon. A plurality of layers of bonding
sheets 122, 124 and 134 are interposed between the
other layers to act as a dielectric and to supply the
epoxy resin necessary to secure the laminate struc
ture.
In the second embodiment of the subject inven
tion, a composite stabilizing layer 140, having low
thermal coefficient of expansion characteristics, is
disclosed. More specifically, stabilizing layer 140
consists of a central dielectric substrate 142 and two
outer metallic core layers 144 and 146, laminated
together to form a composite structure. The dielec
tric substrate layer 142 may be a resin-impregnated
glass cloth, while the metal core layers 144 and 146,
each having a thickness in the range of 0.003 to 0.010
inches, are selected based on the desired expansion
characteristics of the final circuit board laminate.
The stabilizing layer 140 of the second embodi
ment of the subject invention provides certain
advantages over a single layer metal core stabilizing
layer. More specifically, and as illustrated in Figure 4,
the configuration of the pattern formed in the metal
core 144 does not have to be contiguous with the
core panel, since the entire core is supported by a
dielectric substrate. Stated differently, the stabilizing
layer 140 may be provided with a "floating type"
core pattern which may include, for example, por
tions 148 that are non-contiguous with the remain
der of the core 144. Another advantage of the
composite stabilizing layer 140 is that during the
lamination process the relatively large open areas
150 of the core layers are more easily filled with
resin.Thus, the danger of air being entrapped in the
open areas 150 is significantly reduced, enabling the
layers to be laminated in a single step. As in the first
embodiment of the subject invention, stabilizing
layer 140 may be plated with an electroconductive
metal, enabling the layer to act as a ground or
voltage plane.
In summary, there is provided a new and im
proved multi-layer circuit board laminate and
method of making the same having a reduced
thermal coefficient of expansion which is particularly
useful in conjunction with leadless components.
More particularly, a multi-layer circuit board lamin
ate is disclosed having one or more metal stabilizing
layers incorporated therein. The circuit board lamin
ate includes uppermost and lowermost layers which
are adapted to accept leadless components. Sand
wiched between the metallic layers is a conventional
printed circuit board layer, and one or more stabiliz ino avers formed from a metal having a low thermal coefficient of expansion. A plurality of bonding sheets, formed of resin-impregnated glass cloth, are interposed between each of the above stated layers to act as an adhesive.In the novel fabrication process, the uppermost metallic layer is initially laminated with the metal stabilizing layer such that the resin in the bonding sheets can flow freely into the apertures provided in the metal stabilizing layer without the risk of entrapping air therein. A partial laminate structure is formed which is then laminated with the remaining layers to form a complete composite laminate structure. The latter structure may be finished according to conventional fabrication methods. The subject invention functions to reduce the thermal coefficient of expansion of the circuit board laminate such that it may be used in conjunction with alumina components which also have low thermal coefficient of expansion characteristics. Further, the use of the metal stabilizing plane provides excellent surface conditions for multi-layer board laminates and in addition, can perform as a ground or voltage plane.
Although the subject invention has been described by reference to preferred embodiments, it will be apparent that many other modifications could be devised by those skilled in the art that would fall within the spirit and scope of the present invention as defined by the appended claims.
Claims (14)
1. A multi-layer metal core circuit board laminate having a controlled thermal coefficient of expansion for use with leadless components, said circuit board comprising:
a plurality of planar layers disposed in face-to-face contacting relationship and bonded together to form a composite laminate structure, wherein at least one of said layers is formed of a dielectric material and wherein at least another of said layers is a stabilizing layer formed of a metal having a lower thermal coefficient of expansion than said dielectric layer whereby said stabilizing layer is capable of controlling the thermal coefficient of expansion of the composite laminate structure.
2. A multi-layer circuit board laminate as recited in claim 1 wherein said stabilizing layer contains at least one through hole.
3. A multi-layer metal core circuit board laminate as recited in claim 2 further including a bonding layer disposed adjacent to said stabilizing layer and consisting of at least one sheet of resin-impregnated glass cloth to facilitate the filling of the or each said hole in said stabilizing layer during lamination.
4. A multi-layer metal core circuit board laminate as recited in claim 1 wherein said stabilizing layer includes at least one resin-filled through hole.
5. A multi-layer metal core circuit board laminate as recited in Claim 2 or 4 wherein the or each said hole is plated with an electroconductive material.
6. A multi-layer metal core circuit board laminate as recited in any preceding Claim wherein said stabilizing layer is copper-plated enabling said layer to function as a voltage plane.
7. A multi-layer metal core circuit board laminate as recited in any preceding Claim wherein the opposed surfaces of said stabilizing layer are treated with copper oxide to promote adhesion to the adjacent layers.
8. A multi-layer metal core circuit board laminate as recited in any preceding Claim wherein said stabilizing layer is formed of composite laminate structure comprising a central dielectric layer and two outer metal layers.
9. A multi-layer metal core circuit board laminate as recited in Claim 8 wherein said outer metal layers of said composite stabilizing layer have a noncontiguous floating pattern formed thereon.
10. A multi-layer metal core circuit board laminate with a controlled thermal coefficient of expansion for use with leadless components, said circuit board comprising:
an uppermost planar metallic conductive layer;
a planar stabilizing layer formed from metal having a low thermal coefficient of expansion;
a planar printed circuit board layerformed of a dielectric substrate;
a lowermost planar metallic conductive layer with said uppermost and lowermost metallic conductive layers being adapted to accept leadless components; and
three planar bonding layers formed of an epoxyimpregnated cloth material, with one said bonding layer being interposed between and contiguous with said uppermost metallic conductive layer and said stabilizing layer, and with a second said bonding layer being interposed between and contiguous with said stabilizing layer and said printed circuit board layer, and with a third said bonding layer being interposed between and contiguous with said printed circuit board layer and said lowermost metallic layer, said bonding layers functioning to adhesively join the other said layers in a composite laminate structure whereby said stabilizing layer functions to control the thermal coefficient of expansion of said laminate structure.
11. A method of making a multi-layer metal core circuit board laminate with a controlled thermal coefficient of expansion for use with leadless components, said method comprising:
providing an uppermost planar metallic conductive layer and a stabilizing layer formed of a metal having a low thermal coefficient of expansion;
providing a bonding layer interposed between said metallic conductive layer and said stabilizing layer, said bonding layer being formed of resinimpregnated glass cloth;
laminating said layers to form a partial composite laminate structure;
providing a printed circuit board layer and a lowermost planar metallic layer;;
providing a second bonding layer between said printed circuit board layer and said lowermost metallic layer, and providing a third bonding layer between the lower surface of said stabilizing layer and the upper surface of said printed circuit board layer, said second and third bonding layers being formed of resin-impregnated glass cloth; and
laminating said layers to provide a complete composite laminate structure.
12. A multi-layer metal core circuit laminate substantially as herein described wfth reference to and as shown in Figures 1 - 3 or Figure 4 of the accompanying drawings.
13. A method of making a multi-layer metal core circuit laminate substantially as herein described with reference to and as shown in Figures 1 - 3 or
Figure 4 of the accompanying drawings
14. A laminate whenever made by the method claimed in Claim 11 or Claim 13.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16282780A | 1980-06-25 | 1980-06-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2080729A true GB2080729A (en) | 1982-02-10 |
Family
ID=22587293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8116236A Withdrawn GB2080729A (en) | 1980-06-25 | 1981-05-28 | A multi-layer metal core circuit board laminate with a controlled thermal coefficient of expansion and method for making same. |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5736897A (en) |
| DE (1) | DE3123964A1 (en) |
| FR (1) | FR2485865A1 (en) |
| GB (1) | GB2080729A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3447520A1 (en) * | 1984-12-27 | 1986-08-14 | Metallwerk Plansee GmbH, Reutte, Tirol | COMPOUND CIRCUIT BOARD, METHOD FOR PRODUCING A COMPOUND CIRCUIT BOARD AND USE OF ALUMINUM OXIDE AS THE INSULATING LAYER OF A COMPOUND CIRCUIT BOARD |
| EP0393312A1 (en) * | 1989-04-21 | 1990-10-24 | Dyconex AG | Multilayer circuit board |
| US5382505A (en) * | 1991-04-10 | 1995-01-17 | Dyconex Ag | Method of making a laminated structure with shear force delamination resistance |
| US6106923A (en) * | 1997-05-20 | 2000-08-22 | Fujitsu Limited | Venting hole designs for multilayer conductor-dielectric structures |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3501372A1 (en) * | 1985-01-17 | 1986-07-17 | Brown, Boveri & Cie Ag, 6800 Mannheim | Substrate for printed-circuit boards |
| DE3536883A1 (en) * | 1985-10-16 | 1987-04-16 | Isola Werke Ag | BASIC MATERIAL FOR PRINTED CIRCUITS |
| CH687490A5 (en) * | 1992-03-25 | 1996-12-13 | Dyconex Ag | Leiterplattenverstaerkung. |
-
1981
- 1981-05-28 GB GB8116236A patent/GB2080729A/en not_active Withdrawn
- 1981-06-19 DE DE19813123964 patent/DE3123964A1/en not_active Withdrawn
- 1981-06-25 JP JP9761681A patent/JPS5736897A/ja active Pending
- 1981-06-25 FR FR8112525A patent/FR2485865A1/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3447520A1 (en) * | 1984-12-27 | 1986-08-14 | Metallwerk Plansee GmbH, Reutte, Tirol | COMPOUND CIRCUIT BOARD, METHOD FOR PRODUCING A COMPOUND CIRCUIT BOARD AND USE OF ALUMINUM OXIDE AS THE INSULATING LAYER OF A COMPOUND CIRCUIT BOARD |
| EP0393312A1 (en) * | 1989-04-21 | 1990-10-24 | Dyconex AG | Multilayer circuit board |
| US5382505A (en) * | 1991-04-10 | 1995-01-17 | Dyconex Ag | Method of making a laminated structure with shear force delamination resistance |
| US6106923A (en) * | 1997-05-20 | 2000-08-22 | Fujitsu Limited | Venting hole designs for multilayer conductor-dielectric structures |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2485865A1 (en) | 1981-12-31 |
| DE3123964A1 (en) | 1982-03-04 |
| JPS5736897A (en) | 1982-02-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |