US5278724A - Electronic package and method of making same - Google Patents

Electronic package and method of making same Download PDF

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Publication number
US5278724A
US5278724A US07/909,520 US90952092A US5278724A US 5278724 A US5278724 A US 5278724A US 90952092 A US90952092 A US 90952092A US 5278724 A US5278724 A US 5278724A
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Prior art keywords
circuitized substrate
conductors
frame
flexible
substrate
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US07/909,520
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Christopher G. Angulas
Thomas E. Kindl
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International Business Machines Corp
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International Business Machines Corp
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Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: ANGULAS, CHRISTOPHER G., KINDL, THOMAS E.
Priority to JP5122211A priority patent/JPH0773152B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits
    • H05K3/363—Assembling flexible printed circuits with other printed circuits by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05—Flexible printed circuits [FPCs]
    • H05K2201/056—Folded around rigid support or component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10568—Integral adaptations of a component or an auxiliary PCB for mounting, e.g. integral spacer element
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector

Definitions

  • the invention relates to electronic packages and particularly to such packages which utilize flexible circuitry and semiconductor devices (chips) as part thereof. Even more particularly, the invention relates to such packages which may be used in the information handling systems (computer) field.
  • these packages may include a chip electrically coupled to one side of a flexible circuit member which is typically of a dielectric, e.g., polyimide, having at least one layer of circuitry, e.g., copper, thereon.
  • a dielectric e.g., polyimide
  • Such a chip may be coupled, electrically, to the flexible circuit member's circuitry using solder, one well known technique currently used by the assignee of the present invention and referred to as a controlled collapse chip connection (a/k/a C4) procedure.
  • the flexible circuit (a/k/a tape) may then be coupled electrically to respective circuitry, e.g., copper pads or lines, formed on the top surface of a printed circuit board or the like.
  • Such boards usually comprised of several layers of dielectric material, e.g., fiberglass-reinforced epoxy resin, interspersed with various conductor levels, e.g., power, signal and/or ground planes, are known in the art and further definition is not believed necessary.
  • Such packages typically utilize a heat sink member which is thermally coupled to the chip to enhance heat removal from the completed package during operation.
  • a heat sink usually comprises a metallic, e.g., aluminum, element located atop the board with appropriate "feet" firmly oriented on the board's upper surface externally of the aforementioned flexible circuit.
  • the heat-generating chip may be thermally coupled to the heat sink using an appropriate thermal adhesive, several of which are known in the art.
  • the heat sink typically includes appropriate fins or the like at designated locations thereon.
  • solder It is known in package assemblies of the type defined above to electrically couple the outer leads of the flexible circuit to the respective conductors on the circuit board using solder.
  • the dielectric material of the flexible circuit member is removed (etched away) along the flexible circuit's periphery to expose the terminal ends of the outer lead conductors.
  • Solder is applied to the board's conductors and the outer leads are aligned therewith and positioned on the solder. Heat is then applied, e.g., using a thermode structure, to effect the solder bond between respective pairs of conductors (flexible circuit and board).
  • the electronic package and method of making same in accordance with the teachings of the instant invention eliminate the need for such dielectric removal (and thus the need for an etching or the like process at this stage), while still assuring precise orientation and electrical coupling (e.g., soldering) of the flexible circuit's outer lead conductors to respective conductors on the package's circuit board structure.
  • the invention is capable of being readily implemented at reduced cost, and is also adaptable to mass production techniques for packaging structures.
  • an electronic package which includes a first circuitized substrate (e.g., a printed circuit board), a frame having at least part thereof positioned a predetermined distance from the board, and a flexible circuit secured to the frame and including at least one part thereof wrapped about the part of the frame located at the spaced distance from the circuit board. Selected ones of conductors on the flexible circuit are coupled, electrically, to respective conductors on the board.
  • a first circuitized substrate e.g., a printed circuit board
  • the package further includes a semiconductor device (e.g., chip) which is electrically coupled to the selected ones of the flexible circuit's conductors, thus providing electrical connection between the chip and the board along predetermined conductive paths, without the need for dielectric removal or the like as has been customary in some prior packages wherein such connections have been utilized.
  • a semiconductor device e.g., chip
  • a method of making an electronic package which comprises the steps of providing a first circuitized substrate (e.g., circuit board), providing a flexible circuitized substrate, securing the flexible circuitized substrate to a frame such that part of the flexible circuit is wrapped about part of the frame, spacedly positioning the part of the frame having the flexible circuit wrapped thereabout at a distance from the circuit board and electrically coupling selected ones of conductors on the flexible circuit to respective conductors on the board, and positioning a semiconductor device (e.g., chip) on the flexible circuit and electrically coupling the chip to the selected ones of the conductors on the flexible circuit.
  • a semiconductor device e.g., chip
  • FIG. 1 is a partial perspective view of an electronic package in accordance with one embodiment of the invention.
  • FIG. 2 is an enlarged view, taken in section, of the package of FIG. 1, including a showing of the apparatus which may be used to assemble at least part of the package;
  • FIG. 3 is a partial perspective view of an electronic package in accordance with another embodiment of the invention.
  • FIG. 4 is an enlarged view, taken in section, of the package of FIG. 3, further illustrating a heat sink member which may form part thereof;
  • FIG. 5 is a partial view, enlarged and in section over the views in FIGS. 2 and 4, illustrating a flexible circuitized substrate in accordance with an alternative embodiment of the invention, having a portion thereof wrapped about the invention's frame.
  • FIG. 1 there is shown an electronic package 10 in accordance with one embodiment of the invention.
  • Package 10 includes a first circuitized substrate 11 which, in a preferred embodiment of the invention, is a multilayered printed circuit board.
  • Such boards are known in the art and typically include at least one (and preferably several) layer of dielectric material 13 (e.g., epoxy resin reinforced with fiberglass) and a plurality of conductive planes (e.g., signal, power and/or ground) as part thereof.
  • dielectric material 13 e.g., epoxy resin reinforced with fiberglass
  • conductive planes e.g., signal, power and/or ground
  • selected ones of the conductors 15 include a substantially rectangular pad 19, forming a predefined pattern (e.g., rectangular) of such pads on surface 17.
  • the pattern depicted in FIG. 1 is for illustration purposes, only, and not meant to limit the present invention.
  • Pads 19, in the embodiment of FIG. 1, are electrically coupled to or form extensions of a plurality of signal lines 21 which, as shown, fan out in a predetermined pattern to thus form the circuitry for the first substrate 11.
  • Conductors 15 are preferably of copper or other known conductive material as used in the art and may be applied using techniques also known in the art for producing circuit boards of the type defined herein. Further description is thus not believed necessary.
  • Package 10 further includes a flexible circuitized substrate 23 which, in turn, includes a second plurality of conductors 25 as part thereof.
  • Flexible circuitized substrate 23 in accordance with a preferred embodiment of the invention, comprises a relatively thin layer of dielectric material 27 (e.g., polyimide) having thereon the conductors 25.
  • Conductors 25 are preferably provided using known techniques in the art of manufacturing flexible circuits, including sputtering or plating on the dielectric layer, and imaging using a suitable photoresist system.
  • the conductive pattern on substrate 23 may be provided by lamination of a metal (e.g., copper) layer to the dielectric layer, using heat and pressure, and possibly an adhesive, followed by imaging with a photoresist and etching.
  • a preferred flexible substrate for use in the invention possessed a dielectric thickness of about 0.002 inch with a corresponding metallic layer having a thickness of about 0.0014 inch, thus giving an overall thickness for the flexible circuit of about 0.0034 inch.
  • an electronic package and a method of assembling same wherein the fine pattern of conductors 25 on the flexible circuitized substrate 23 are precisely aligned and electrically coupled to respective conductors 15 on the first substrate 11.
  • this connection is attainable without the requirement for selective removal of end portions of the flexible substrate's dielectric so as to expose only terminal ends of the conductors 25, as has heretofore been required in some package assemblies using these structures.
  • the invention defines a technique whereby such dielectric removal is eliminated, while still assuring precise alignment and connection in the manner taught herein.
  • a pattern of conductors 25 on the flexible circuitized substrate 23 each having a width of only about 0.005 inch and separated from adjacent such conductors by a distance of only about 0.007 inch are capable of being electrically coupled to corresponding conductors 15 having a width of only about 0.008 inch and spaced from the nearest adjacent such conductor at a distance of only about 0.004 inch.
  • Such close positioning of both pairs of mating conductors as defined herein thus represents a high density pattern of such conductors and further illustrates the preciseness attained using the teachings of the present invention.
  • Device 31 Electrically coupled to the inner lead portions of conductors 25 on substrate 23 is at least one semiconductor device (e.g., chip) 31.
  • Device 31 may be of a known type of semiconductor chip and, in one embodiment of the invention, included the illustrated substantially rectangular, box-like configuration having side dimensions of about 0.500 inch by 0.500 inch and a thickness of only about 0.025 inch.
  • the contact sites located on the underside of the device as illustrated in FIG. 1 are, in accordance with a preferred embodiment of the invention, electrically coupled to the internal terminal ends 33 (FIG. 2) of the conductors 25 using a known soldering operation, referred to in the art as controlled collapse chip connection (a/k/a C4).
  • solder connections are illustrated by the spherical solder balls 32 in FIG. 2.
  • This pattern as shown in FIG. 1 thus includes a plurality of signal lines 37 which extend outwardly from device 31 to the outer periphery of substrate 23. This is also illustrated in FIG. 2 wherein circuit lines 37 are shown to extend substantially flush to the ends of the underlying dielectric 27.
  • circuitry 25 as depicted in FIGS. 1 and 2 is not meant to limit the invention. Specifically, it is also possible to utilize additional layers of such circuitry in accordance with the teachings herein. For example, it is possible to provide an additional conductive plane 26 (e.g., ground) on the opposite side of dielectric layer 27 from that of conductors 25 as shown, to thus enhance the electrical performance capabilities of substrate 23. Selected areas of this underlying conductive plane can be coupled to respective ones of the conductors 25 through known techniques, including the provision of conductive vias or plated through holes, as is known in the art. Attention is directed to FIG. 5 and also the additional description provided below.
  • additional conductive plane 26 e.g., ground
  • interim conductive layers (not shown) as part of the flexible circuitized substrate while still assuring the necessary flexibility thereof.
  • Such interim layers could also be electrically coupled to the upper circuitry 25 using the aforementioned vias or plated through holes, in addition to also being coupled to an underlying conductor layer as described above.
  • FIG. 1 It is understood in FIG. 1 that a portion (that nearest the viewer) of the flexible circuitized substrate 23 as shown in section has been removed for illustration purposes and that this portion would possess a similar configuration to that of the other three corners of this substantially rectangular structure. Similar removal, for illustration purposes, is provided in FIG. 3.
  • package 10 further includes a frame 41 which, as defined herein, includes at least part thereof which is designed for being spacedly positioned from the upper surface 17 of substrate 11 and, significantly, for having a portion of the flexible substrate 23 wrapped thereabout such that the conductors on these wrapped portions will form an electrical connection with respective conductors 15 on substrate 11.
  • Frame 41 as shown in FIGS. 1 and 2, is preferably of substantially rectangular configuration, including four longitudinal sides 43 which define an opening 45 therein. Opening 45, in the embodiment of the invention as depicted in FIGS. 1 and 2, is also of substantially rectangular configuration.
  • the flexible substrate in FIG. 1 it is understood that the two sides nearest the viewer in FIG. 1 converge to form a unitary structure for frame 41, the portions of the sides being removed in FIG. 1 for illustration purposes. Phantom lines are used in FIG. 1 to illustrate the joining of these two nearest sides.
  • frame 41 is comprised of a plastic material (a preferred example of such material being Ryton, a trademark of the Phillips Petroleum Company).
  • plastic materials suitable for use with the present invention include Teflon (a trademark of E. I. duPont de Nemours and Co.).
  • CTE coefficient of thermal expansion
  • the material for frame 41 possess a coefficient of thermal expansion (CTE) which is substantially compatible with that of the dielectric 27 and 13 used for the invention's flexible and first substrates, respectively.
  • CTE coefficient of thermal expansion
  • the aforementioned plastic material possessed a CTE of about 17 p.p.m./degrees Celsius (degrees C.), while the metal-dielectric (copper-polyimide) flexible circuit possessed substantially the same CTE.
  • Use of such an insulative material for frame 41 is also essential in those embodiments of the invention wherein an additional conductive layer (as described above) may be utilized on the under side of the flexible substrate, in addition to the illustrated upper layer of conductors 25, such an embodiment shown in FIG. 5.
  • a metallic material e.g., copper, stainless steel
  • an insulative coating e.g., polyimide
  • a dielectric coating is provided thereon for insulation purposes. Should only a single conductive layer be used for flexible substrate 23, no such additional coating would be necessary.
  • the sides 43 are spaced at a distance ("D") from the lower substrate's upper surface 17. In one embodiment of the invention, this distance was about 0.013 inch. It is also seen in FIG. 2, that semiconductor device 31 is located on the opposite side of the flexible circuit 23 from the provided opening 45 within frame 41. Provision of such an opening serves to reduce the weight of the assembly and to enhance mechanical flexibility.
  • Flexible substrate 23 is positioned on frame 41 and secured thereto using a suitable adhesive.
  • a suitable adhesive for this purpose is sold under the product designation CHR-XA252, and is available from the Chemical Hard Rubber Division of the Furon Company, New Haven, Conn.
  • Such an adhesive is preferably applied to the upper surface of the frame's four sides 43 and the flexible substrate pressed thereon. Additionally, it may also be desirable to place the flexible substrate in tension prior to such attachment using conventional apparatus known in the art. Having the flexible substrate in tension may be considered worthwhile to make the flexible substrate sufficiently planar relative to frame 41.
  • the outer edges of the substrate are wrapped around the frame's outer peripheral edges to form the configuration as illustrated herein. Adhesive is also preferably used on the frame's under surface at these locations to effect final securement.
  • pins 51 may be utilized. As shown in FIG. 2, such pins 51 may be inserted within (or form integral extensions thereof) designated sides 43 of the frame and project upwardly for being positioned within corresponding openings 53 formed within the flexible substrate. In one embodiment, pins made of Ryton may be used, these pins frictionally inserted within corresponding apertures within the designated frame sides. Reinforcement material (e.g., copper, not shown) may be provided on the substrate's upper surface about such apertures, to assist in preventing possible deformation (e.g., tearing) of the relatively thin flexible substrate.
  • Reinforcement material e.g., copper, not shown
  • this subassembly is next aligned with the respective circuitry on the lower, first substrate 11 such that the individual conductors 25 of the flexible substrate will be electrically coupled to respective pads 19 of the conductors 15 on the lower substrate.
  • this aligning and positioning is accomplished using a vacuum device 61 (FIG. 2) which lowers to engage the upper surface of device 31 and thus hold the chip, and the underlying flexible substrate and frame, in an elevated position above the conductors 15. The subassembly is then lowered to engage the conductors 15 in the manner shown in FIG. 2.
  • solder is then formed between the respective aligned pairs of conductors of both circuitized substrates.
  • such permanent connections are formed using solder.
  • solder is applied to the pads 19 using a wave solder process and apparatus known in the industry. Such a procedure causes a wave of solder to be passed by and contact with wettable pads 19, resulting in the deposition of a small amount of this solder on each pad.
  • pads are electrically isolated from each other by a surrounding coating of non-wetting material, one example being Probimer 52, available from the Ciba-Geigy Corporation. (Probimer is a trademark of Ciba-Geigy.)
  • Probimer 52 available from the Ciba-Geigy Corporation.
  • the preferred solder applied using this wave technique was a 63:37 eutectic tin:lead solder, known in the art. With this solder applied to the respective pads 19, the flexible circuit-frame-chip subassembly is then lowered such that the outer, wrapped conductors 25 on the flexible substrate engage respective coated conductors 19.
  • thermodes 71 (FIG. 2) which, as shown in FIG. 2, may constitute extensions of the overall apparatus 73 which includes suction device 61. These thermodes 71 engage the outer peripheries of the wrapped flexible circuitized substrate to apply heat thereto, which heat passes around the conductors 25 to melt the solder and cause it to reflow, causing a substantial mechanical and electrically conductive bond between the subassembly and lower substrate members. Precise positioning of the described subassembly relative to the lower substrate may be accomplished using split optics which key on the lower substrate and subassembly (e.g., at registration points thereof).
  • thermodes proximity hot air thermodes.
  • both lower substrate and subassembly may be placed in a suitable and heated oven. Heating of the flexible circuitized substrate is accomplished, as defined above with the contact thermodes 71, until solder reflow occurs (e.g., at a temperature of about 250 degrees Celsius (C.)). This reflowed solder is represented by the numerals 75 in FIG. 2.
  • a predetermined amount of solder paste is applied to the respective pads 19, preferably using a screening technique, various types of which are known.
  • the subassembly is then located, again using a vacuum apparatus as defined above, such that the flexible substrate's individual conductors align with corresponding pads 19 on the lower substrate.
  • the subassembly is then lowered until contact between respective conductors occurs, following which the paste is then reflowed.
  • Two preferred techniques for accomplishing such paste reflow are to either use directed hot air or to place the subassembly and lower substrate within an oven.
  • a preferred solder paste is 63:37 tin:lead solder paste, available from Alpha Metals, Incorporated. Should an oven be utilized, full reflow of the described solder may be accomplished by placing the subassembly and lower substrate within the oven at a temperature of about 250 degrees C. for approximately 1.5 to five minutes.
  • a heat sink 81 (FIG. 4), which is preferably metallic (e.g., aluminum) and is positioned over the wrapped flexible substrate and frame elements in the manner shown in FIG. 4.
  • a heat sink may include outer leg portions (not shown) which physically engage respective locations on the upper surface of the lower substrate 11.
  • the semiconductor device 31 is preferably thermally coupled to this heat sink using an adhesive, one example being available in the industry from the Minnesota Mining and Manufacturing Company under the trade designation "Scotchcast".
  • Such a composition includes about 47 percent (%) by weight of an epoxy polymer, about 52% by weight of a hardener and flexiblizer mixture, and about 0.4% by weight of a coloring agent.
  • the hardener and flexiblizer mixture contains about 25% to 39% of hexahydrophthalic anhydride, about 50% to about 75% by weight of polypropylene glycol and/or polyoxypropylene glycol flexiblizer, about 0.85% to about 1% by weight of a tertiary amine, and a minor amount of hexahydrophthalic acid.
  • This adhesive is known in the art and further description is not believed necessary.
  • Such an adhesive is represented by the numeral 83 in FIG. 4.
  • Heat sink 81 as is known in the art, may also include a plurality of fins 85 for promoting heat removal.
  • FIGS. 3 and 4 there is shown an electronic package 10' in accordance with an alternative embodiment of the invention.
  • Package 10' is substantially similar to package 10 in FIGS. 1 and 2 with the exception of the addition of a standoff portion 91 at the central location of the frame (now 41') in place of the defined opening 45 for the frame 41 in FIGS. 1 and 2.
  • a substantially solid and planar upper portion for the frame is provided, including, of course, the outer side members (43' in FIGS. 3 an 4) which are spaced (dimension "D") from the lower substrate's upper surface 17.
  • Standoff portion 91 physically engages the upper surface 17 and rests thereon and, significantly, serves to support the semiconductor device 31 such that this device will be maintained at a precise distance from the lower substrate at all times.
  • Standoff can further serve, through appropriate material selection, as a thermal conductor through which heat can be removed from chip 31.
  • Standoff portion 91 is preferably of substantially rectangular configuration and is thus located directly opposite semiconductor device 31. All the remaining elements of package 10' remain the same as those in package 10, and thus similar numerals are used to illustrate such similar elements.
  • Positioning of the flexible substrate-frame-semiconductor device subassembly in the embodiment of FIGS. 3 and 4 is accomplished substantially similarly to that of the subassembly in FIGS. 1 and 2. Further description is thus not believed necessary.
  • Substrate 24' includes the earlier defined upper layer of conductors 25 thereon as located on the described dielectric 27 (e.g., polyimide).
  • Substrate 23' further includes a second conductive layer 26 located on the opposite side of the dielectric 27 from the upper layers of conductors 25.
  • this second, lower layer 26 of conductors may be electrically coupled to respective ones of the conductors 25 (e.g., using a plated through hole 28).
  • the use of additional layers of circuitry further increases the operational capabilities of the present invention.
  • the package includes a flexible circuitized substrate wrapped about an appropriate frame which in turn serves to position the substrate in a precise manner relative to another substrate such that conductors on both substrates may be electrically coupled to form a final package structure.
  • a resulting structure assures high density connections as is highly desired in the packaging industry, and particularly that portion of the industry dedicated to information handling systems (computers).
  • the flexible circuitized substrate of the invention does not require selective removal of portions of the substrate's dielectric (e.g., polyimide) using such a relatively harsh process as etching in order to expose terminal ends of the substrate's conductors.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Cited By (28)

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US5359493A (en) * 1993-07-09 1994-10-25 Texas Instruments Incorporated Three dimensional multi-chip module with integral heat sink
US5362656A (en) * 1992-12-02 1994-11-08 Intel Corporation Method of making an electronic assembly having a flexible circuit wrapped around a substrate
DE4422216A1 (de) * 1993-06-25 1995-01-05 Fuji Electric Co Ltd Mehrlagige metallische Leiterplatte und gegossener Baustein
US5435732A (en) * 1991-08-12 1995-07-25 International Business Machines Corporation Flexible circuit member
US5561323A (en) * 1994-01-28 1996-10-01 International Business Machines Corporation Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
US5633533A (en) * 1995-07-26 1997-05-27 International Business Machines Corporation Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
EP0788158A2 (en) 1996-02-01 1997-08-06 International Business Machines Corporation Electronic Package
US5773884A (en) * 1996-06-27 1998-06-30 International Business Machines Corporation Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
US5825625A (en) * 1996-05-20 1998-10-20 Hewlett-Packard Company Heat conductive substrate mounted in PC board for transferring heat from IC to heat sink
US5847929A (en) * 1996-06-28 1998-12-08 International Business Machines Corporation Attaching heat sinks directly to flip chips and ceramic chip carriers
US5854534A (en) 1992-08-05 1998-12-29 Fujitsu Limited Controlled impedence interposer substrate
WO1999004415A2 (en) * 1997-07-21 1999-01-28 Rambus Incorporated Integrated circuit package
US5876215A (en) * 1995-07-07 1999-03-02 Minnesota Mining And Manufacturing Company Separable electrical connector assembly having a planar array of conductive protrusions
US5896651A (en) * 1994-10-17 1999-04-27 Lsi Logic Corporation Method of mounting microelectronic circuit package
US5960535A (en) * 1997-10-28 1999-10-05 Hewlett-Packard Company Heat conductive substrate press-mounted in PC board hole for transferring heat from IC to heat sink
US6008991A (en) * 1993-12-20 1999-12-28 Lsi Logic Corporation Electronic system including packaged integrated circuits with heat spreading standoff support members
US6020221A (en) * 1996-12-12 2000-02-01 Lsi Logic Corporation Process for manufacturing a semiconductor device having a stiffener member
US6060341A (en) * 1998-01-12 2000-05-09 International Business Machines Corporation Method of making an electronic package
US6075287A (en) * 1997-04-03 2000-06-13 International Business Machines Corporation Integrated, multi-chip, thermally conductive packaging device and methodology
US6107674A (en) * 1993-05-05 2000-08-22 Ixys Corporation Isolated multi-chip devices
WO2000054333A1 (en) * 1999-03-08 2000-09-14 Koninklijke Philips Electronics N.V. Display device
US6147393A (en) * 1993-05-05 2000-11-14 Ixys Corporation Isolated multi-chip devices
EP1054447A1 (en) * 1999-05-21 2000-11-22 The Whitaker Corporation Surface mount millimeter wave IC package
US6234820B1 (en) 1997-07-21 2001-05-22 Rambus Inc. Method and apparatus for joining printed circuit boards
EP1385208A2 (en) * 2002-07-22 2004-01-28 Texas Instruments Incorporated Folded tape area array package with one metal layer
US20060006507A1 (en) * 2003-06-04 2006-01-12 Dong Zhong Silicon building block architecture with flex tape
US20080266819A1 (en) * 2007-04-27 2008-10-30 Fukui Precision Component (Shenzhen) Co., Ltd. Mounting support for a flexible printed circuit board and retaining apparatus having the same
US20100304580A1 (en) * 2009-05-26 2010-12-02 Thomas Baycura Electrical component interface

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US6905342B2 (en) * 2003-04-01 2005-06-14 Hewlett-Packard Development Company, L.P. Protected electrical interconnect assemblies
DE102010060855A1 (de) * 2010-11-29 2012-05-31 Schweizer Electronic Ag Elektronisches Bauteil, Verfahren zu dessen Herstellung und Leiterplatte mit elektronischem Bauteil

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Cited By (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5435732A (en) * 1991-08-12 1995-07-25 International Business Machines Corporation Flexible circuit member
US6102710A (en) 1992-08-05 2000-08-15 Fujitsu Limited Controlled impedance interposer substrate and method of making
US5854534A (en) 1992-08-05 1998-12-29 Fujitsu Limited Controlled impedence interposer substrate
US5362656A (en) * 1992-12-02 1994-11-08 Intel Corporation Method of making an electronic assembly having a flexible circuit wrapped around a substrate
US6107674A (en) * 1993-05-05 2000-08-22 Ixys Corporation Isolated multi-chip devices
US6147393A (en) * 1993-05-05 2000-11-14 Ixys Corporation Isolated multi-chip devices
DE4422216A1 (de) * 1993-06-25 1995-01-05 Fuji Electric Co Ltd Mehrlagige metallische Leiterplatte und gegossener Baustein
US5359493A (en) * 1993-07-09 1994-10-25 Texas Instruments Incorporated Three dimensional multi-chip module with integral heat sink
US6008991A (en) * 1993-12-20 1999-12-28 Lsi Logic Corporation Electronic system including packaged integrated circuits with heat spreading standoff support members
US5561323A (en) * 1994-01-28 1996-10-01 International Business Machines Corporation Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
US5896651A (en) * 1994-10-17 1999-04-27 Lsi Logic Corporation Method of mounting microelectronic circuit package
US5923538A (en) * 1994-10-17 1999-07-13 Lsi Logic Corporation Support member for mounting a microelectronic circuit package
US5876215A (en) * 1995-07-07 1999-03-02 Minnesota Mining And Manufacturing Company Separable electrical connector assembly having a planar array of conductive protrusions
US5633533A (en) * 1995-07-26 1997-05-27 International Business Machines Corporation Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
US5760465A (en) * 1996-02-01 1998-06-02 International Business Machines Corporation Electronic package with strain relief means
US5877043A (en) * 1996-02-01 1999-03-02 International Business Machines Corporation Electronic package with strain relief means and method of making
EP0788158A2 (en) 1996-02-01 1997-08-06 International Business Machines Corporation Electronic Package
US5825625A (en) * 1996-05-20 1998-10-20 Hewlett-Packard Company Heat conductive substrate mounted in PC board for transferring heat from IC to heat sink
US5773884A (en) * 1996-06-27 1998-06-30 International Business Machines Corporation Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
US5847929A (en) * 1996-06-28 1998-12-08 International Business Machines Corporation Attaching heat sinks directly to flip chips and ceramic chip carriers
US6251707B1 (en) * 1996-06-28 2001-06-26 International Business Machines Corporation Attaching heat sinks directly to flip chips and ceramic chip carriers
US6069023A (en) * 1996-06-28 2000-05-30 International Business Machines Corporation Attaching heat sinks directly to flip chips and ceramic chip carriers
US6020221A (en) * 1996-12-12 2000-02-01 Lsi Logic Corporation Process for manufacturing a semiconductor device having a stiffener member
US6075287A (en) * 1997-04-03 2000-06-13 International Business Machines Corporation Integrated, multi-chip, thermally conductive packaging device and methodology
WO1999004415A2 (en) * 1997-07-21 1999-01-28 Rambus Incorporated Integrated circuit package
US6234820B1 (en) 1997-07-21 2001-05-22 Rambus Inc. Method and apparatus for joining printed circuit boards
US6447321B1 (en) 1997-07-21 2002-09-10 Rambus, Inc. Socket for coupling an integrated circuit package to a printed circuit board
WO1999004415A3 (en) * 1997-07-21 1999-04-08 Rambus Inc Integrated circuit package
US6002589A (en) * 1997-07-21 1999-12-14 Rambus Inc. Integrated circuit package for coupling to a printed circuit board
US5960535A (en) * 1997-10-28 1999-10-05 Hewlett-Packard Company Heat conductive substrate press-mounted in PC board hole for transferring heat from IC to heat sink
US6018193A (en) * 1997-10-28 2000-01-25 Hewlett-Packard Company Heat conductive substrate press-mounted in PC board hole for transferring heat from IC to heat sink
US6060341A (en) * 1998-01-12 2000-05-09 International Business Machines Corporation Method of making an electronic package
WO2000054333A1 (en) * 1999-03-08 2000-09-14 Koninklijke Philips Electronics N.V. Display device
EP1054447A1 (en) * 1999-05-21 2000-11-22 The Whitaker Corporation Surface mount millimeter wave IC package
EP1385208A2 (en) * 2002-07-22 2004-01-28 Texas Instruments Incorporated Folded tape area array package with one metal layer
EP1385208A3 (en) * 2002-07-22 2004-03-10 Texas Instruments Incorporated Folded tape area array package with one metal layer
US20060006507A1 (en) * 2003-06-04 2006-01-12 Dong Zhong Silicon building block architecture with flex tape
US20080266819A1 (en) * 2007-04-27 2008-10-30 Fukui Precision Component (Shenzhen) Co., Ltd. Mounting support for a flexible printed circuit board and retaining apparatus having the same
US8009432B2 (en) * 2007-04-27 2011-08-30 Fukui Precision Component (Shenzhen) Co., Ltd. Retaining apparatus for a flexible printed circuit board
US20100304580A1 (en) * 2009-05-26 2010-12-02 Thomas Baycura Electrical component interface
US7845956B1 (en) * 2009-05-26 2010-12-07 Thomas Baycura Electrical component interface

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