US5206585A - Methods for testing integrated circuit devices - Google Patents

Methods for testing integrated circuit devices Download PDF

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Publication number
US5206585A
US5206585A US07/801,213 US80121391A US5206585A US 5206585 A US5206585 A US 5206585A US 80121391 A US80121391 A US 80121391A US 5206585 A US5206585 A US 5206585A
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US
United States
Prior art keywords
integrated circuit
solder bumps
chip
anisotropic conductive
ecpi
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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US07/801,213
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English (en)
Inventor
David D. C. Chang
Edward L. Smith, Jr.
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Nokia Bell Labs
AT&T Corp
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AT&T Bell Laboratories Inc
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Publication date
Application filed by AT&T Bell Laboratories Inc filed Critical AT&T Bell Laboratories Inc
Priority to US07/801,213 priority Critical patent/US5206585A/en
Assigned to AMERICAN TELEPHONE AND TELEGRAPH COMPANY A CORP. OF NEW YORK reassignment AMERICAN TELEPHONE AND TELEGRAPH COMPANY A CORP. OF NEW YORK ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: CHANG, DAVID DER CHI, SMITH, EDWARD L., JR.
Priority to JP4341045A priority patent/JP2735449B2/ja
Application granted granted Critical
Publication of US5206585A publication Critical patent/US5206585A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets

Definitions

  • This invention relates to methods for testing integrated circuit chips and, more particularly, to such methods which employ a layer of anisotropic conductive material for conducting current between solder bumps on the integrated circuit device and conductive pads of a test fixture.
  • Anisotropic conductive material is material in the form of a flat sheet that conducts electrical current across its thickness only and not in the length or width dimensions.
  • the references discuss a particular kind of anisotropic conductive material known as Elastomeric Conductive Polymer Interconnect (ECPI) material which comprises chains of conductive particles which are magnetically aligned in columns in an elastomeric matrix to provide conduction only in the thickness of Z direction. It is known that such materials can be used to provide a dependable interconnection between an array of conductors on a device to be tested with an array of conductors on a test fixture. The electronic device to be tested is typically mechanically compressed against the ECPI material to give dependable electrical interconnection to conductor pads of the test fixture.
  • ECPI Elastomeric Conductive Polymer Interconnect
  • the apparatus is heated to reflow the solder and cause it to adhere to the conductor pads of the substrate so that thereafter the solder bumps constitute both an electrical interconnection and a bonding member for securing the integrated circuit chip to the substrate.
  • Applying the solder bumps to the bonding pads of the integrated circuit can result in malfunctions if placement is not accurate, and so it is customary to test the integrated circuit chip after it has been permanently bonded to the substrate.
  • a drawback of this process is that, if the chip fails test, the solder bumps must be remelted so that the chip can be removed, and remnant solder must be cleaned from the substrate to avoid bridging or short circuits when the chip is replaced.
  • the U.S. patent of Liu et al., U.S. Pat. No. 4,923,521 is an example of prior art describing methods for removing remnant solder.
  • a method for testing an integrated circuit (IC) chip in accordance with the invention comprises the step of forming a solder bump on each of an array of bonding pads on a first surface of the chip, in accordance with the known flip-chip method of IC device packaging.
  • Each of the solder bumps is inserted through an aperture in a spacer member, the spacer member having a smaller thickness than the length of each solder bump, whereby each solder bump protrudes through an aperture.
  • the solder bumps are then placed on a layer of anisotropic conductive material which is arranged over an array of test fixture conductive pads so that the anisotropic conductive layer is sandwiched between the IC chip and the test fixture.
  • the integrated circuit chip is then compressed against the anisotropic conductor material to establish electrical contact between the solder bumps of the integrated circuit chip and the test fixture conductor pads.
  • the testing of the chip then proceeds by passing electrical current through the solder bumps, the anisotropic material, and the test fixture conductor pads in a known manner.
  • the use of the spacer member distributes the strsses within the anisotropic conductive material so as to maintain a proper insulative separation between adjacent conductive elements or columns of the material. It is the bulging of the conductive elements that has been found to lead to anomalous breakdown and other problems leading to unreliability, in the absence of the spacer member.
  • FIG. 1 is a sectional schematic view showing the use of ECPI material for interconnecting solder bumps of an integrated circuit to conductor pads of a test fixture;
  • FIG. 2 is a sectional schematic view showing the use of ECPI materials in accordance with an illustrative embodiment of the invention
  • FIG. 3 is a view of part of the spacer member of FIG. 2;
  • FIG. 4 is a schematic view showing the relationship of solder bump length with thickness of the spacer material of the embodiment of FIG. 2.
  • FIG. 1 there is illustrated a method for testing an integrated chip device 10 using a layer 11 of ECPI material which acts as an anisotropic conductor as described generally in the aforementioned papers of Lambert et al. and Fulton et al. and the patent of Lambert et al.
  • the integrated circuit 10 has an array of bonding pads 13 upon each of which has been formed a solder bump 14 for the purpose of eventually permitting "flip-chip” bonding as generally described in the aforementioned Ingraham et al. paper.
  • the ECPI material 11 overlies a test fixture comprising a substrate 16 containing an array of conductor pads 17.
  • array of solder bumps 14 and the matching array of conductor pads 17 may each constitute a matrix array of conductors as is generally consistent with the apparatus described in the Ingraham et al. paper.
  • the drawing is not intended to be to scale.
  • the purpose of the ECPI material 11 is to provide a temporary interconnection between each solder bump 14 and a corresponding opposite one of the array of conductor pads 17 of the substrate 16.
  • the ECPI material comprises an array of columns 19 of conductors which contain ferromagnetic material for permitting them to be magnetically aligned within a polymer matrix. That is, the conductive columns are made by impressing a magnetic field through the material with the polymer in a fluid uncured condition to permit the particles to form the columns 19 which are fixed in place by allowing the polymer matrix to harden, thereby forming the ECPI material 11.
  • a compressive force schematically shown by arrow 20 is applied to the integrated circuit chip 10, as shown, to force the solder bumps 14 to make good electrical contact with conductive columns 19.
  • our experience with the apparatus of FIG. 1 is that it is generally unreliable, at least for testing integrated circuits having a fine pitch. That is, if the center-to-center distance of the bonding pads is sufficiently close together so as to require a distance between adjacent columns 19 of about eight mils, the ECPI material is considered fine pitch material having a pitch equal to eight mils.
  • the solder bumps 14 each may have a nominal length of about four mils.
  • this problem is solved by using a spacer member 22 between the integrated circuit chip 10 and the ECPI layer 11.
  • This spacer member 22 reduces the penetration of the solder bumps 14 into the ECPI material 11, and it translates applied forces to the ECPI layer between adjacent solder bumps 14, thereby reducing the generation of component forces in the X and Y directions.
  • the distortion of the vertical conductor columns 19 is greatly reduced so that the conduction paths between solder bumps 14 and conductor pads 17 are made more reliable.
  • current from a test source 23 can be conducted through the integrated circuit 10, the solder bumps 14, and the conductor columns 19 to the conductor pads 17 of the test fixture for giving reliable readings of test current through the integrated circuit.
  • the spacer also protects the chip 10 from the ECPI layer 11 to prevent possible contamination of the chip surface by particles from the ECPI layer.
  • the spacer member 22 should then be made with apertures 25 each of which corresponds to the location of one of the solder bumps 14.
  • the apertures 25 are of sufficient diameter, typically less than about ten mils, to permit each of the solder bumps 14 to protrude through the aperture as shown in FIG. 2.
  • the spacer member 22 may be made of any of various materials such as polyimide, and the apertures 25 may be made in any of various ways.
  • the apertures may be made by photolithographic masking and etching or, alternatively, they may be made by laser drilling.
  • the aperture spacing of course reflects the solder bump spacing which is typically less than fifteen mils center-to-center.
  • FIG. 4 shows the relationship of the length L of the solder bump 14 with respect to the thickness t of the spacer 22 and the compression d of the ECPI material during operation. It is assumed that there is substantially no compression of the spacer 22, although this is not essential to the operation of the invention.
  • the thickness t should be smaller than the length L so that each of the solder bumps 14 can protrude through an aperture 25 under compression.
  • the compression d should be sufficient to insure good electrical contact but should not be so great as to produce significant bulging as was discussed with reference to FIG. 1.
  • L may be four mils
  • t may be three mils
  • d may be one mil.
  • solder bumps 14 have a typical thickness of about 0.8 microns, while bonding pads 17 may have a thickness of 0.7 to 1.4 mils.
  • the invention while it is particularly applicable to the testing of flip-chip integrated circuits, is applicable to any electronic device in which the protruding of conductors or the like causes lateral or transverse forces on the conductive columns, as described with reference to FIG. 1.
  • the invention may be used with anisotropic conductors other than ECPI layers, such as anisotropic conductors that use metal pins extending across the layer thickness to provide unidirectional interconnection.
  • anisotropic conductors other than ECPI layers, such as anisotropic conductors that use metal pins extending across the layer thickness to provide unidirectional interconnection.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
US07/801,213 1991-12-02 1991-12-02 Methods for testing integrated circuit devices Expired - Lifetime US5206585A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US07/801,213 US5206585A (en) 1991-12-02 1991-12-02 Methods for testing integrated circuit devices
JP4341045A JP2735449B2 (ja) 1991-12-02 1992-11-30 電子デバイスの試験方法

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US07/801,213 US5206585A (en) 1991-12-02 1991-12-02 Methods for testing integrated circuit devices

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US5633122A (en) * 1993-08-16 1997-05-27 Micron Technology, Inc. Test fixture and method for producing a test fixture for testing unpackaged semiconductor die
US5661042A (en) * 1995-08-28 1997-08-26 Motorola, Inc. Process for electrically connecting electrical devices using a conductive anisotropic material
US5672979A (en) * 1994-10-03 1997-09-30 Motorola, Inc. Method of using an anisotropically conductive material to locate alignment of a semiconductor substrate
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US5701666A (en) * 1994-08-31 1997-12-30 Motorola, Inc. Method for manufacturing a stimulus wafer for use in a wafer-to-wafer testing system to test integrated circuits located on a product wafer
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US20100219528A1 (en) * 2007-04-13 2010-09-02 Texas Instruments Incorporated Electromigration-Resistant Flip-Chip Solder Joints
US20110092066A1 (en) * 1997-05-27 2011-04-21 Mackay John Bumping Electronic Components Using Transfer Substrates
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US8518304B1 (en) 2003-03-31 2013-08-27 The Research Foundation Of State University Of New York Nano-structure enhancements for anisotropic conductive material and thermal interposers
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US6127195A (en) * 1993-09-03 2000-10-03 Micron Technology, Inc. Methods of forming an apparatus for engaging electrically conductive pads and method of forming a removable electrical interconnect apparatus
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US5500605A (en) * 1993-09-17 1996-03-19 At&T Corp. Electrical test apparatus and method
US5798655A (en) * 1993-12-17 1998-08-25 Nhk Spring Co., Ltd. Contact probe unit including needle members urged by a resilient material block
US5680057A (en) * 1994-01-06 1997-10-21 Hewlett-Packard Company Integrated circuit testing assembly and method
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US6255213B1 (en) 1994-03-07 2001-07-03 Micron Technology, Inc. Method of forming a structure upon a semiconductive substrate
US5849633A (en) * 1994-03-07 1998-12-15 Micron Technology, Inc. Electrically conductive projections and semiconductor processing method of forming same
US6577148B1 (en) 1994-08-31 2003-06-10 Motorola, Inc. Apparatus, method, and wafer used for testing integrated circuits formed on a product wafer
US6411116B1 (en) 1994-08-31 2002-06-25 Motorola, Inc. Method for testing a product integrated circuit wafer using a stimulus integrated circuit wafer
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US5672979A (en) * 1994-10-03 1997-09-30 Motorola, Inc. Method of using an anisotropically conductive material to locate alignment of a semiconductor substrate
US5627730A (en) * 1994-11-30 1997-05-06 Ncr Corporation Printed circuit board assembly for high speed data transfer
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