US5117427A - Communication system with concatenated coding error correction - Google Patents

Communication system with concatenated coding error correction Download PDF

Info

Publication number
US5117427A
US5117427A US07/318,152 US31815289A US5117427A US 5117427 A US5117427 A US 5117427A US 31815289 A US31815289 A US 31815289A US 5117427 A US5117427 A US 5117427A
Authority
US
United States
Prior art keywords
data
path metric
coding
sync
words
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US07/318,152
Other languages
English (en)
Inventor
Makoto Miyake
Toshiharu Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63051167A external-priority patent/JP2563961B2/ja
Priority claimed from JP63205551A external-priority patent/JPH0253330A/ja
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA, A CORP. OF JAPAN reassignment MITSUBISHI DENKI KABUSHIKI KAISHA, A CORP. OF JAPAN ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: KOJIMA, TOSHIHARU, MIYAKE, MAKOTO
Application granted granted Critical
Publication of US5117427A publication Critical patent/US5117427A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/186—Phase-modulated carrier systems, i.e. using phase-shift keying in which the information is carried by both the individual signal points and the subset to which the individual signal points belong, e.g. coset coding or related schemes

Definitions

  • This invention relates to communication systems with error correction using concatenated coding scheme and, more particularly, to improvements in a communication system adopting concatenated coding involving the inner code obtained by convolutional coding with Viterbi decoding and the outer code obtained by a Reed-Solomon coding, which realizes powerful error correcting capability in a low CNR (carrier-to-noise power ratio) channel as in space communications.
  • CNR carrier-to-noise power ratio
  • Space communication channels handle weak received electromagnetic waves, so they adopt error correction systems to minimize power required to obtain a pre-determined channel quality.
  • the system comprises a transmitter 40 and a receiver 41.
  • reference number 1 indicates digital input data which can take a value of either "0" or "1"; 2 indicates a Reed-Solomon (hereinafter referred to as RS) encoder/interleaver; 3 shows RS coded data, 8 shows a convolutional encoder; 9 and 10 show convolutionally encoded data (channels P and Q, respectively), 38 is a quarternary phase-shift keying (hereinafter referred to as QPSK) modulator; 15 is the transmitted signal, 16 is a transmission frame signal for controlling the RS encoder/interleaver; 18 is the received signal; 39 is a QPSK demodulator, 23 and 24 are demodulated data on the channels P and Q (respectively); 25 is an RS decoder/deinterleaver, 29 is the fully decoded data, and 21 is a self-synchronization circuit for the Viterbi decoder 25.
  • RS Reed-Solomon
  • 3 shows RS coded data
  • 8 shows a convolutional encoder
  • the operation of the transmitter 40 will be described first.
  • the input data 1 is supplied to the RS coder/interleaver 2 for RS coding followed by interleaving.
  • Parameters of the RS coding are, for example,
  • the timing of RS coding and interleaving are controlled by the transmission frame signal 16.
  • the RS coded data 3 is then supplied to the convolutional encoder 8 for convolutional coding.
  • the convolutionally coded data 9 and 10 are supplied to the QPSK modulator 38 for QPSK modulation to produce transmitted signal 15.
  • the received signal 18 is supplied to the QPSK demodulator 39, which produces the demodulated data 23 and 24 in two channels, P and Q.
  • the demodulated data 23 and 24 are supplied to the Viterbi decoder 25, which produces the Viterbi decoded data 27, corresponding to the output of convolutional encoder 8.
  • the Viterbi decoded data 27 is supplied to the RS decoder/deinterleaver 28 for deinterleaving in correspondence with the interleaving in the transmitter, and then RS decoded with the timing thereof controlled by the Viterbi decoded data 27 to obtain decoded data 29.
  • the demodulated data 23 and 24 on the two channels P and Q are interchanged.
  • the receiver's reference phase is skipped by 90 degrees
  • Q data appears on the P line while logically inverted P data appears on the Q line
  • "-" indicates logical inversion, i.e., 01 appears in place of 00, 11 appears in place of 01, 10 appears in place of 11, etc.
  • Such a phenomenon leads to loss of synchronization in the Viterbi decoder, resulting in a failure of normal operation of the Viterbi decoder 25.
  • the self-synchronization circuit 21 detects such an out of-sync condition and recovers the synchronization of the Viterbi decoder 25.
  • FIG. 16 shows theoretical bit error rate performance. It will be seen in FIG. 16 that the communication system using concatenated coding, of FIG. 15, enables us to greatly reduce the CNR (carrier-to noise power ratio) necessary for obtaining a desired quality of bit error rate.
  • the demodulator is assumed to perform a 8-level soft decision to provide 8-level decision data as demodulated data 23 and 24.
  • E b represents the signal energy per bit of the input data 1
  • N 0 is the single sided noise power spectral density of white Gaussian noise in the transmission channel.
  • this type of concatenated error correction coding communication system has high capability of error correction, and is applicable to earth stations in space communication systems with small sized antennas where the CNR's of their transmission channels are considerably low.
  • the Viterbi decoder 25 will now be described.
  • FIG. 17 is a block diagram showing a prior art Viterbi decoder, which is disclosed in A. Shenoy and P. Johnson "Serial implementation of Viterbi decoders," COMSAT Tech. Rev., Vol. 13, No. 2, pp. 315-330 (Fall 1983).
  • reference numeral 101 designates soft decision data; 102, a branch metric calculation circuit; 103, branch metrics; 104, an adder; 105, a comparator; 106, a selector; 107, path metric before normalization; 112, a subtrahend; 113, a subtractor; 114, path metric data after normalization; 115, a register, 116, path metric after normalization; 117, an ACS (add compare-select) circuit; 118, a trellis connection signal; 121, a path memory; 122, Viterbi decoded data; 124, a minimum value detector; and 125, maximum likelihood (ML) state signal.
  • ML maximum likelihood
  • the branch metric calculation circuit 102 first calculates branch metrics 103. More specifically, with respect to soft decision data 101 produced from the received signal, the Viterbi decoder calculates branch metrics 103 representing the likelihood of each possible coded data. Without loss of generality, we consider that a branch metric 103 takes on a non-negative value, and its maximum likelihood value is equal to zero.
  • the ACS circuit 117 performs the path metric calculation, which consists of the following two main functions:
  • the normalized path metrics 114 thus obtained are stored in the register 115 and are supplied to the adder 104 at the next time instant.
  • the result of comparison and selection of path metrics information in the ACS circuit 117 is the output signal of the comparator 105 and is referred to as a trellis connection signal.
  • the trellis connection signal is provided to the path memory 121.
  • the path memory 121 produces the Viterbi decoded data from the trellis connection signal 118 stored in the path memory 121 on the basis of the ML state signal 125.
  • the RS encoder/interleaver 2 and RS decoder/deinterleaver 28 are disclosed in greater detail in G. C. Clark, Jr., and J. B. Cain “Error-Correction Coding for Digital Communications," Plenum Press, 1981.
  • the Viterbi decoder 25 and self-synchronization circuit 21 are disclosed in detail in Y. Yasuda et al., "Development of variable-rate Viterbi decoder and its performance characteristics," 6th Int. Conf. Digital Satellite Commun., Phoenix, Ariz., pp. XII. 24-XII. 31, Sept., 1983.
  • the concatenated error correction coding system has the self-synchronization circuit 21 for detecting out-of-sync condition and recovering synchronization as noted before, a long time interval is often required to recover the synchronization, which often amounts to several hundreds of bits. Such long time intervals deteriorate the characteristics of the Viterbi decoder and the degraded bit error rate of the decoded data 29 becomes greater than the theoretical value, is described in the above-noted IEEE treatise by Liu and Lee.
  • the prior art Viterbi decoder presents a problem when its operating speed is increased. More specifically, increasing speed requires enormous hardware for the minimum value detector 124. Maximum operating speed of the Viterbi decoder is, therefore, limited in practice.
  • the hardware of the path memory 121 is increased, although it is possible to increase the operating speed by simplifying the scheme of state selection.
  • An object of the invention is to provide a concatenated error correction compensation communication system, which can realize satisfactory bit error rate performance without causing loss of synchronization even in the situation where cycle skip of the recovered carrier occurs in the demodulator.
  • Another object of the invention is to provide a Viterbi decoder, which permits effective normalization of path metrics in an ACS circuit with simple hardware and which also functions to permit detection of the ML state with high probability so that it is suited for realizing satisfactory bit error rate performance in high speed operation.
  • the concatenated error correcting coding communication system includes a differential encoder provided between an RS encoder/interleaver and a convolutional encoder and a differential decoder provided between a Viterbi decoder and a RS decoder/deinterleaver.
  • the 2-channel output of the convolutional encoder is supplied to a parallel-to-serial converter, synchronization words (sync-words) are inserted in gaps of the coded data to produce a continuous bit sequence, and the bit sequence is transmitted after BPSK (binary phase shift keying) modulation.
  • the received signal is BPSK demodulated; the sync-words are detected and removed; the demodulated data produced in this way are supplied after serial-to-parallel conversion to a Viterbi decoder; the RS decoder/deinterleaver completes decoding, operating on the basis of the timing of detection of the sync-words. Even if cycle skip of the recovered carrier occurs in the demodulator, satisfactory bit error rate performance can be realized without loss of synchronization.
  • FIG. 1 is a block diagram showing a transmitter of a first embodiment of the concatenated error correction coding communication system according to the invention
  • FIG. 2 is a block diagram showing one embodiment of a convolutional encoder contained in the transmitter shown in FIG. 1;
  • FIG. 3 is a block diagram showing a receiver in the first embodiment
  • FIG. 4 comprised of FIGS. 4a-4e, is a time chart showing signal formats in various parts of the transmitter shown in FIG. 1;
  • FIG. 5, comprised of FIGS. 5a-5e, is a time chart showing signal formats in various parts of the receiver shown in FIG. 3;
  • FIG. 6 is a graph showing the results of measurements of the bit error rate performance in one embodiment of the invention.
  • FIG. 7 is a block diagram showing a second embodiment of the invention, with a differential coding termination circuit
  • FIG. 8 is a block diagram showing one embodiment of the Viterbi decoder according to the invention.
  • FIG. 9 is a block diagram showing one embodiment of the path metric conversion circuit shown in FIG. 8;
  • FIG. 10 is one embodiment of the threshold signal generator shown in FIG. 9;
  • FIG. 11 is a truth table showing the operation of the threshold signal generator shown in FIG. 10;
  • FIG. 12 is a graph showing bit error rate performance for (255, 223) Reed-Solomon code and (146, 130) Reed-Solomon code, when the differential coding is not employed;
  • FIG. 13 is a graph showing bit error rate performance for (255, 223) Reed-Solomon code and (146, 130) Reed-Solomon code, when the differential coding is employed;
  • FIG. 14 is a graph showing the missed detection probability of the synchronization word
  • FIG. 15, comprised of FIGS. 15a and 15b, is a block diagram showing a prior art concatenated error correction coding communication system
  • FIG. 16 is a graph showing theoretical bit error rate performance of the concatenated error correction coding communication system.
  • FIG. 17 is a block diagram showing a prior art Viterbi decoder.
  • FIG. 1 is a block diagram showing a transmitter of a first embodiment of the concatenated error correction coding communication system according to the invention.
  • reference numeral 4 designates a differential encoder, 5 a modulo 2 adder, 6 a one-bit delay element, 7 differentially coded RS coded data, 11 a parallel-to-serial converter, 12 a modulo 2 adder, 13 BPSK modulator input data, 14 a BPSK modulator, and 17 a sync word generator.
  • FIG. 2 is a block diagram showing a convolutional encoder 8.
  • 32a to 32g are registers, each of which providing a delay for one-bit;
  • 33a to 33h are modulo 2 adders.
  • each of the data output on channels 9 and 10 is also logically inverted.
  • ⁇ c k ⁇ c 0
  • c 1 . . . is output on channel 9.
  • FIG. 3 is a block diagram showing a receiver of the first embodiment of the system showing in FIG. 1.
  • reference numeral 19 designates a BPSK demodulator, 20 demodulated data, 22 a serial-to-parallel converter, 26 a differential decoder, 30 sync-word detector, and 31 receiving frame signal corresponding to the transmitting frame signal 8.
  • FIG. 4 is a time chart showing signal formats in various parts of the transmitter shown in FIG. 1.
  • FIG. 5 is a time chart showing signal formats in various parts of the receiver shown in FIG. 2.
  • the input data 1 is supplied to the RS encoder/interleaver 2 for RS coding and subsequent interleaving to obtain RS coded data 3.
  • the differentially coded data 7 provided from the differential encoder 4 is supplied to the convolutional encoder 8, which generates convolutionally coded data 9 and 10 in two channels.
  • the output of the parallel-to serial converter is supplied to the adder 12, where sync-words having sharp autocorrelation property are inserted in each of the gaps (guard times intervals) of the coded data to obtain modulator input data 13.
  • the modulator input data 13 is supplied to the BPSK modulator 14 for BPSK modulation to obtain transmitted signal 15.
  • the guard time interval is filled with a data sequence having either all "0" pattern or all "1" pattern. This is because at the start of the guard time interval the value of the last bit of the RS coded data 7 stored in the delay element 6 determines the value of the succeeding data sequence in the guard time interval after the differential coding.
  • the convolutional encoder 8 effects convolutional coding continuously on the differentially coded, RS coded data 7 including the data sequence in the guard time interval. Thereafter, the adder 12 inserts a sync-word into portion of the data sequence corresponding to the guard time interval, thus producing the modulator input data 13.
  • the sync-word is inserted through a modulo 2 adder 12.
  • a n is supplied to the BPSK modulator 14 if the data sequence in the differentially coded, RS coded data in the guard time interval has all "0" pattern.
  • Data ⁇ a n * ⁇ (a 1 *, a 2 *, . . . , a n *) is supplied if the data sequence in the guard time interval has all "1" pattern.
  • the demodulator establishes synchronization by detecting the absolute value of the correlation function of the sync-word. Consequently, transmitting the logically inverted sync word ⁇ a n * ⁇ is essentially equivalent to transmitting the sync word ⁇ a n ⁇ in the transmitter.
  • the sync-word detector 30 detects sync words in the demodulated data 20 to produce the receiving frame signal 31.
  • the sync-word detector 30 can be readily realized on the basis of a unique word detector which is employed in currently practiced TDMA (time-division multiple-access) space communication systems.
  • sync-word generator 17a generates sync-words according to the received frame signal 31, which are added to the demodulated data 20 by modulo 2 addition in the adder 12a. In this way, the sync-words are removed from the demodulated data 20, and the data sequence in the guard time interval is changed either to the all "0" pattern or to all "1" pattern.
  • a cycle skip in the recovered carrier occurs in the BPSK demodulator 19
  • the values of the input data 23 and 24 to the Viterbi decoder are changed. More specifically, when the phase of the recovered carrier skips from 0 degrees to 180 degrees, all the bits of the input data 23 and 24 to the Viterbi decoder inclusive of the data sequence in the guard time interval are logically inverted.
  • the recovered carrier may assume four different phases: 0 degrees, 90 degrees, 180 degrees and 270 degrees.
  • the recovered carrier may assume only two different phases of 0 degrees and 180 degrees.
  • the present invention is free from the phenomenon such that data expected in channel Q appears in channel P with respect to the demodulated data 23 and 24 in the two output channels of serial-to-parallel converter 22, due to a cycle skip of 90 degrees of the recovered carrier.
  • the self-synchronization circuit 21 is unnecessary for continuous operation of the Viterbi decoder 25 inclusive of the guard time intervals.
  • the output data of the Viterbi decoder 25 is provided to the differential decoder 26 to provide differentially decoded, Viterbi decoded data 27a.
  • This data 27a is provided to the RS decoder/deinterleaver 28 for decoding to obtain decoded data 29.
  • the RS decoder/deinterleaver 28 can operate independently of the recovered carrier phase, because the differentially decoded, Viterbi decoded data 17a has the same value independent of whether the recovered carrier phase is 0 degrees (correct) of 180 degrees (skipped).
  • the first embodiment of the concatenated error correction coding communication system is continuously operable without losing synchronization caused by occurrence of a recovered carrier cycle skip.
  • the differential coding and decoding are incorporated as means for realizing this, the deterioration of the bit error rate performance due to the incorporation is very slight. This is due to the fact that an error pattern after Viterbi decoding is only bursty, and that the RS decoder has burst error correcting capability.
  • FIG. 6 shows the results of measurement of bit error rate performance.
  • the parameters of codes shown in FIG. 6 are the same as in the case of FIG. 16. Further, as in the case of FIG. 16, 8-level soft decision is done in the demodulation process.
  • a second embodiment of the invention may be applied to burst mode communication.
  • the convolutionally coded data 9 and 10 in the guard time interval are either all “0" or all "1" and not fixed.
  • a differential coding termination circuit 34 is provided between the RS encoder 2 and differential encoder 4 as shown in FIG. 7 so that it is possible to fix all the values in the guard time interval to "0".
  • FIG. 7 is a block diagram including a differential coding termination circuit.
  • reference numeral 34 designates the differential coding termination circuit, 35 a modulo 2 adder, 36 a one-bit delay element, and 37 a selector.
  • the adder 35 and the delay element 36 constitute a circuit similar to the differential encoder 4. For this reason, the same data as the RS coded data 7 stored in the delay element 6 in the differential encoder 4 is stored in the delay element 36 except in the guard time interval.
  • the selector forwards the RS coded data 3 to the differential encoder 4, with one exception; the selector 37 selects one bit of data stored in the delay element 36 to the end of the RS coded data 3 at the start of guard time interval.
  • FIG. 8 is a block diagram showing one embodiment of the Viterbi decoder according to the invention.
  • FIG. 9 is a schematic showing an example of the path metric conversion circuit 108.
  • reference numeral 123 designates a threshold signal generator.
  • FIG. 10 is a circuit diagram showing an embodiment of the threshold signal generator 23.
  • designated as 126a and 126b are AND gates, and 127a to 127c are OR gates.
  • FIG. 11 is a truth table showing the operation of the threshold signal generator showing in FIG. 10.
  • the portion excluding the function for providing the discrimination signal ⁇ k .sup.(i) ⁇ may be attained by using a path metric conversion circuit in an embodiment of the aforenoted patent application entitled "Add Compare-Select Circuit.”
  • the path metrics ⁇ G k .sup.(i) ⁇ 107 before normalization is provided to a path metric conversion circuit 108 and converted into threshold signals ⁇ k .sup.(i) ⁇ 109.
  • the subtrahend generator 111 detects the minimum value among the threshold signals ⁇ .sup.(i) ⁇ 109 as the subtrahend ⁇ k 112.
  • the threshold signal generator 123 consists of the circuit as shown in FIG. 10, and its operation is expressed as a truth table as shown in FIG. 11.
  • the path metric conversion circuit 108 is discussed in detail in M. Miyake, T. Fujino and K. Fijuwara, "Compression of path metrics in Viterbi decoders," in Proc. GLOBECOM' 87 Tokyo, Japan, pp. 43.2.1-43.2.5, Nov. 1987.
  • Such path metric conversion circuit 108 has the following two main features:
  • the subtrahend generator 111 having a function to detect the minimum threshold value can be realized with simple hardware.
  • the minimum value can be readily obtained by taking the AND of corresponding bits in the threshold signals ⁇ k .sup.(i) ⁇ as shown in the literature. This is obvious from the truth table shown in FIG. 11.
  • the ML state or its equivalent state can be detected using simple hardware, as seen from the following. Since the minimum of the path metrics G k .sup.(i) 107 before normalization takes a small value, the minimum value of the threshold signal ⁇ .sup.(i) k ⁇ becomes zero with high probability. Particularly, where CNR of the received signal is moderately high, the minimum value of the path metric ⁇ G.sup.(i) k ⁇ before normalization assumes zero with probability high enough.
  • the discrimination signal ⁇ k .sup.(i) ⁇ is a signal representing a state having a path metric of G k .sup.(i) ⁇ 1.
  • the state signal generator 119 provides a state signal 120 representing the ML state or its equivalent state.
  • the state signal 120 can represent the ML state with high probability.
  • the state signal generator 119 for producing the state signal from the discrimination signal ⁇ .sup.(i) k ⁇ 110 can be readily realized by using the TTL IC "8N74LS148" by Texas Instruments or the FAST TTL IC “74F148” by Signetics.
  • the above embodiment has been concerned with a path metric conversion circuit with a threshold generator as shown in FIG. 10.
  • a path metric conversion circuit shown in the applied patent "Add-Compare-Select circuit" it is possible to use a path metric conversion circuit shown in the applied patent "Add-Compare-Select circuit" to obtain the same effects as in the above embodiment.
  • bit error rate performance shown in FIGS. 12 and 13 the bit error rate performance realized by the above two kinds of Reed-Solomon coding are substantially the same. Further, this embodiment uses a 225-bit sync word.
  • FIG. 14 shows the results of measurement of the sync word missed detection probability on the receiving side.
  • the concatenated error correction coding system can realize BER of 10 -6 at Eb/N 0 ⁇ 3.0 dB. Meanwhile, at this operating point, the sync word missed detection probability is sufficiently small, so that stable synchronization performance can be obtained.
  • the Viterbi decoder includes, instead of a complex minimum value detection circuit for detecting the minimum path metric, there is a circuit for converting the path metric using pre-determined rules, a circuit for generating a subtrahend for normalization from the output of the path metric conversion circuit using simple hardware, and a circuit for detecting the ML state or its equivalent state from the output signal of the path metric conversion circuit with high probability. It is thus possible to reduce the hardware of the ACS circuit in the Viterbi decoder and produce decoded data having satisfactory bit error rate performance without increasing hardware of the path memory. It is thus possible to realize a Viterbi decoder suited for high speed operation.

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Algebra (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
US07/318,152 1988-03-03 1989-03-02 Communication system with concatenated coding error correction Expired - Lifetime US5117427A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP63-51167 1988-03-03
JP63051167A JP2563961B2 (ja) 1988-03-03 1988-03-03 ビタビ復号器
JP63205551A JPH0253330A (ja) 1988-08-18 1988-08-18 連接符号化誤り訂正通信装置
JP63-205551 1988-08-18

Publications (1)

Publication Number Publication Date
US5117427A true US5117427A (en) 1992-05-26

Family

ID=26391701

Family Applications (1)

Application Number Title Priority Date Filing Date
US07/318,152 Expired - Lifetime US5117427A (en) 1988-03-03 1989-03-02 Communication system with concatenated coding error correction

Country Status (3)

Country Link
US (1) US5117427A (ja)
FR (1) FR2628587B1 (ja)
GB (1) GB2216753B (ja)

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258987A (en) * 1992-04-16 1993-11-02 At&T Bell Laboratories Multilevel coding using trellis-coded modulation and reed-solomon codes
US5307377A (en) * 1990-10-09 1994-04-26 U.S. Philips Corporation System for modulating/demodulating digital signals transmitted with encoded modulation
US5363408A (en) * 1992-03-24 1994-11-08 General Instrument Corporation Mode selective quadrature amplitude modulation communication system
US5410555A (en) * 1991-11-15 1995-04-25 Sony Corporation Viterbi decoding apparatus
US5422894A (en) * 1993-06-25 1995-06-06 Oki Electric Industry Co., Ltd. Real-time convolutional decoder with block synchronizing function
US5438590A (en) * 1993-05-24 1995-08-01 Comstream Corporation Transmitting and receiving apparatus and method including punctured convolutional encoding and decoding
WO1995028046A1 (en) * 1994-04-08 1995-10-19 Echelon Corporation Method and apparatus for robust communications based upon angular modulation
US5465267A (en) * 1993-01-05 1995-11-07 Nec Corporation Error-correcting tandem encoding system
US5473621A (en) * 1992-04-16 1995-12-05 At&T Corp. Rotationally invariant coding
US5475716A (en) * 1994-01-18 1995-12-12 Gi Corporation Method for communicating block coded digital data with associated synchronization/control data
EP0696108A1 (en) * 1994-07-15 1996-02-07 Kabushiki Kaisha Toshiba Transmission system and apparatus therefor
US5610983A (en) * 1994-09-30 1997-03-11 Thomson Consumer Electronics, Inc. Apparatus for detecting a synchronization component in a satellite transmission system receiver
WO1997028607A2 (en) * 1996-02-02 1997-08-07 Nokia Telecommunications Oy Data transfer method and transceiver equipment
US5666380A (en) * 1993-06-30 1997-09-09 Nec Corporation Digital communication system and method of compressing information
US5862153A (en) * 1995-09-29 1999-01-19 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US5889791A (en) * 1996-08-13 1999-03-30 Motorola, Inc. System, device and method of FEC coding and interleaving for variable length burst transmission
US5943371A (en) * 1997-03-24 1999-08-24 Delco Electronics Corporation Memory efficient time de-interleave, de-puncture and viterbi decoder circuitry
WO1999052282A1 (en) * 1998-04-02 1999-10-14 Sarnoff Corporation Bursty data transmission of compressed video data
US6138261A (en) * 1998-04-29 2000-10-24 Trw Inc. Concatenated coding system for satellite communications
US6157642A (en) * 1997-10-14 2000-12-05 Teledesic Llc Coding system and method for low-earth orbit satellite data communication
US6204725B1 (en) * 1999-01-21 2001-03-20 Fujitsu Limited Circuit for demodulating digital signal undergoing different modulation schemes
US6219388B1 (en) 1997-07-23 2001-04-17 Mitsubishi Denki Kabushiki Kaisha Digital data demodulating device for estimating channel impulse response
US6263466B1 (en) 1998-03-05 2001-07-17 Teledesic Llc System and method of separately coding the header and payload of a data packet for use in satellite data communication
US20020018523A1 (en) * 2000-06-06 2002-02-14 Georgia Tech Research Corporation System and method for object-oriented video processing
US20020026616A1 (en) * 1995-09-29 2002-02-28 Kabushiki Kaisha Toshiba Coding system and decoding system
US6456672B1 (en) * 1997-10-30 2002-09-24 Mitsubishi Denki Kabushiki Kaisha Automatic frequency control communication system
US6493838B1 (en) 1995-09-29 2002-12-10 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US6556632B1 (en) 1997-07-23 2003-04-29 Mitsubishi Denki Kabushiki Kaisha Sequence estimation method and sequence estimator
US20040166817A1 (en) * 2003-01-20 2004-08-26 Mehran Mokhtari System, method and apparatus for burst communications
US20050204258A1 (en) * 2004-02-13 2005-09-15 Broadcom Corporation Encoding system and method for a transmitter in wireless communications
US20050229079A1 (en) * 1995-09-29 2005-10-13 Kabushiki Kaisha Toshiba Coding system and decoding system
KR100611901B1 (ko) * 1999-07-27 2006-08-11 엘지전자 주식회사 통신 시스템의 버스트 에러 제거 회로
US20090051811A1 (en) * 2007-08-24 2009-02-26 Lg Electronics Inc. Digital broadcasting system and method of processing data in digital broadcasting system
US20100050070A1 (en) * 2008-08-22 2010-02-25 Jong Yeul Suh Method for processing a web service in an NRT service and a broadcast receiver
CN102893570A (zh) * 2010-05-14 2013-01-23 波音公司 用于差分编码广播的比特信号结构
US20170033893A1 (en) * 2015-07-28 2017-02-02 Shinwoo KANG Apparatus and method for controlling receiving data

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03270526A (ja) * 1990-03-20 1991-12-02 Fujitsu Ltd 差動符号化における誤り波及抑圧方式
US5113400A (en) * 1990-11-21 1992-05-12 Motorola, Inc. Error detection system
US5241563A (en) * 1992-08-10 1993-08-31 General Instrument Corporation Method and apparatus for communicating interleaved data
JP3581377B2 (ja) * 1993-04-06 2004-10-27 ソニー株式会社 ディジタル多重伝送方法と装置
RU2179365C1 (ru) * 2001-05-22 2002-02-10 Плотников Андрей Алексеевич Способ передачи дискретного сообщения и система для его осуществления
RU2179366C1 (ru) 2001-05-22 2002-02-10 Плотников Андрей Алексеевич Способ передачи дискретного сообщения и система для его осуществления

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3988677A (en) * 1975-06-23 1976-10-26 Nasa Space communication system for compressed data with a concatenated Reed-Solomon-Viterbi coding channel
US4035767A (en) * 1976-03-01 1977-07-12 Ibm Corporation Error correction code and apparatus for the correction of differentially encoded quadrature phase shift keyed data (DQPSK)
US4211996A (en) * 1977-07-19 1980-07-08 Nippon Electric Co., Ltd. Error correction system for differential phase-shift-keying
US4240156A (en) * 1979-03-29 1980-12-16 Doland George D Concatenated error correcting system
US4312070A (en) * 1979-12-07 1982-01-19 Motorola, Inc. Digital encoder-decoder
GB2095517A (en) * 1981-03-23 1982-09-29 Kokusai Denshin Denwa Co Ltd Error correcting method
US4567591A (en) * 1983-08-01 1986-01-28 Gray James S Digital audio satellite transmission system
US4713817A (en) * 1985-04-25 1987-12-15 Codex Corporation Multidimensional, convolutionally coded communication systems
US4907233A (en) * 1988-05-18 1990-03-06 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration VLSI single-chip (255,223) Reed-Solomon encoder with interleaver
US4918446A (en) * 1987-09-30 1990-04-17 Nec Corporation Decoder with reduced synchronization capture time

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3988677A (en) * 1975-06-23 1976-10-26 Nasa Space communication system for compressed data with a concatenated Reed-Solomon-Viterbi coding channel
US4035767A (en) * 1976-03-01 1977-07-12 Ibm Corporation Error correction code and apparatus for the correction of differentially encoded quadrature phase shift keyed data (DQPSK)
US4211996A (en) * 1977-07-19 1980-07-08 Nippon Electric Co., Ltd. Error correction system for differential phase-shift-keying
US4240156A (en) * 1979-03-29 1980-12-16 Doland George D Concatenated error correcting system
US4312070A (en) * 1979-12-07 1982-01-19 Motorola, Inc. Digital encoder-decoder
GB2095517A (en) * 1981-03-23 1982-09-29 Kokusai Denshin Denwa Co Ltd Error correcting method
US4567591A (en) * 1983-08-01 1986-01-28 Gray James S Digital audio satellite transmission system
US4713817A (en) * 1985-04-25 1987-12-15 Codex Corporation Multidimensional, convolutionally coded communication systems
US4918446A (en) * 1987-09-30 1990-04-17 Nec Corporation Decoder with reduced synchronization capture time
US4907233A (en) * 1988-05-18 1990-03-06 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration VLSI single-chip (255,223) Reed-Solomon encoder with interleaver

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
Bartee, Thomas C., "Data Communications, Networks, and Systems", Howard W. Sams & Co., Inc., 1985, pp. 318-325.
Bartee, Thomas C., Data Communications, Networks, and Systems , Howard W. Sams & Co., Inc., 1985, pp. 318 325. *
Liu et al., Recent Results on the Use of Concatenated Reed Solomon/Viterbi Channel Coding and Data Compression for Space Communications, IEEE Trans. on Comm. vol. COM 32; No. 5, May 1984, pp. 518 523. *
Liu et al., Recent Results on the Use of Concatenated Reed-Solomon/Viterbi Channel Coding and Data Compression for Space Communications, IEEE Trans. on Comm. vol. COM-32; No. 5, May 1984, pp. 518-523.
Sandrin et al., Aeronautical Satellite Data Link Study, COMSAT Technical Review 15, No. 1, 1985, pp. 1 38. *
Sandrin et al., Aeronautical Satellite Data Link Study, COMSAT Technical Review 15, No. 1, 1985, pp. 1-38.

Cited By (100)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5307377A (en) * 1990-10-09 1994-04-26 U.S. Philips Corporation System for modulating/demodulating digital signals transmitted with encoded modulation
US5410555A (en) * 1991-11-15 1995-04-25 Sony Corporation Viterbi decoding apparatus
US5363408A (en) * 1992-03-24 1994-11-08 General Instrument Corporation Mode selective quadrature amplitude modulation communication system
US5258987A (en) * 1992-04-16 1993-11-02 At&T Bell Laboratories Multilevel coding using trellis-coded modulation and reed-solomon codes
US5473621A (en) * 1992-04-16 1995-12-05 At&T Corp. Rotationally invariant coding
US5465267A (en) * 1993-01-05 1995-11-07 Nec Corporation Error-correcting tandem encoding system
US5438590A (en) * 1993-05-24 1995-08-01 Comstream Corporation Transmitting and receiving apparatus and method including punctured convolutional encoding and decoding
US5422894A (en) * 1993-06-25 1995-06-06 Oki Electric Industry Co., Ltd. Real-time convolutional decoder with block synchronizing function
US5666380A (en) * 1993-06-30 1997-09-09 Nec Corporation Digital communication system and method of compressing information
US5475716A (en) * 1994-01-18 1995-12-12 Gi Corporation Method for communicating block coded digital data with associated synchronization/control data
US5828676A (en) * 1994-04-08 1998-10-27 Echelon Corporation Method and apparatus for robust communication based upon angular modulation
WO1995028046A1 (en) * 1994-04-08 1995-10-19 Echelon Corporation Method and apparatus for robust communications based upon angular modulation
EP0696108A1 (en) * 1994-07-15 1996-02-07 Kabushiki Kaisha Toshiba Transmission system and apparatus therefor
US5610983A (en) * 1994-09-30 1997-03-11 Thomson Consumer Electronics, Inc. Apparatus for detecting a synchronization component in a satellite transmission system receiver
US7457994B2 (en) 1995-09-29 2008-11-25 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information using synchronization code
US7469364B2 (en) 1995-09-29 2008-12-23 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information using synchronization code
US5862153A (en) * 1995-09-29 1999-01-19 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US7669108B2 (en) 1995-09-29 2010-02-23 Kabushiki Kaisha Toshiba Coding system and decoding system
US7506221B2 (en) 1995-09-29 2009-03-17 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information using synchronization code
US7487410B2 (en) 1995-09-29 2009-02-03 Kabushiki Kaisha Toshiba Coding system and decoding system using a multiplexed code string
US7475298B2 (en) 1995-09-29 2009-01-06 Kabushiki Kaisha Toshiba Coding system and decoding system
US7472316B2 (en) 1995-09-29 2008-12-30 Kabushiki Kaisha Toshiba Coding system and decoding system
US7472317B2 (en) 1995-09-29 2008-12-30 Kabushiki Kaisha Toshiba Coding system and decoding system
US7464305B2 (en) 1995-09-29 2008-12-09 Kabushiki Kaisha Toshiba Coding system and decoding system using a synchronization code
US6249895B1 (en) 1995-09-29 2001-06-19 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/ storage of information
US7464304B2 (en) 1995-09-29 2008-12-09 Kabushiki Kaisha Toshiba Coding system and decoding system
US7454669B2 (en) 1995-09-29 2008-11-18 Kabushiki Kaisha Toshiba Coding system and decoding system
US20020026616A1 (en) * 1995-09-29 2002-02-28 Kabushiki Kaisha Toshiba Coding system and decoding system
US20020029363A1 (en) * 1995-09-29 2002-03-07 Kabushiki Kaisha Toshiba Coding system and decoding system
US20020035714A1 (en) * 1995-09-29 2002-03-21 Yoshihiro Kikuchi Coding system and decoding system
US6415398B1 (en) 1995-09-29 2002-07-02 Kabushiki Kaisha Toshiba Coding system and decoding system
US7447949B2 (en) 1995-09-29 2008-11-04 Kabushiki Kaisha Toshiba Coding system and decoding system using an input code string
US7441162B2 (en) 1995-09-29 2008-10-21 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information using synchronization code
US6493838B1 (en) 1995-09-29 2002-12-10 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US20030066007A1 (en) * 1995-09-29 2003-04-03 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US7441161B2 (en) 1995-09-29 2008-10-21 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information using synchronization code
US7428668B2 (en) 1995-09-29 2008-09-23 Kabushiki Kaisha Toshiba Coding system and decoding system using an input code string
US20080005642A1 (en) * 1995-09-29 2008-01-03 Kabushiki Kaishi Toshiba Coding system and decoding system
US6823484B2 (en) 1995-09-29 2004-11-23 Kabushiki Kaisha Toshiba Coding system and decoding system
US6857100B2 (en) 1995-09-29 2005-02-15 Kabushiki Kaisha Toshiba Coding system and decoding system
US20070283225A1 (en) * 1995-09-29 2007-12-06 Kabushiki Kaishi Toshiba Coding system and decoding system
US20070283228A1 (en) * 1995-09-29 2007-12-06 Kabushiki Kaishi Toshiba Coding system and decoding system
US20050229079A1 (en) * 1995-09-29 2005-10-13 Kabushiki Kaisha Toshiba Coding system and decoding system
US20050229078A1 (en) * 1995-09-29 2005-10-13 Kabushiki Kaisha Toshiba Coding system and decoding system
US20070283226A1 (en) * 1995-09-29 2007-12-06 Kabushiki Kaishi Toshiba Coding system and decoding system
US7032137B2 (en) 1995-09-29 2006-04-18 Kabushiki Kaisha Toshiba Coding system and decoding system
US7051248B2 (en) 1995-09-29 2006-05-23 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US7051247B2 (en) 1995-09-29 2006-05-23 Kabushiki Kaisha Toshiba Coding system and decoding system
US20070094576A1 (en) * 1995-09-29 2007-04-26 Kabushiki Kaishi Toshiba Coding system and decoding system
US7093170B2 (en) 1995-09-29 2006-08-15 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US20060195764A1 (en) * 1995-09-29 2006-08-31 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US20060195763A1 (en) * 1995-09-29 2006-08-31 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US20060206786A1 (en) * 1995-09-29 2006-09-14 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US20060206785A1 (en) * 1995-09-29 2006-09-14 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US20060206788A1 (en) * 1995-09-29 2006-09-14 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US20060206787A1 (en) * 1995-09-29 2006-09-14 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US20060218462A1 (en) * 1995-09-29 2006-09-28 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US20060218473A1 (en) * 1995-09-29 2006-09-28 Kabushiki Kaisha Toshiba Coding apparatus and decoding apparatus for transmission/storage of information
US20070061680A1 (en) * 1995-09-29 2007-03-15 Kabushiki Kaishi Toshiba Coding system and decoding system
US20070061679A1 (en) * 1995-09-29 2007-03-15 Kabushiki Kaishi Toshiba Coding system and decoding system
US20070061676A1 (en) * 1995-09-29 2007-03-15 Kabushiki Kaishi Toshiba Coding system and decoding system
US20070061678A1 (en) * 1995-09-29 2007-03-15 Kabushiki Kaishi Toshiba Coding system and decoding system
US20070061677A1 (en) * 1995-09-29 2007-03-15 Kabushiki Kaishi Toshiba Coding system and decoding system
US20070094578A1 (en) * 1995-09-29 2007-04-26 Kabushiki Kaishi Toshiba Coding system and decoding system
US20070094577A1 (en) * 1995-09-29 2007-04-26 Kabushiki Kaishi Toshiba Coding system and decoding system
WO1997028607A3 (en) * 1996-02-02 1997-09-18 Nokia Telecommunications Oy Data transfer method and transceiver equipment
WO1997028607A2 (en) * 1996-02-02 1997-08-07 Nokia Telecommunications Oy Data transfer method and transceiver equipment
US5889791A (en) * 1996-08-13 1999-03-30 Motorola, Inc. System, device and method of FEC coding and interleaving for variable length burst transmission
US5943371A (en) * 1997-03-24 1999-08-24 Delco Electronics Corporation Memory efficient time de-interleave, de-puncture and viterbi decoder circuitry
US6556632B1 (en) 1997-07-23 2003-04-29 Mitsubishi Denki Kabushiki Kaisha Sequence estimation method and sequence estimator
US20030081702A1 (en) * 1997-07-23 2003-05-01 Mitsubishi Denki Kabushiki Kaisha Sequence estimation method and sequence estimator
US6996196B2 (en) 1997-07-23 2006-02-07 Mitsubishi Denki Kabushiki Kaisha Sequence estimation method and sequence estimator
US6219388B1 (en) 1997-07-23 2001-04-17 Mitsubishi Denki Kabushiki Kaisha Digital data demodulating device for estimating channel impulse response
US6157642A (en) * 1997-10-14 2000-12-05 Teledesic Llc Coding system and method for low-earth orbit satellite data communication
US6456672B1 (en) * 1997-10-30 2002-09-24 Mitsubishi Denki Kabushiki Kaisha Automatic frequency control communication system
US6263466B1 (en) 1998-03-05 2001-07-17 Teledesic Llc System and method of separately coding the header and payload of a data packet for use in satellite data communication
WO1999052282A1 (en) * 1998-04-02 1999-10-14 Sarnoff Corporation Bursty data transmission of compressed video data
US6459811B1 (en) 1998-04-02 2002-10-01 Sarnoff Corporation Bursty data transmission of compressed video data
US6138261A (en) * 1998-04-29 2000-10-24 Trw Inc. Concatenated coding system for satellite communications
US6204725B1 (en) * 1999-01-21 2001-03-20 Fujitsu Limited Circuit for demodulating digital signal undergoing different modulation schemes
KR100611901B1 (ko) * 1999-07-27 2006-08-11 엘지전자 주식회사 통신 시스템의 버스트 에러 제거 회로
US20020018523A1 (en) * 2000-06-06 2002-02-14 Georgia Tech Research Corporation System and method for object-oriented video processing
US6882686B2 (en) * 2000-06-06 2005-04-19 Georgia Tech Research Corporation System and method for object-oriented video processing
US20040166817A1 (en) * 2003-01-20 2004-08-26 Mehran Mokhtari System, method and apparatus for burst communications
US20050204258A1 (en) * 2004-02-13 2005-09-15 Broadcom Corporation Encoding system and method for a transmitter in wireless communications
US8996949B2 (en) * 2004-02-13 2015-03-31 Broadcom Corporation Encoding system and method for a transmitter in wireless communications
US20140105202A1 (en) * 2004-02-13 2014-04-17 Broadcom Corporation Encoding system and method for a transmitter in wireless communications
US20090051811A1 (en) * 2007-08-24 2009-02-26 Lg Electronics Inc. Digital broadcasting system and method of processing data in digital broadcasting system
US8386893B2 (en) * 2007-08-24 2013-02-26 Lg Electronics Inc. Digital broadcasting system and method of processing data in digital broadcasting system
US8422509B2 (en) 2008-08-22 2013-04-16 Lg Electronics Inc. Method for processing a web service in an NRT service and a broadcast receiver
US8767764B2 (en) 2008-08-22 2014-07-01 Lg Electronics Inc. Method for processing a web service in an NRT service and a broadcast receiver
US20100050070A1 (en) * 2008-08-22 2010-02-25 Jong Yeul Suh Method for processing a web service in an NRT service and a broadcast receiver
US9071586B2 (en) 2008-08-22 2015-06-30 Lg Electronics Inc. Method for processing a web service in an NRT service and a broadcast receiver
US9432724B2 (en) 2008-08-22 2016-08-30 Lg Electronics Inc. Method for processing a web service in an NRT service and a broadcast receiver
US10349146B2 (en) 2008-08-22 2019-07-09 Lg Electronics, Inc. Method for processing a web service in an NRT service and a broadcast receiver
CN102893570A (zh) * 2010-05-14 2013-01-23 波音公司 用于差分编码广播的比特信号结构
CN102893570B (zh) * 2010-05-14 2016-03-09 波音公司 用于差分编码广播的比特信号结构
US20170033893A1 (en) * 2015-07-28 2017-02-02 Shinwoo KANG Apparatus and method for controlling receiving data
US10461888B2 (en) * 2015-07-28 2019-10-29 Samsung Electronics Co., Ltd Apparatus and method for controlling receiving data
US10972218B2 (en) 2015-07-28 2021-04-06 Samsung Electronics Co., Ltd Apparatus and method for controlling receiving data

Also Published As

Publication number Publication date
GB2216753A (en) 1989-10-11
FR2628587A1 (ja) 1989-09-15
FR2628587B1 (ja) 1992-11-27
GB8904936D0 (en) 1989-04-12
GB2216753B (en) 1992-11-04

Similar Documents

Publication Publication Date Title
US5117427A (en) Communication system with concatenated coding error correction
US5511096A (en) Quadrature amplitude modulated data for standard bandwidth television channel
US4805174A (en) Error correcting coder/decoder
KR100554322B1 (ko) 복수의 코딩 버스트내에 배치된 ｃｒｃ 비트에 의해 종료 상태가결정되는 컨벌루셔널 디코딩
KR100247373B1 (ko) 신호 송신 장치, 신호 수신 장치, 및 신호 송수신방법
US5416801A (en) Digital signal transmission system based on partitioning of a coded modulation with concatenated codings
KR100491910B1 (ko) 비동일 에러 보호를 갖는 통신 신호를 검출하는 방법 및 장치
US6118825A (en) Digital data transmission device and method, digital data demodulation device and method, and transmission medium
US6085349A (en) Method for selecting cyclic redundancy check polynomials for linear coded systems
US7865812B2 (en) Apparatus and method for determining a detected punctured position in punctured convolutional codes
GB2305088A (en) A coding communication system using Viterbi decoders
US6944206B1 (en) Rate one coding and decoding methods and systems
KR100593580B1 (ko) 디지털 방송 신호 송신 장치 및 방법
US6490260B1 (en) Transmitter with increased traffic throughput in digital mobile telecommunication system and method for operating the same
EP1418699B1 (en) Frame generation for synchronisation
US5428646A (en) Device and method for frame synchronization in a multi-level trellis coding system
JP4067012B2 (ja) デジタル放送信号送信装置及び送信方法
JPH0253330A (ja) 連接符号化誤り訂正通信装置
JP4386103B2 (ja) デジタル放送信号送信装置及び受信方法
JP2710696B2 (ja) 軟判定ビタビ復号方法
US5666380A (en) Digital communication system and method of compressing information
JP3107090B2 (ja) デジタル放送信号送信装置及び方法
JP4396736B2 (ja) デジタル放送信号送信装置及び受信方法
SNYDER et al. Forward error correction for satellite TDMA in the INTELSAT V era
JP4067013B2 (ja) デジタル放送信号送信装置及び送信方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA, A CORP. OF JAPA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:MIYAKE, MAKOTO;KOJIMA, TOSHIHARU;REEL/FRAME:005067/0113

Effective date: 19890417

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12