US4741964A - Structure containing hydrogenated amorphous silicon and process - Google Patents

Structure containing hydrogenated amorphous silicon and process Download PDF

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US4741964A
US4741964A US06/887,167 US88716786A US4741964A US 4741964 A US4741964 A US 4741964A US 88716786 A US88716786 A US 88716786A US 4741964 A US4741964 A US 4741964A
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layer
amorphous silicon
hydrogenated amorphous
hydrogen
concentration
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Ivan Haller
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International Business Machines Corp
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International Business Machines Corp
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Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, ARMONK, NEW YORK 10504, A CORP. OF NEW YORK reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION, ARMONK, NEW YORK 10504, A CORP. OF NEW YORK ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: HALLER, IVAN
Priority to JP62121454A priority patent/JP2677338B2/ja
Priority to EP87109391A priority patent/EP0253201B1/de
Priority to DE8787109391T priority patent/DE3778986D1/de
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H10P14/24—
    • H10P14/2901—
    • H10P14/3211—
    • H10P14/3411—

Definitions

  • the present invention is concerned with a structure for providing semiconductor devices and to a process for fabricating such.
  • the present invention is especially applicable to structures that, in turn, are suitable for providing thin-film field effect transistors.
  • the present invention provides a relatively simple and readily reproducible process for obtaining such structures.
  • the semiconductor material is a deposited thin film (as opposed to bulk grown crystal) material, for example, hydrogenated amorphous silicon, or crystalline silicon formed by the high temperature or laser annealing of the amorphous material.
  • a deposited thin film as opposed to bulk grown crystal
  • hydrogenated amorphous silicon or crystalline silicon formed by the high temperature or laser annealing of the amorphous material.
  • One particular application being thin-film field effect transistors.
  • a typical thin-film field effect transistor includes an electrically conductive gate above an insulating substrate such as glass, a gate insulator such as silicon dioxide above the gate, a hydrogenated amorphous silicon layer above the gate insulator, and electrically conductive source and drain regions above the amorphous silicon. It is desired for such devices to control the current such that when the device is in the "on” state, as high a current as possible exists, but when the device is in the "off” state, the residual current is as small as possible. To achieve such it is desirable to provide doping in the amorphous silicon layer beneath the source and drain regions, but to limit the doping in the amorphous silicon layer in the region between the source and drain regions referred to as the "channel"
  • such patterns are fabricated by plasma depositing a layer of uniform thickness hydrogenated amorphous silicon, protecting the desired thicker part of the pattern with a resist image, and etching the unprotected area for a predetermined length of time.
  • meticulous control of conditions and of timing is required. Such is relatively expensive and often not practical to implement. Accordingly, these methods are not very well developed and not convenient from a manufacturing or commercial viewpoint.
  • the present invention is concerned with a structure and process capable of providing a patterned multilevel structure that is relatively simple and readily reproducible.
  • the structure of the present invention includes a substrate (1) that has at least one major surface area. Above the major surface area of the substrate is a first layer (4) of hydrogenated amorphous silicon.
  • the first layer of hydrogenated amorphous silicon contains a first concentration of hydrogen incorporated therein.
  • Located above the first layer of hydrogenated amorphous silicon is a second layer (5) of hydrogenated amorphous silicon.
  • the second layer of hydrogenated amorphous silicon has a second concentration of hydrogen incorporated therein that differs from the concentration of hydrogen incorporated in the first layer.
  • the present invention is concerned with a process for fabricating a structure.
  • the process includes providing a substrate (1) having at least one major surface area. Above the major surface area of the substrate is provided a first layer (4) of hydrogenated amorphous silicon.
  • the first layer of hydrogenated amorphous silicon has a first concentration of hydrogen incorporated therein.
  • a second layer (5) of hydrogenated amorphous silicon is provided above the first layer. This second layer has a second concentration of hydrogen incorporated therein that differs from the concentration of hydrogen incorporated in the first layer.
  • a vertically differentiated pattern is provided by selectively etching the layer of hydrogenated amorphous silicon having the higher hydrogen concentration of the first and second layers.
  • FIGS. 1 to 4 are schematic diagrams showing the structure in various stages of processing in accordance with the present invention.
  • FIGS. 5 to 8 illustrate the application of the invention in fabricating thin film field effect transistors.
  • FIG. 1 In FIG. 1 is illustrated a substrate (1).
  • the substrate (1) includes any suitable substrate material such as glass (e.g., quartz), sapphire, silicon, metal, or metallized substrate.
  • suitable substrate material such as glass (e.g., quartz), sapphire, silicon, metal, or metallized substrate.
  • a first layer (4) of hydrogenated amorphous silicon containing a first concentration of hydrogen incorporated therein is deposited (see FIG. 2).
  • hydrogenated amorphous silicon layer (4) contains a relatively low concentration of hydrogen as compared to the subsequently to be applied hydrogenated amorphous silicon layer (5).
  • the hydrogenated amorphous silicon layer (4) can be provided by well-known plasma deposition techniques such as placing the structure in a plasma reaction chamber using silane as the source of the hydrogenated amorphous silicon.
  • a typical power density is about 5 milliwatts/cm 2 of combined surface area of the electrodes exposed to the plasma.
  • the power source is typically operated at a radio frequency of about 13.6 megahertz.
  • the preferred source of the hydrogenated amorphous silicon is 100% silane, such, if desired, can be diluted with an inert gas such as helium, neon, argon, and krypton or diluted with hydrogen. It is known that the presence of hydrogen in the diluent gas will not significantly effect the amount of hydrogen deposited along with the silicon in the hydrogenated amorphous silicon layer.
  • the second layer (5) of hydrogenated amorphous silicon is deposited (see FIG. 3).
  • the second layer of hydrogenated amorphous silicon (5) contains the greater quantity of hydrogen of the two layers.
  • the increased quantity of incorporated hydrogen can be achieved by the same plasma deposition employed for the first hydrogenated amorphous silicon layer, except by employing a reduced temperature and/or increased pressure.
  • the temperature employed for the second hydrogenated amorphous silicon layer is reduced to about room temperature to about 200° C. and preferably about 125° C. while employing the same pressure as used for depositing the first hydrogenated amorphous silicon layer (4).
  • thicknesses of the two layers may be chosen at will within the limits of practicality of thin films depositions. Important benefits of the present invention as compared to the prior art will, however, derive when the second layer is thicker or not much thinner than the first layer and when both layers are relatively thin.
  • typical thicknesses of the first hydrogenated amorphous silicon layer (4) are about 100 to about 50,000 angstroms and preferably about 100 to about 1,000 angstroms.
  • Typical thicknesses of hydrogenated amorphous silicon layer (5) are about 50 to about 50,000 angstroms and preferably about 100 to about 1,000 angstroms.
  • the higher concentration of hydrogen in the second hydrogenated amorphous silicon layer results in that layer being more rapidly etched, thereby making it possible to accurately etch down to the interface with first hydrogenated layer (4) allowing for a well-defined remaining thickness as well as a flat surface.
  • the second hydrogenated amorphous silicon layer (5) can be patterned (see FIG. 4), for instance, by covering the layer (5) with a photoresist material (not shown) exposing the photoresist material to imaging radiation in a predetermined pattern and, thereafter, removing that portion of the photoresist material exposed to the imaging radiation in the case of a positive photoresist material and that material not exposed to radiation in the case of a negative photoresist material as is well-known in the art.
  • a photoresist material not shown
  • Suitable wet chemical etching compositions include strongly alkaline solutions such as alkali metal hydroxide solutions and, in particular, potassium hydroxide and sodium hydroxide. Such compositions preferably are 1 molar or higher.
  • the etching is preferably carried out at normal room temperatures. When more elevated temperatures are employed, the pH of the solution can be somewhat less than that obtained from a 1 molar solution, such as down to about 12.5.
  • other methods of etching can be employed, although not preferred, such as plasma etching or reactive ion etching. The most pronounced effects from the present invention are achieved when employing a wet chemical etching.
  • the etching can be carried out such that the etch rate will slow down as the interface to layer (4) is reached, thereby allowing a well-defined remaining thickness and a planar surface.
  • the level of hydrogen in hydrogenated layers (4) and (5) can now be equilibrated once layer (5) has been patterned by merely raising the temperature of the substrate to that at which the first layer was formed, such as at about 225° C. to about 325° C. and preferably at about 275° C. and maintain the substrate there for a sufficient amount of time in order to lower the hydrogen content in the second layer. This usually takes about 1 to about 30 minutes.
  • FIGS. 5 to 8 illustrates the application of the present invention in fabricating thin film effect transistors.
  • FIG. 5 is illustrated a substrate (1) containing an electrically conductive gate (2) thereon and a gate insulator (3).
  • the substrate (1) includes any suitable substrate material such as glass (e.g., quartz), sapphire, silicon, metal, or metallized substrate.
  • suitable substrate material such as glass (e.g., quartz), sapphire, silicon, metal, or metallized substrate.
  • the gate (2) is of a metallic-type high electrical conductivity material, preferably a metal such as chromium, nickel, molybdenum, and aluminum, as well as non-metallic materials such as highly doped polycrystalline silicon or intermetallic silicides which, nevertheless, have electrical conductivities of the magnitude generally possessed by metals.
  • the gate (2) is defined by well-known photolithographical techniques that need not be discussed herein in any detail.
  • a gate insulator (3) such as silicon dioxide and silicon nitride.
  • a first layer (4) of hydrogenated amorphous silicon containing a first concentration of hydrogen incorporated therein is deposited (see FIG. 6).
  • hydrogenated amorphous silicon layer (4) contains a relatively low concentration of hydrogen as compared to the subsequently to be applied hydrogenated amorphous silicon layer (5).
  • the hydrogenated amorphous silicon layer (4) can be provided by well-known plasma deposition techniques such as placing the structure in a plasma reaction chamber using silane as the source of the hydrogenated amorphous silicon.
  • a typical power density is about 5 milliwatts/cm 2 of combined surface area of the electrodes exposed to the plasma.
  • the power source is typically operated at a radio frequency of about 13.6 megahertz.
  • the preferred source of the hydrogenated amorphous silicon is 100% silane, such, if desired, can be diluted with an inert gas such as helium, neon, argon, and krypton or diluted with hydrogen. It is known that the presence of hydrogen in the diluent gas will not significantly effect the amount of hydrogen deposited along with the silicon in the hydrogenated amorphous silicon layer.
  • the second layer (5) of hydrogenated amorphous silicon is deposited (see FIG. 3).
  • the second layer of hydrogenated amorphous silicon (5) contains the greater quantity of hydrogen of the two layers.
  • the increased quantity of incorporated hydrogen can be achieved by the same plasma deposition employed for the first hydrogenated amorphous silicon layer, except by employing a reduced temperature and/or increased pressure.
  • the temperature employed for the second hydrogenated amorphous silicon layer is reduced to about room temperature to about 200° C. and preferably about 125° C. while employing the same pressure as used for depositing the first hydrogenated amorphous silicon layer (4).
  • the thickness of the two layers may be chosen at will within the limits of practicality of thin films depositions. Important benefits of the present invention as compared to the prior art will, however, derive when thc second layer is thicker or not much thinner than the first layer and when both layers are relatively thin.
  • typical thicknesses of the first hydrogenated amorphous silicon layer (4) are about 100 to about 50,000 angstroms and preferably about 100 to about 1,000 angstroms.
  • Typical thicknesses of hydrogenated amorphous silicon layer (5) are about 50 to about 50,000 angstroms and preferably about 100 to about 1,000 angstroms.
  • the second hydrogenated amorphous silicon layer is also doped in order to increase its conductivity.
  • a suitable n-type dopant is phosphorous and a suitable p-type dopant is boron.
  • the phosphorous can be incorporated, fcr instance, by including in the plasma gas, phosphine (PH 3 ), such as in amounts of a few ppm to about 1% by volume of the gaseous mixture employed.
  • the boron can be provided by using a gaseous boron-containing compound such as diborane (B 2 H 6 ).
  • the higher concentration of hydrogen in the second hydrogenated amorphous silicon layer results in that layer being more rapidly etched, thereby making it possible to accurately etch down to the interface with first hydrogenated layer (4) allowing for a well-defined remaining thickness as well as a flat surface.
  • the second hydrogenated amorphous silicon layer (5) can be patterned (see FIG. 4), for instance, by covering the layer (5) with a photoresist material (not shown) exposing the photoresist material to imaging radiation in a predetermined pattern and, thereafter, removing that portion of the photoresist material exposed to the imaging radiation in the case of a positive photoresist material and that material not exposed to radiation in the case of a negative photoresist material as is well-known in the art.
  • a photoresist material not shown
  • Suitable wet chemical etching compositions include strongly alkaline solutions such as alkali metal hydroxide solutions and, in particular, potassium hydroxide and sodium hydroxide. Such compositions preferably are 1 molar or higher.
  • the etching is preferably carried out at normal room temperatures. When more elevated temperatures are employed, the pH of the solution can be somewhat less than that obtained from a 1 molar solution, such as down to about 12.5.
  • other methods of etching can be employed, although not preferred, such as plasma etching or reactive ion etching. The most pronounced effects from the present invention are achieved when employing a wet chemical etching.
  • the etching can be carried out such that the etch rate will slow down as the interface to layer (4) is reached, thereby allowing a well-defined remaining thickness and a planar surface.
  • That portion of layer (5) that remains is patterned so as to be beneath source and drain regions to be subsequently provided, while that portion of layer (5) removed corresponds to the area between the source and drain regions to be provided, referred to as the "channel". Accordingly, by proper doping of layer (5), increased conductivity beneath the source and drain regions can be obtained without concomitantly increasing the conductivity between the source and drain regions when the device is in the "off" state. This, in turn, allows for improved ohmic contact. In other words, increased ohmic contact is provided by the doping between the hydrogenated amorphous silicon and the source and drain regions, but the highly doped amorphous layer is cleanly removed from the channel region between the source and drain regions.
  • Source and drain regions (7) and (8) are provided by well-known techniques, for example, by depositing a blanket metallization (not shown) prior to application of the photoresist on top of layer (5) and patterning it with the mask as used for patterning layer (5).
  • the level of hydrogen in hydrogenated layers (4) and (5) can be equilibrated once layer (5) has been patterned by merely raising the temperature of the substrate to that at which the first layer was formed, such as at about 225° C. to about 325° C. and preferably at about 275° C. and maintain the substrate there for a sufficient amount of time in order to lower the hydrogen content in the second layer. This usually takes about 1 to about 30 minutes.
  • the etched region can be covered with a passivation or encapsulation layer (6).
  • the present invention has been described with respect to only two different layers of hydrogenated amorphous silicon, it is understood that the present invention can be carried out with three or more different layers or thicknesses of hydrogenated amorphous silicon, each having a different concentration of hydrogen as compared to the layer juxtaposed it.
  • a number of samples are prepared whereby hydrogenated amorphous silicon is deposited using the same apparatus and conditions, except for the substrate temperature and the presence or absence of dopant gas. No significant variation in the deposition rate of the hydrogenated amorphous silicon layer is observed.
  • the substrate employed is glass
  • the pressure of the plasma deposition is about 230 millitorr
  • the power density is about 5 milliwatts/cm 2 of combined surface area of the electrodes exposed to the plasma
  • the power is radio frequency of about 13.6 megahertz.
  • the dopant gas when employed, is phosphine.
  • the hydrogen content and distribution of the samples are obtained from infrared spectra.
  • the samples are protected with groove-pattern wax and are held in a jig that allows simultaneous immersion into the etchant of all of the samples.
  • the etchant is a continuously stirred 1 molar solution of potassium hydroxide at 23° C.
  • the depth of grooves etched into the hydrogenated amorphous silicon in three different etch times is measured with a "Tencor Alphastep" instrument. The results obtained are presented hereinbelow in Table I.
  • the lowering of the substrate temperature results in a significant increase of the total hydrogen content, of the relative intensity of the hydrogen bending modes (a measure of the fraction of hydrogen in other than monohydride form), and of the etch rate.
  • the addition of the dopant, even without a temperature change, has a similar, although much smaller, effect.
  • a set of samples similar to those in Example 1, are prepared.
  • the samples are etched in a dry etching apparatus, in the plasma etching mode, at various power levels, at a pressure of 30 mtorr, in an 80:20 mixture of carbon tetrafluoride and oxygen.
  • High hydrogen content samples are found to etch at rates approximately 60 percent higher than corresponding identically doped samples with low hydrogen content.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Weting (AREA)
  • Thin Film Transistor (AREA)
  • Drying Of Semiconductors (AREA)
US06/887,167 1986-07-17 1986-07-17 Structure containing hydrogenated amorphous silicon and process Expired - Fee Related US4741964A (en)

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Application Number Priority Date Filing Date Title
US06/887,167 US4741964A (en) 1986-07-17 1986-07-17 Structure containing hydrogenated amorphous silicon and process
JP62121454A JP2677338B2 (ja) 1986-07-17 1987-05-20 シリコン・デバイスの製造方法
EP87109391A EP0253201B1 (de) 1986-07-17 1987-06-30 Hydrogeniertes amorphes Silizium beinhaltende Struktur und Verfahren zu ihrer Herstellung
DE8787109391T DE3778986D1 (de) 1986-07-17 1987-06-30 Hydrogeniertes amorphes silizium beinhaltende struktur und verfahren zu ihrer herstellung.

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EP (1) EP0253201B1 (de)
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US4905072A (en) * 1981-11-13 1990-02-27 Canon Kabushiki Kaisha Semiconductor element
US4951113A (en) * 1988-11-07 1990-08-21 Xerox Corporation Simultaneously deposited thin film CMOS TFTs and their method of fabrication
US5045905A (en) * 1988-03-23 1991-09-03 Nippon Precision Circuits Ltd. Amorphous silicon thin film transistor
US5273920A (en) * 1992-09-02 1993-12-28 General Electric Company Method of fabricating a thin film transistor using hydrogen plasma treatment of the gate dielectric/semiconductor layer interface
US5281546A (en) * 1992-09-02 1994-01-25 General Electric Company Method of fabricating a thin film transistor using hydrogen plasma treatment of the intrinsic silicon/doped layer interface
US5387542A (en) * 1991-11-14 1995-02-07 Kanegafuchi Chemical Industry Co., Ltd. Polycrystalline silicon thin film and low temperature fabrication method thereof
US5404007A (en) * 1992-05-29 1995-04-04 The United States Of America As Represented By The Secretary Of The Air Force Radiation resistant RLG detector systems
US5510640A (en) * 1990-04-17 1996-04-23 Cannon Kabushiki Kaisha Semiconductor device and process for preparing the same
US5602403A (en) * 1991-03-01 1997-02-11 The United States Of America As Represented By The Secretary Of The Navy Ion Implantation buried gate insulator field effect transistor
US5856775A (en) * 1996-06-18 1999-01-05 Pico Systems, Inc. Programmable thin film filament resistor and method of constructing same
US6049091A (en) * 1996-07-01 2000-04-11 Nec Corporation High electron mobility transistor
US6444326B1 (en) * 1999-03-05 2002-09-03 Restek Corporation Surface modification of solid supports through the thermal decomposition and functionalization of silanes
US20060011995A1 (en) * 1990-02-06 2006-01-19 Semiconductor Energy Laboratory Co., Ltd. Method of forming an oxide film
US20070197005A1 (en) * 2006-02-21 2007-08-23 Yuh-Hwa Chang Delamination resistant semiconductor film and method for forming the same
US20110177349A1 (en) * 2004-12-13 2011-07-21 Smith David A Process for the modification of substrate surfaces through the deposition of amorphous silicon layers followed by surface functionalization with organic molecules and functionalized structures
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JP2811765B2 (ja) * 1989-07-12 1998-10-15 松下電器産業株式会社 半導体装置およびその製造方法

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EP0253201A2 (de) 1988-01-20
JPS6331169A (ja) 1988-02-09

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